1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved. 4*4882a593Smuzhiyun * Copyright (c) 2015 System Fabric Works, Inc. All rights reserved. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef RXE_OPCODE_H 8*4882a593Smuzhiyun #define RXE_OPCODE_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* 11*4882a593Smuzhiyun * contains header bit mask definitions and header lengths 12*4882a593Smuzhiyun * declaration of the rxe_opcode_info struct and 13*4882a593Smuzhiyun * rxe_wr_opcode_info struct 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun enum rxe_wr_mask { 17*4882a593Smuzhiyun WR_INLINE_MASK = BIT(0), 18*4882a593Smuzhiyun WR_ATOMIC_MASK = BIT(1), 19*4882a593Smuzhiyun WR_SEND_MASK = BIT(2), 20*4882a593Smuzhiyun WR_READ_MASK = BIT(3), 21*4882a593Smuzhiyun WR_WRITE_MASK = BIT(4), 22*4882a593Smuzhiyun WR_LOCAL_MASK = BIT(5), 23*4882a593Smuzhiyun WR_REG_MASK = BIT(6), 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun WR_READ_OR_WRITE_MASK = WR_READ_MASK | WR_WRITE_MASK, 26*4882a593Smuzhiyun WR_READ_WRITE_OR_SEND_MASK = WR_READ_OR_WRITE_MASK | WR_SEND_MASK, 27*4882a593Smuzhiyun WR_WRITE_OR_SEND_MASK = WR_WRITE_MASK | WR_SEND_MASK, 28*4882a593Smuzhiyun WR_ATOMIC_OR_READ_MASK = WR_ATOMIC_MASK | WR_READ_MASK, 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define WR_MAX_QPT (8) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct rxe_wr_opcode_info { 34*4882a593Smuzhiyun char *name; 35*4882a593Smuzhiyun enum rxe_wr_mask mask[WR_MAX_QPT]; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun extern struct rxe_wr_opcode_info rxe_wr_opcode_info[]; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun enum rxe_hdr_type { 41*4882a593Smuzhiyun RXE_LRH, 42*4882a593Smuzhiyun RXE_GRH, 43*4882a593Smuzhiyun RXE_BTH, 44*4882a593Smuzhiyun RXE_RETH, 45*4882a593Smuzhiyun RXE_AETH, 46*4882a593Smuzhiyun RXE_ATMETH, 47*4882a593Smuzhiyun RXE_ATMACK, 48*4882a593Smuzhiyun RXE_IETH, 49*4882a593Smuzhiyun RXE_RDETH, 50*4882a593Smuzhiyun RXE_DETH, 51*4882a593Smuzhiyun RXE_IMMDT, 52*4882a593Smuzhiyun RXE_PAYLOAD, 53*4882a593Smuzhiyun NUM_HDR_TYPES 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun enum rxe_hdr_mask { 57*4882a593Smuzhiyun RXE_LRH_MASK = BIT(RXE_LRH), 58*4882a593Smuzhiyun RXE_GRH_MASK = BIT(RXE_GRH), 59*4882a593Smuzhiyun RXE_BTH_MASK = BIT(RXE_BTH), 60*4882a593Smuzhiyun RXE_IMMDT_MASK = BIT(RXE_IMMDT), 61*4882a593Smuzhiyun RXE_RETH_MASK = BIT(RXE_RETH), 62*4882a593Smuzhiyun RXE_AETH_MASK = BIT(RXE_AETH), 63*4882a593Smuzhiyun RXE_ATMETH_MASK = BIT(RXE_ATMETH), 64*4882a593Smuzhiyun RXE_ATMACK_MASK = BIT(RXE_ATMACK), 65*4882a593Smuzhiyun RXE_IETH_MASK = BIT(RXE_IETH), 66*4882a593Smuzhiyun RXE_RDETH_MASK = BIT(RXE_RDETH), 67*4882a593Smuzhiyun RXE_DETH_MASK = BIT(RXE_DETH), 68*4882a593Smuzhiyun RXE_PAYLOAD_MASK = BIT(RXE_PAYLOAD), 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun RXE_REQ_MASK = BIT(NUM_HDR_TYPES + 0), 71*4882a593Smuzhiyun RXE_ACK_MASK = BIT(NUM_HDR_TYPES + 1), 72*4882a593Smuzhiyun RXE_SEND_MASK = BIT(NUM_HDR_TYPES + 2), 73*4882a593Smuzhiyun RXE_WRITE_MASK = BIT(NUM_HDR_TYPES + 3), 74*4882a593Smuzhiyun RXE_READ_MASK = BIT(NUM_HDR_TYPES + 4), 75*4882a593Smuzhiyun RXE_ATOMIC_MASK = BIT(NUM_HDR_TYPES + 5), 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun RXE_RWR_MASK = BIT(NUM_HDR_TYPES + 6), 78*4882a593Smuzhiyun RXE_COMP_MASK = BIT(NUM_HDR_TYPES + 7), 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun RXE_START_MASK = BIT(NUM_HDR_TYPES + 8), 81*4882a593Smuzhiyun RXE_MIDDLE_MASK = BIT(NUM_HDR_TYPES + 9), 82*4882a593Smuzhiyun RXE_END_MASK = BIT(NUM_HDR_TYPES + 10), 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun RXE_LOOPBACK_MASK = BIT(NUM_HDR_TYPES + 12), 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun RXE_READ_OR_ATOMIC = (RXE_READ_MASK | RXE_ATOMIC_MASK), 87*4882a593Smuzhiyun RXE_WRITE_OR_SEND = (RXE_WRITE_MASK | RXE_SEND_MASK), 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define OPCODE_NONE (-1) 91*4882a593Smuzhiyun #define RXE_NUM_OPCODE 256 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct rxe_opcode_info { 94*4882a593Smuzhiyun char *name; 95*4882a593Smuzhiyun enum rxe_hdr_mask mask; 96*4882a593Smuzhiyun int length; 97*4882a593Smuzhiyun int offset[NUM_HDR_TYPES]; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun extern struct rxe_opcode_info rxe_opcode[RXE_NUM_OPCODE]; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun #endif /* RXE_OPCODE_H */ 103