1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
5*4882a593Smuzhiyun * modify it under the terms of EITHER the GNU General Public License
6*4882a593Smuzhiyun * version 2 as published by the Free Software Foundation or the BSD
7*4882a593Smuzhiyun * 2-Clause License. This program is distributed in the hope that it
8*4882a593Smuzhiyun * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9*4882a593Smuzhiyun * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10*4882a593Smuzhiyun * See the GNU General Public License version 2 for more details at
11*4882a593Smuzhiyun * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License
14*4882a593Smuzhiyun * along with this program available in the file COPYING in the main
15*4882a593Smuzhiyun * directory of this source tree.
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * The BSD 2-Clause License
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
20*4882a593Smuzhiyun * without modification, are permitted provided that the following
21*4882a593Smuzhiyun * conditions are met:
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * - Redistributions of source code must retain the above
24*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
25*4882a593Smuzhiyun * disclaimer.
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
28*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
29*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
30*4882a593Smuzhiyun * provided with the distribution.
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33*4882a593Smuzhiyun * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34*4882a593Smuzhiyun * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35*4882a593Smuzhiyun * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36*4882a593Smuzhiyun * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37*4882a593Smuzhiyun * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38*4882a593Smuzhiyun * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39*4882a593Smuzhiyun * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40*4882a593Smuzhiyun * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41*4882a593Smuzhiyun * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42*4882a593Smuzhiyun * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43*4882a593Smuzhiyun * OF THE POSSIBILITY OF SUCH DAMAGE.
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #ifndef __PVRDMA_VERBS_H__
47*4882a593Smuzhiyun #define __PVRDMA_VERBS_H__
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #include <linux/types.h>
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun union pvrdma_gid {
52*4882a593Smuzhiyun u8 raw[16];
53*4882a593Smuzhiyun struct {
54*4882a593Smuzhiyun __be64 subnet_prefix;
55*4882a593Smuzhiyun __be64 interface_id;
56*4882a593Smuzhiyun } global;
57*4882a593Smuzhiyun };
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun enum pvrdma_link_layer {
60*4882a593Smuzhiyun PVRDMA_LINK_LAYER_UNSPECIFIED,
61*4882a593Smuzhiyun PVRDMA_LINK_LAYER_INFINIBAND,
62*4882a593Smuzhiyun PVRDMA_LINK_LAYER_ETHERNET,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun enum pvrdma_mtu {
66*4882a593Smuzhiyun PVRDMA_MTU_256 = 1,
67*4882a593Smuzhiyun PVRDMA_MTU_512 = 2,
68*4882a593Smuzhiyun PVRDMA_MTU_1024 = 3,
69*4882a593Smuzhiyun PVRDMA_MTU_2048 = 4,
70*4882a593Smuzhiyun PVRDMA_MTU_4096 = 5,
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
pvrdma_mtu_enum_to_int(enum pvrdma_mtu mtu)73*4882a593Smuzhiyun static inline int pvrdma_mtu_enum_to_int(enum pvrdma_mtu mtu)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun switch (mtu) {
76*4882a593Smuzhiyun case PVRDMA_MTU_256: return 256;
77*4882a593Smuzhiyun case PVRDMA_MTU_512: return 512;
78*4882a593Smuzhiyun case PVRDMA_MTU_1024: return 1024;
79*4882a593Smuzhiyun case PVRDMA_MTU_2048: return 2048;
80*4882a593Smuzhiyun case PVRDMA_MTU_4096: return 4096;
81*4882a593Smuzhiyun default: return -1;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
pvrdma_mtu_int_to_enum(int mtu)85*4882a593Smuzhiyun static inline enum pvrdma_mtu pvrdma_mtu_int_to_enum(int mtu)
86*4882a593Smuzhiyun {
87*4882a593Smuzhiyun switch (mtu) {
88*4882a593Smuzhiyun case 256: return PVRDMA_MTU_256;
89*4882a593Smuzhiyun case 512: return PVRDMA_MTU_512;
90*4882a593Smuzhiyun case 1024: return PVRDMA_MTU_1024;
91*4882a593Smuzhiyun case 2048: return PVRDMA_MTU_2048;
92*4882a593Smuzhiyun case 4096:
93*4882a593Smuzhiyun default: return PVRDMA_MTU_4096;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun enum pvrdma_port_state {
98*4882a593Smuzhiyun PVRDMA_PORT_NOP = 0,
99*4882a593Smuzhiyun PVRDMA_PORT_DOWN = 1,
100*4882a593Smuzhiyun PVRDMA_PORT_INIT = 2,
101*4882a593Smuzhiyun PVRDMA_PORT_ARMED = 3,
102*4882a593Smuzhiyun PVRDMA_PORT_ACTIVE = 4,
103*4882a593Smuzhiyun PVRDMA_PORT_ACTIVE_DEFER = 5,
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun enum pvrdma_port_cap_flags {
107*4882a593Smuzhiyun PVRDMA_PORT_SM = 1 << 1,
108*4882a593Smuzhiyun PVRDMA_PORT_NOTICE_SUP = 1 << 2,
109*4882a593Smuzhiyun PVRDMA_PORT_TRAP_SUP = 1 << 3,
110*4882a593Smuzhiyun PVRDMA_PORT_OPT_IPD_SUP = 1 << 4,
111*4882a593Smuzhiyun PVRDMA_PORT_AUTO_MIGR_SUP = 1 << 5,
112*4882a593Smuzhiyun PVRDMA_PORT_SL_MAP_SUP = 1 << 6,
113*4882a593Smuzhiyun PVRDMA_PORT_MKEY_NVRAM = 1 << 7,
114*4882a593Smuzhiyun PVRDMA_PORT_PKEY_NVRAM = 1 << 8,
115*4882a593Smuzhiyun PVRDMA_PORT_LED_INFO_SUP = 1 << 9,
116*4882a593Smuzhiyun PVRDMA_PORT_SM_DISABLED = 1 << 10,
117*4882a593Smuzhiyun PVRDMA_PORT_SYS_IMAGE_GUID_SUP = 1 << 11,
118*4882a593Smuzhiyun PVRDMA_PORT_PKEY_SW_EXT_PORT_TRAP_SUP = 1 << 12,
119*4882a593Smuzhiyun PVRDMA_PORT_EXTENDED_SPEEDS_SUP = 1 << 14,
120*4882a593Smuzhiyun PVRDMA_PORT_CM_SUP = 1 << 16,
121*4882a593Smuzhiyun PVRDMA_PORT_SNMP_TUNNEL_SUP = 1 << 17,
122*4882a593Smuzhiyun PVRDMA_PORT_REINIT_SUP = 1 << 18,
123*4882a593Smuzhiyun PVRDMA_PORT_DEVICE_MGMT_SUP = 1 << 19,
124*4882a593Smuzhiyun PVRDMA_PORT_VENDOR_CLASS_SUP = 1 << 20,
125*4882a593Smuzhiyun PVRDMA_PORT_DR_NOTICE_SUP = 1 << 21,
126*4882a593Smuzhiyun PVRDMA_PORT_CAP_MASK_NOTICE_SUP = 1 << 22,
127*4882a593Smuzhiyun PVRDMA_PORT_BOOT_MGMT_SUP = 1 << 23,
128*4882a593Smuzhiyun PVRDMA_PORT_LINK_LATENCY_SUP = 1 << 24,
129*4882a593Smuzhiyun PVRDMA_PORT_CLIENT_REG_SUP = 1 << 25,
130*4882a593Smuzhiyun PVRDMA_PORT_IP_BASED_GIDS = 1 << 26,
131*4882a593Smuzhiyun PVRDMA_PORT_CAP_FLAGS_MAX = PVRDMA_PORT_IP_BASED_GIDS,
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun enum pvrdma_port_width {
135*4882a593Smuzhiyun PVRDMA_WIDTH_1X = 1,
136*4882a593Smuzhiyun PVRDMA_WIDTH_4X = 2,
137*4882a593Smuzhiyun PVRDMA_WIDTH_8X = 4,
138*4882a593Smuzhiyun PVRDMA_WIDTH_12X = 8,
139*4882a593Smuzhiyun };
140*4882a593Smuzhiyun
pvrdma_width_enum_to_int(enum pvrdma_port_width width)141*4882a593Smuzhiyun static inline int pvrdma_width_enum_to_int(enum pvrdma_port_width width)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun switch (width) {
144*4882a593Smuzhiyun case PVRDMA_WIDTH_1X: return 1;
145*4882a593Smuzhiyun case PVRDMA_WIDTH_4X: return 4;
146*4882a593Smuzhiyun case PVRDMA_WIDTH_8X: return 8;
147*4882a593Smuzhiyun case PVRDMA_WIDTH_12X: return 12;
148*4882a593Smuzhiyun default: return -1;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun enum pvrdma_port_speed {
153*4882a593Smuzhiyun PVRDMA_SPEED_SDR = 1,
154*4882a593Smuzhiyun PVRDMA_SPEED_DDR = 2,
155*4882a593Smuzhiyun PVRDMA_SPEED_QDR = 4,
156*4882a593Smuzhiyun PVRDMA_SPEED_FDR10 = 8,
157*4882a593Smuzhiyun PVRDMA_SPEED_FDR = 16,
158*4882a593Smuzhiyun PVRDMA_SPEED_EDR = 32,
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun struct pvrdma_port_attr {
162*4882a593Smuzhiyun enum pvrdma_port_state state;
163*4882a593Smuzhiyun enum pvrdma_mtu max_mtu;
164*4882a593Smuzhiyun enum pvrdma_mtu active_mtu;
165*4882a593Smuzhiyun u32 gid_tbl_len;
166*4882a593Smuzhiyun u32 port_cap_flags;
167*4882a593Smuzhiyun u32 max_msg_sz;
168*4882a593Smuzhiyun u32 bad_pkey_cntr;
169*4882a593Smuzhiyun u32 qkey_viol_cntr;
170*4882a593Smuzhiyun u16 pkey_tbl_len;
171*4882a593Smuzhiyun u16 lid;
172*4882a593Smuzhiyun u16 sm_lid;
173*4882a593Smuzhiyun u8 lmc;
174*4882a593Smuzhiyun u8 max_vl_num;
175*4882a593Smuzhiyun u8 sm_sl;
176*4882a593Smuzhiyun u8 subnet_timeout;
177*4882a593Smuzhiyun u8 init_type_reply;
178*4882a593Smuzhiyun u8 active_width;
179*4882a593Smuzhiyun u8 active_speed;
180*4882a593Smuzhiyun u8 phys_state;
181*4882a593Smuzhiyun u8 reserved[2];
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun struct pvrdma_global_route {
185*4882a593Smuzhiyun union pvrdma_gid dgid;
186*4882a593Smuzhiyun u32 flow_label;
187*4882a593Smuzhiyun u8 sgid_index;
188*4882a593Smuzhiyun u8 hop_limit;
189*4882a593Smuzhiyun u8 traffic_class;
190*4882a593Smuzhiyun u8 reserved;
191*4882a593Smuzhiyun };
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun struct pvrdma_grh {
194*4882a593Smuzhiyun __be32 version_tclass_flow;
195*4882a593Smuzhiyun __be16 paylen;
196*4882a593Smuzhiyun u8 next_hdr;
197*4882a593Smuzhiyun u8 hop_limit;
198*4882a593Smuzhiyun union pvrdma_gid sgid;
199*4882a593Smuzhiyun union pvrdma_gid dgid;
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun enum pvrdma_ah_flags {
203*4882a593Smuzhiyun PVRDMA_AH_GRH = 1,
204*4882a593Smuzhiyun };
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun enum pvrdma_rate {
207*4882a593Smuzhiyun PVRDMA_RATE_PORT_CURRENT = 0,
208*4882a593Smuzhiyun PVRDMA_RATE_2_5_GBPS = 2,
209*4882a593Smuzhiyun PVRDMA_RATE_5_GBPS = 5,
210*4882a593Smuzhiyun PVRDMA_RATE_10_GBPS = 3,
211*4882a593Smuzhiyun PVRDMA_RATE_20_GBPS = 6,
212*4882a593Smuzhiyun PVRDMA_RATE_30_GBPS = 4,
213*4882a593Smuzhiyun PVRDMA_RATE_40_GBPS = 7,
214*4882a593Smuzhiyun PVRDMA_RATE_60_GBPS = 8,
215*4882a593Smuzhiyun PVRDMA_RATE_80_GBPS = 9,
216*4882a593Smuzhiyun PVRDMA_RATE_120_GBPS = 10,
217*4882a593Smuzhiyun PVRDMA_RATE_14_GBPS = 11,
218*4882a593Smuzhiyun PVRDMA_RATE_56_GBPS = 12,
219*4882a593Smuzhiyun PVRDMA_RATE_112_GBPS = 13,
220*4882a593Smuzhiyun PVRDMA_RATE_168_GBPS = 14,
221*4882a593Smuzhiyun PVRDMA_RATE_25_GBPS = 15,
222*4882a593Smuzhiyun PVRDMA_RATE_100_GBPS = 16,
223*4882a593Smuzhiyun PVRDMA_RATE_200_GBPS = 17,
224*4882a593Smuzhiyun PVRDMA_RATE_300_GBPS = 18,
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun struct pvrdma_ah_attr {
228*4882a593Smuzhiyun struct pvrdma_global_route grh;
229*4882a593Smuzhiyun u16 dlid;
230*4882a593Smuzhiyun u16 vlan_id;
231*4882a593Smuzhiyun u8 sl;
232*4882a593Smuzhiyun u8 src_path_bits;
233*4882a593Smuzhiyun u8 static_rate;
234*4882a593Smuzhiyun u8 ah_flags;
235*4882a593Smuzhiyun u8 port_num;
236*4882a593Smuzhiyun u8 dmac[6];
237*4882a593Smuzhiyun u8 reserved;
238*4882a593Smuzhiyun };
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun enum pvrdma_cq_notify_flags {
241*4882a593Smuzhiyun PVRDMA_CQ_SOLICITED = 1 << 0,
242*4882a593Smuzhiyun PVRDMA_CQ_NEXT_COMP = 1 << 1,
243*4882a593Smuzhiyun PVRDMA_CQ_SOLICITED_MASK = PVRDMA_CQ_SOLICITED |
244*4882a593Smuzhiyun PVRDMA_CQ_NEXT_COMP,
245*4882a593Smuzhiyun PVRDMA_CQ_REPORT_MISSED_EVENTS = 1 << 2,
246*4882a593Smuzhiyun };
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun struct pvrdma_qp_cap {
249*4882a593Smuzhiyun u32 max_send_wr;
250*4882a593Smuzhiyun u32 max_recv_wr;
251*4882a593Smuzhiyun u32 max_send_sge;
252*4882a593Smuzhiyun u32 max_recv_sge;
253*4882a593Smuzhiyun u32 max_inline_data;
254*4882a593Smuzhiyun u32 reserved;
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun enum pvrdma_sig_type {
258*4882a593Smuzhiyun PVRDMA_SIGNAL_ALL_WR,
259*4882a593Smuzhiyun PVRDMA_SIGNAL_REQ_WR,
260*4882a593Smuzhiyun };
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun enum pvrdma_qp_type {
263*4882a593Smuzhiyun PVRDMA_QPT_SMI,
264*4882a593Smuzhiyun PVRDMA_QPT_GSI,
265*4882a593Smuzhiyun PVRDMA_QPT_RC,
266*4882a593Smuzhiyun PVRDMA_QPT_UC,
267*4882a593Smuzhiyun PVRDMA_QPT_UD,
268*4882a593Smuzhiyun PVRDMA_QPT_RAW_IPV6,
269*4882a593Smuzhiyun PVRDMA_QPT_RAW_ETHERTYPE,
270*4882a593Smuzhiyun PVRDMA_QPT_RAW_PACKET = 8,
271*4882a593Smuzhiyun PVRDMA_QPT_XRC_INI = 9,
272*4882a593Smuzhiyun PVRDMA_QPT_XRC_TGT,
273*4882a593Smuzhiyun PVRDMA_QPT_MAX,
274*4882a593Smuzhiyun };
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun enum pvrdma_qp_create_flags {
277*4882a593Smuzhiyun PVRDMA_QP_CREATE_IPOPVRDMA_UD_LSO = 1 << 0,
278*4882a593Smuzhiyun PVRDMA_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 1 << 1,
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun enum pvrdma_qp_attr_mask {
282*4882a593Smuzhiyun PVRDMA_QP_STATE = 1 << 0,
283*4882a593Smuzhiyun PVRDMA_QP_CUR_STATE = 1 << 1,
284*4882a593Smuzhiyun PVRDMA_QP_EN_SQD_ASYNC_NOTIFY = 1 << 2,
285*4882a593Smuzhiyun PVRDMA_QP_ACCESS_FLAGS = 1 << 3,
286*4882a593Smuzhiyun PVRDMA_QP_PKEY_INDEX = 1 << 4,
287*4882a593Smuzhiyun PVRDMA_QP_PORT = 1 << 5,
288*4882a593Smuzhiyun PVRDMA_QP_QKEY = 1 << 6,
289*4882a593Smuzhiyun PVRDMA_QP_AV = 1 << 7,
290*4882a593Smuzhiyun PVRDMA_QP_PATH_MTU = 1 << 8,
291*4882a593Smuzhiyun PVRDMA_QP_TIMEOUT = 1 << 9,
292*4882a593Smuzhiyun PVRDMA_QP_RETRY_CNT = 1 << 10,
293*4882a593Smuzhiyun PVRDMA_QP_RNR_RETRY = 1 << 11,
294*4882a593Smuzhiyun PVRDMA_QP_RQ_PSN = 1 << 12,
295*4882a593Smuzhiyun PVRDMA_QP_MAX_QP_RD_ATOMIC = 1 << 13,
296*4882a593Smuzhiyun PVRDMA_QP_ALT_PATH = 1 << 14,
297*4882a593Smuzhiyun PVRDMA_QP_MIN_RNR_TIMER = 1 << 15,
298*4882a593Smuzhiyun PVRDMA_QP_SQ_PSN = 1 << 16,
299*4882a593Smuzhiyun PVRDMA_QP_MAX_DEST_RD_ATOMIC = 1 << 17,
300*4882a593Smuzhiyun PVRDMA_QP_PATH_MIG_STATE = 1 << 18,
301*4882a593Smuzhiyun PVRDMA_QP_CAP = 1 << 19,
302*4882a593Smuzhiyun PVRDMA_QP_DEST_QPN = 1 << 20,
303*4882a593Smuzhiyun PVRDMA_QP_ATTR_MASK_MAX = PVRDMA_QP_DEST_QPN,
304*4882a593Smuzhiyun };
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun enum pvrdma_qp_state {
307*4882a593Smuzhiyun PVRDMA_QPS_RESET,
308*4882a593Smuzhiyun PVRDMA_QPS_INIT,
309*4882a593Smuzhiyun PVRDMA_QPS_RTR,
310*4882a593Smuzhiyun PVRDMA_QPS_RTS,
311*4882a593Smuzhiyun PVRDMA_QPS_SQD,
312*4882a593Smuzhiyun PVRDMA_QPS_SQE,
313*4882a593Smuzhiyun PVRDMA_QPS_ERR,
314*4882a593Smuzhiyun };
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun enum pvrdma_mig_state {
317*4882a593Smuzhiyun PVRDMA_MIG_MIGRATED,
318*4882a593Smuzhiyun PVRDMA_MIG_REARM,
319*4882a593Smuzhiyun PVRDMA_MIG_ARMED,
320*4882a593Smuzhiyun };
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun enum pvrdma_mw_type {
323*4882a593Smuzhiyun PVRDMA_MW_TYPE_1 = 1,
324*4882a593Smuzhiyun PVRDMA_MW_TYPE_2 = 2,
325*4882a593Smuzhiyun };
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun struct pvrdma_srq_attr {
328*4882a593Smuzhiyun u32 max_wr;
329*4882a593Smuzhiyun u32 max_sge;
330*4882a593Smuzhiyun u32 srq_limit;
331*4882a593Smuzhiyun u32 reserved;
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun struct pvrdma_qp_attr {
335*4882a593Smuzhiyun enum pvrdma_qp_state qp_state;
336*4882a593Smuzhiyun enum pvrdma_qp_state cur_qp_state;
337*4882a593Smuzhiyun enum pvrdma_mtu path_mtu;
338*4882a593Smuzhiyun enum pvrdma_mig_state path_mig_state;
339*4882a593Smuzhiyun u32 qkey;
340*4882a593Smuzhiyun u32 rq_psn;
341*4882a593Smuzhiyun u32 sq_psn;
342*4882a593Smuzhiyun u32 dest_qp_num;
343*4882a593Smuzhiyun u32 qp_access_flags;
344*4882a593Smuzhiyun u16 pkey_index;
345*4882a593Smuzhiyun u16 alt_pkey_index;
346*4882a593Smuzhiyun u8 en_sqd_async_notify;
347*4882a593Smuzhiyun u8 sq_draining;
348*4882a593Smuzhiyun u8 max_rd_atomic;
349*4882a593Smuzhiyun u8 max_dest_rd_atomic;
350*4882a593Smuzhiyun u8 min_rnr_timer;
351*4882a593Smuzhiyun u8 port_num;
352*4882a593Smuzhiyun u8 timeout;
353*4882a593Smuzhiyun u8 retry_cnt;
354*4882a593Smuzhiyun u8 rnr_retry;
355*4882a593Smuzhiyun u8 alt_port_num;
356*4882a593Smuzhiyun u8 alt_timeout;
357*4882a593Smuzhiyun u8 reserved[5];
358*4882a593Smuzhiyun struct pvrdma_qp_cap cap;
359*4882a593Smuzhiyun struct pvrdma_ah_attr ah_attr;
360*4882a593Smuzhiyun struct pvrdma_ah_attr alt_ah_attr;
361*4882a593Smuzhiyun };
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun enum pvrdma_send_flags {
364*4882a593Smuzhiyun PVRDMA_SEND_FENCE = 1 << 0,
365*4882a593Smuzhiyun PVRDMA_SEND_SIGNALED = 1 << 1,
366*4882a593Smuzhiyun PVRDMA_SEND_SOLICITED = 1 << 2,
367*4882a593Smuzhiyun PVRDMA_SEND_INLINE = 1 << 3,
368*4882a593Smuzhiyun PVRDMA_SEND_IP_CSUM = 1 << 4,
369*4882a593Smuzhiyun PVRDMA_SEND_FLAGS_MAX = PVRDMA_SEND_IP_CSUM,
370*4882a593Smuzhiyun };
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun enum pvrdma_access_flags {
373*4882a593Smuzhiyun PVRDMA_ACCESS_LOCAL_WRITE = 1 << 0,
374*4882a593Smuzhiyun PVRDMA_ACCESS_REMOTE_WRITE = 1 << 1,
375*4882a593Smuzhiyun PVRDMA_ACCESS_REMOTE_READ = 1 << 2,
376*4882a593Smuzhiyun PVRDMA_ACCESS_REMOTE_ATOMIC = 1 << 3,
377*4882a593Smuzhiyun PVRDMA_ACCESS_MW_BIND = 1 << 4,
378*4882a593Smuzhiyun PVRDMA_ZERO_BASED = 1 << 5,
379*4882a593Smuzhiyun PVRDMA_ACCESS_ON_DEMAND = 1 << 6,
380*4882a593Smuzhiyun PVRDMA_ACCESS_FLAGS_MAX = PVRDMA_ACCESS_ON_DEMAND,
381*4882a593Smuzhiyun };
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun int pvrdma_query_device(struct ib_device *ibdev,
384*4882a593Smuzhiyun struct ib_device_attr *props,
385*4882a593Smuzhiyun struct ib_udata *udata);
386*4882a593Smuzhiyun int pvrdma_query_port(struct ib_device *ibdev, u8 port,
387*4882a593Smuzhiyun struct ib_port_attr *props);
388*4882a593Smuzhiyun int pvrdma_query_gid(struct ib_device *ibdev, u8 port,
389*4882a593Smuzhiyun int index, union ib_gid *gid);
390*4882a593Smuzhiyun int pvrdma_query_pkey(struct ib_device *ibdev, u8 port,
391*4882a593Smuzhiyun u16 index, u16 *pkey);
392*4882a593Smuzhiyun enum rdma_link_layer pvrdma_port_link_layer(struct ib_device *ibdev,
393*4882a593Smuzhiyun u8 port);
394*4882a593Smuzhiyun int pvrdma_modify_device(struct ib_device *ibdev, int mask,
395*4882a593Smuzhiyun struct ib_device_modify *props);
396*4882a593Smuzhiyun int pvrdma_modify_port(struct ib_device *ibdev, u8 port,
397*4882a593Smuzhiyun int mask, struct ib_port_modify *props);
398*4882a593Smuzhiyun int pvrdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma);
399*4882a593Smuzhiyun int pvrdma_alloc_ucontext(struct ib_ucontext *uctx, struct ib_udata *udata);
400*4882a593Smuzhiyun void pvrdma_dealloc_ucontext(struct ib_ucontext *context);
401*4882a593Smuzhiyun int pvrdma_alloc_pd(struct ib_pd *pd, struct ib_udata *udata);
402*4882a593Smuzhiyun int pvrdma_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata);
403*4882a593Smuzhiyun struct ib_mr *pvrdma_get_dma_mr(struct ib_pd *pd, int acc);
404*4882a593Smuzhiyun struct ib_mr *pvrdma_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
405*4882a593Smuzhiyun u64 virt_addr, int access_flags,
406*4882a593Smuzhiyun struct ib_udata *udata);
407*4882a593Smuzhiyun int pvrdma_dereg_mr(struct ib_mr *mr, struct ib_udata *udata);
408*4882a593Smuzhiyun struct ib_mr *pvrdma_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
409*4882a593Smuzhiyun u32 max_num_sg);
410*4882a593Smuzhiyun int pvrdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg,
411*4882a593Smuzhiyun int sg_nents, unsigned int *sg_offset);
412*4882a593Smuzhiyun int pvrdma_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
413*4882a593Smuzhiyun struct ib_udata *udata);
414*4882a593Smuzhiyun int pvrdma_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
415*4882a593Smuzhiyun int pvrdma_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
416*4882a593Smuzhiyun int pvrdma_req_notify_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
417*4882a593Smuzhiyun int pvrdma_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
418*4882a593Smuzhiyun struct ib_udata *udata);
419*4882a593Smuzhiyun int pvrdma_destroy_ah(struct ib_ah *ah, u32 flags);
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun int pvrdma_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr,
422*4882a593Smuzhiyun struct ib_udata *udata);
423*4882a593Smuzhiyun int pvrdma_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
424*4882a593Smuzhiyun enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
425*4882a593Smuzhiyun int pvrdma_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr);
426*4882a593Smuzhiyun int pvrdma_destroy_srq(struct ib_srq *srq, struct ib_udata *udata);
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun struct ib_qp *pvrdma_create_qp(struct ib_pd *pd,
429*4882a593Smuzhiyun struct ib_qp_init_attr *init_attr,
430*4882a593Smuzhiyun struct ib_udata *udata);
431*4882a593Smuzhiyun int pvrdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
432*4882a593Smuzhiyun int attr_mask, struct ib_udata *udata);
433*4882a593Smuzhiyun int pvrdma_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
434*4882a593Smuzhiyun int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr);
435*4882a593Smuzhiyun int pvrdma_destroy_qp(struct ib_qp *qp, struct ib_udata *udata);
436*4882a593Smuzhiyun int pvrdma_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
437*4882a593Smuzhiyun const struct ib_send_wr **bad_wr);
438*4882a593Smuzhiyun int pvrdma_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
439*4882a593Smuzhiyun const struct ib_recv_wr **bad_wr);
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun #endif /* __PVRDMA_VERBS_H__ */
442