1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
5*4882a593Smuzhiyun * modify it under the terms of EITHER the GNU General Public License
6*4882a593Smuzhiyun * version 2 as published by the Free Software Foundation or the BSD
7*4882a593Smuzhiyun * 2-Clause License. This program is distributed in the hope that it
8*4882a593Smuzhiyun * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9*4882a593Smuzhiyun * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10*4882a593Smuzhiyun * See the GNU General Public License version 2 for more details at
11*4882a593Smuzhiyun * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License
14*4882a593Smuzhiyun * along with this program available in the file COPYING in the main
15*4882a593Smuzhiyun * directory of this source tree.
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * The BSD 2-Clause License
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
20*4882a593Smuzhiyun * without modification, are permitted provided that the following
21*4882a593Smuzhiyun * conditions are met:
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * - Redistributions of source code must retain the above
24*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
25*4882a593Smuzhiyun * disclaimer.
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
28*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
29*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
30*4882a593Smuzhiyun * provided with the distribution.
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33*4882a593Smuzhiyun * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34*4882a593Smuzhiyun * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35*4882a593Smuzhiyun * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36*4882a593Smuzhiyun * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37*4882a593Smuzhiyun * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38*4882a593Smuzhiyun * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39*4882a593Smuzhiyun * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40*4882a593Smuzhiyun * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41*4882a593Smuzhiyun * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42*4882a593Smuzhiyun * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43*4882a593Smuzhiyun * OF THE POSSIBILITY OF SUCH DAMAGE.
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #include <linux/errno.h>
47*4882a593Smuzhiyun #include <linux/inetdevice.h>
48*4882a593Smuzhiyun #include <linux/init.h>
49*4882a593Smuzhiyun #include <linux/module.h>
50*4882a593Smuzhiyun #include <linux/slab.h>
51*4882a593Smuzhiyun #include <rdma/ib_addr.h>
52*4882a593Smuzhiyun #include <rdma/ib_smi.h>
53*4882a593Smuzhiyun #include <rdma/ib_user_verbs.h>
54*4882a593Smuzhiyun #include <net/addrconf.h>
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #include "pvrdma.h"
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define DRV_NAME "vmw_pvrdma"
59*4882a593Smuzhiyun #define DRV_VERSION "1.0.1.0-k"
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun static DEFINE_MUTEX(pvrdma_device_list_lock);
62*4882a593Smuzhiyun static LIST_HEAD(pvrdma_device_list);
63*4882a593Smuzhiyun static struct workqueue_struct *event_wq;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun static int pvrdma_add_gid(const struct ib_gid_attr *attr, void **context);
66*4882a593Smuzhiyun static int pvrdma_del_gid(const struct ib_gid_attr *attr, void **context);
67*4882a593Smuzhiyun
hca_type_show(struct device * device,struct device_attribute * attr,char * buf)68*4882a593Smuzhiyun static ssize_t hca_type_show(struct device *device,
69*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun return sprintf(buf, "VMW_PVRDMA-%s\n", DRV_VERSION);
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun static DEVICE_ATTR_RO(hca_type);
74*4882a593Smuzhiyun
hw_rev_show(struct device * device,struct device_attribute * attr,char * buf)75*4882a593Smuzhiyun static ssize_t hw_rev_show(struct device *device,
76*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun return sprintf(buf, "%d\n", PVRDMA_REV_ID);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun static DEVICE_ATTR_RO(hw_rev);
81*4882a593Smuzhiyun
board_id_show(struct device * device,struct device_attribute * attr,char * buf)82*4882a593Smuzhiyun static ssize_t board_id_show(struct device *device,
83*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun return sprintf(buf, "%d\n", PVRDMA_BOARD_ID);
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun static DEVICE_ATTR_RO(board_id);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun static struct attribute *pvrdma_class_attributes[] = {
90*4882a593Smuzhiyun &dev_attr_hw_rev.attr,
91*4882a593Smuzhiyun &dev_attr_hca_type.attr,
92*4882a593Smuzhiyun &dev_attr_board_id.attr,
93*4882a593Smuzhiyun NULL,
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun static const struct attribute_group pvrdma_attr_group = {
97*4882a593Smuzhiyun .attrs = pvrdma_class_attributes,
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
pvrdma_get_fw_ver_str(struct ib_device * device,char * str)100*4882a593Smuzhiyun static void pvrdma_get_fw_ver_str(struct ib_device *device, char *str)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun struct pvrdma_dev *dev =
103*4882a593Smuzhiyun container_of(device, struct pvrdma_dev, ib_dev);
104*4882a593Smuzhiyun snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d\n",
105*4882a593Smuzhiyun (int) (dev->dsr->caps.fw_ver >> 32),
106*4882a593Smuzhiyun (int) (dev->dsr->caps.fw_ver >> 16) & 0xffff,
107*4882a593Smuzhiyun (int) dev->dsr->caps.fw_ver & 0xffff);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
pvrdma_init_device(struct pvrdma_dev * dev)110*4882a593Smuzhiyun static int pvrdma_init_device(struct pvrdma_dev *dev)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun /* Initialize some device related stuff */
113*4882a593Smuzhiyun spin_lock_init(&dev->cmd_lock);
114*4882a593Smuzhiyun sema_init(&dev->cmd_sema, 1);
115*4882a593Smuzhiyun atomic_set(&dev->num_qps, 0);
116*4882a593Smuzhiyun atomic_set(&dev->num_srqs, 0);
117*4882a593Smuzhiyun atomic_set(&dev->num_cqs, 0);
118*4882a593Smuzhiyun atomic_set(&dev->num_pds, 0);
119*4882a593Smuzhiyun atomic_set(&dev->num_ahs, 0);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun return 0;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
pvrdma_port_immutable(struct ib_device * ibdev,u8 port_num,struct ib_port_immutable * immutable)124*4882a593Smuzhiyun static int pvrdma_port_immutable(struct ib_device *ibdev, u8 port_num,
125*4882a593Smuzhiyun struct ib_port_immutable *immutable)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun struct pvrdma_dev *dev = to_vdev(ibdev);
128*4882a593Smuzhiyun struct ib_port_attr attr;
129*4882a593Smuzhiyun int err;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun if (dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V1)
132*4882a593Smuzhiyun immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE;
133*4882a593Smuzhiyun else if (dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V2)
134*4882a593Smuzhiyun immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun err = ib_query_port(ibdev, port_num, &attr);
137*4882a593Smuzhiyun if (err)
138*4882a593Smuzhiyun return err;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun immutable->pkey_tbl_len = attr.pkey_tbl_len;
141*4882a593Smuzhiyun immutable->gid_tbl_len = attr.gid_tbl_len;
142*4882a593Smuzhiyun immutable->max_mad_size = IB_MGMT_MAD_SIZE;
143*4882a593Smuzhiyun return 0;
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun static const struct ib_device_ops pvrdma_dev_ops = {
147*4882a593Smuzhiyun .owner = THIS_MODULE,
148*4882a593Smuzhiyun .driver_id = RDMA_DRIVER_VMW_PVRDMA,
149*4882a593Smuzhiyun .uverbs_abi_ver = PVRDMA_UVERBS_ABI_VERSION,
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun .add_gid = pvrdma_add_gid,
152*4882a593Smuzhiyun .alloc_mr = pvrdma_alloc_mr,
153*4882a593Smuzhiyun .alloc_pd = pvrdma_alloc_pd,
154*4882a593Smuzhiyun .alloc_ucontext = pvrdma_alloc_ucontext,
155*4882a593Smuzhiyun .create_ah = pvrdma_create_ah,
156*4882a593Smuzhiyun .create_cq = pvrdma_create_cq,
157*4882a593Smuzhiyun .create_qp = pvrdma_create_qp,
158*4882a593Smuzhiyun .dealloc_pd = pvrdma_dealloc_pd,
159*4882a593Smuzhiyun .dealloc_ucontext = pvrdma_dealloc_ucontext,
160*4882a593Smuzhiyun .del_gid = pvrdma_del_gid,
161*4882a593Smuzhiyun .dereg_mr = pvrdma_dereg_mr,
162*4882a593Smuzhiyun .destroy_ah = pvrdma_destroy_ah,
163*4882a593Smuzhiyun .destroy_cq = pvrdma_destroy_cq,
164*4882a593Smuzhiyun .destroy_qp = pvrdma_destroy_qp,
165*4882a593Smuzhiyun .get_dev_fw_str = pvrdma_get_fw_ver_str,
166*4882a593Smuzhiyun .get_dma_mr = pvrdma_get_dma_mr,
167*4882a593Smuzhiyun .get_link_layer = pvrdma_port_link_layer,
168*4882a593Smuzhiyun .get_port_immutable = pvrdma_port_immutable,
169*4882a593Smuzhiyun .map_mr_sg = pvrdma_map_mr_sg,
170*4882a593Smuzhiyun .mmap = pvrdma_mmap,
171*4882a593Smuzhiyun .modify_port = pvrdma_modify_port,
172*4882a593Smuzhiyun .modify_qp = pvrdma_modify_qp,
173*4882a593Smuzhiyun .poll_cq = pvrdma_poll_cq,
174*4882a593Smuzhiyun .post_recv = pvrdma_post_recv,
175*4882a593Smuzhiyun .post_send = pvrdma_post_send,
176*4882a593Smuzhiyun .query_device = pvrdma_query_device,
177*4882a593Smuzhiyun .query_gid = pvrdma_query_gid,
178*4882a593Smuzhiyun .query_pkey = pvrdma_query_pkey,
179*4882a593Smuzhiyun .query_port = pvrdma_query_port,
180*4882a593Smuzhiyun .query_qp = pvrdma_query_qp,
181*4882a593Smuzhiyun .reg_user_mr = pvrdma_reg_user_mr,
182*4882a593Smuzhiyun .req_notify_cq = pvrdma_req_notify_cq,
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun INIT_RDMA_OBJ_SIZE(ib_ah, pvrdma_ah, ibah),
185*4882a593Smuzhiyun INIT_RDMA_OBJ_SIZE(ib_cq, pvrdma_cq, ibcq),
186*4882a593Smuzhiyun INIT_RDMA_OBJ_SIZE(ib_pd, pvrdma_pd, ibpd),
187*4882a593Smuzhiyun INIT_RDMA_OBJ_SIZE(ib_ucontext, pvrdma_ucontext, ibucontext),
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun static const struct ib_device_ops pvrdma_dev_srq_ops = {
191*4882a593Smuzhiyun .create_srq = pvrdma_create_srq,
192*4882a593Smuzhiyun .destroy_srq = pvrdma_destroy_srq,
193*4882a593Smuzhiyun .modify_srq = pvrdma_modify_srq,
194*4882a593Smuzhiyun .query_srq = pvrdma_query_srq,
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun INIT_RDMA_OBJ_SIZE(ib_srq, pvrdma_srq, ibsrq),
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun
pvrdma_register_device(struct pvrdma_dev * dev)199*4882a593Smuzhiyun static int pvrdma_register_device(struct pvrdma_dev *dev)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun int ret = -1;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun dev->ib_dev.node_guid = dev->dsr->caps.node_guid;
204*4882a593Smuzhiyun dev->sys_image_guid = dev->dsr->caps.sys_image_guid;
205*4882a593Smuzhiyun dev->flags = 0;
206*4882a593Smuzhiyun dev->ib_dev.num_comp_vectors = 1;
207*4882a593Smuzhiyun dev->ib_dev.dev.parent = &dev->pdev->dev;
208*4882a593Smuzhiyun dev->ib_dev.uverbs_cmd_mask =
209*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
210*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
211*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
212*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
213*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
214*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_REG_MR) |
215*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
216*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
217*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
218*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
219*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
220*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
221*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
222*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
223*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
224*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
225*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_POST_SEND) |
226*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_POST_RECV) |
227*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
228*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_DESTROY_AH);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun dev->ib_dev.node_type = RDMA_NODE_IB_CA;
231*4882a593Smuzhiyun dev->ib_dev.phys_port_cnt = dev->dsr->caps.phys_port_cnt;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun ib_set_device_ops(&dev->ib_dev, &pvrdma_dev_ops);
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun mutex_init(&dev->port_mutex);
236*4882a593Smuzhiyun spin_lock_init(&dev->desc_lock);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun dev->cq_tbl = kcalloc(dev->dsr->caps.max_cq, sizeof(struct pvrdma_cq *),
239*4882a593Smuzhiyun GFP_KERNEL);
240*4882a593Smuzhiyun if (!dev->cq_tbl)
241*4882a593Smuzhiyun return ret;
242*4882a593Smuzhiyun spin_lock_init(&dev->cq_tbl_lock);
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun dev->qp_tbl = kcalloc(dev->dsr->caps.max_qp, sizeof(struct pvrdma_qp *),
245*4882a593Smuzhiyun GFP_KERNEL);
246*4882a593Smuzhiyun if (!dev->qp_tbl)
247*4882a593Smuzhiyun goto err_cq_free;
248*4882a593Smuzhiyun spin_lock_init(&dev->qp_tbl_lock);
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun /* Check if SRQ is supported by backend */
251*4882a593Smuzhiyun if (dev->dsr->caps.max_srq) {
252*4882a593Smuzhiyun dev->ib_dev.uverbs_cmd_mask |=
253*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
254*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
255*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
256*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
257*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun ib_set_device_ops(&dev->ib_dev, &pvrdma_dev_srq_ops);
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun dev->srq_tbl = kcalloc(dev->dsr->caps.max_srq,
262*4882a593Smuzhiyun sizeof(struct pvrdma_srq *),
263*4882a593Smuzhiyun GFP_KERNEL);
264*4882a593Smuzhiyun if (!dev->srq_tbl)
265*4882a593Smuzhiyun goto err_qp_free;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun ret = ib_device_set_netdev(&dev->ib_dev, dev->netdev, 1);
268*4882a593Smuzhiyun if (ret)
269*4882a593Smuzhiyun goto err_srq_free;
270*4882a593Smuzhiyun spin_lock_init(&dev->srq_tbl_lock);
271*4882a593Smuzhiyun rdma_set_device_sysfs_group(&dev->ib_dev, &pvrdma_attr_group);
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun ret = ib_register_device(&dev->ib_dev, "vmw_pvrdma%d", &dev->pdev->dev);
274*4882a593Smuzhiyun if (ret)
275*4882a593Smuzhiyun goto err_srq_free;
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun dev->ib_active = true;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun return 0;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun err_srq_free:
282*4882a593Smuzhiyun kfree(dev->srq_tbl);
283*4882a593Smuzhiyun err_qp_free:
284*4882a593Smuzhiyun kfree(dev->qp_tbl);
285*4882a593Smuzhiyun err_cq_free:
286*4882a593Smuzhiyun kfree(dev->cq_tbl);
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun return ret;
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
pvrdma_intr0_handler(int irq,void * dev_id)291*4882a593Smuzhiyun static irqreturn_t pvrdma_intr0_handler(int irq, void *dev_id)
292*4882a593Smuzhiyun {
293*4882a593Smuzhiyun u32 icr = PVRDMA_INTR_CAUSE_RESPONSE;
294*4882a593Smuzhiyun struct pvrdma_dev *dev = dev_id;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun dev_dbg(&dev->pdev->dev, "interrupt 0 (response) handler\n");
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun if (!dev->pdev->msix_enabled) {
299*4882a593Smuzhiyun /* Legacy intr */
300*4882a593Smuzhiyun icr = pvrdma_read_reg(dev, PVRDMA_REG_ICR);
301*4882a593Smuzhiyun if (icr == 0)
302*4882a593Smuzhiyun return IRQ_NONE;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun if (icr == PVRDMA_INTR_CAUSE_RESPONSE)
306*4882a593Smuzhiyun complete(&dev->cmd_done);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun return IRQ_HANDLED;
309*4882a593Smuzhiyun }
310*4882a593Smuzhiyun
pvrdma_qp_event(struct pvrdma_dev * dev,u32 qpn,int type)311*4882a593Smuzhiyun static void pvrdma_qp_event(struct pvrdma_dev *dev, u32 qpn, int type)
312*4882a593Smuzhiyun {
313*4882a593Smuzhiyun struct pvrdma_qp *qp;
314*4882a593Smuzhiyun unsigned long flags;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun spin_lock_irqsave(&dev->qp_tbl_lock, flags);
317*4882a593Smuzhiyun qp = dev->qp_tbl[qpn % dev->dsr->caps.max_qp];
318*4882a593Smuzhiyun if (qp)
319*4882a593Smuzhiyun refcount_inc(&qp->refcnt);
320*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->qp_tbl_lock, flags);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun if (qp && qp->ibqp.event_handler) {
323*4882a593Smuzhiyun struct ib_qp *ibqp = &qp->ibqp;
324*4882a593Smuzhiyun struct ib_event e;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun e.device = ibqp->device;
327*4882a593Smuzhiyun e.element.qp = ibqp;
328*4882a593Smuzhiyun e.event = type; /* 1:1 mapping for now. */
329*4882a593Smuzhiyun ibqp->event_handler(&e, ibqp->qp_context);
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun if (qp) {
332*4882a593Smuzhiyun if (refcount_dec_and_test(&qp->refcnt))
333*4882a593Smuzhiyun complete(&qp->free);
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun
pvrdma_cq_event(struct pvrdma_dev * dev,u32 cqn,int type)337*4882a593Smuzhiyun static void pvrdma_cq_event(struct pvrdma_dev *dev, u32 cqn, int type)
338*4882a593Smuzhiyun {
339*4882a593Smuzhiyun struct pvrdma_cq *cq;
340*4882a593Smuzhiyun unsigned long flags;
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun spin_lock_irqsave(&dev->cq_tbl_lock, flags);
343*4882a593Smuzhiyun cq = dev->cq_tbl[cqn % dev->dsr->caps.max_cq];
344*4882a593Smuzhiyun if (cq)
345*4882a593Smuzhiyun refcount_inc(&cq->refcnt);
346*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun if (cq && cq->ibcq.event_handler) {
349*4882a593Smuzhiyun struct ib_cq *ibcq = &cq->ibcq;
350*4882a593Smuzhiyun struct ib_event e;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun e.device = ibcq->device;
353*4882a593Smuzhiyun e.element.cq = ibcq;
354*4882a593Smuzhiyun e.event = type; /* 1:1 mapping for now. */
355*4882a593Smuzhiyun ibcq->event_handler(&e, ibcq->cq_context);
356*4882a593Smuzhiyun }
357*4882a593Smuzhiyun if (cq) {
358*4882a593Smuzhiyun if (refcount_dec_and_test(&cq->refcnt))
359*4882a593Smuzhiyun complete(&cq->free);
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
pvrdma_srq_event(struct pvrdma_dev * dev,u32 srqn,int type)363*4882a593Smuzhiyun static void pvrdma_srq_event(struct pvrdma_dev *dev, u32 srqn, int type)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun struct pvrdma_srq *srq;
366*4882a593Smuzhiyun unsigned long flags;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun spin_lock_irqsave(&dev->srq_tbl_lock, flags);
369*4882a593Smuzhiyun if (dev->srq_tbl)
370*4882a593Smuzhiyun srq = dev->srq_tbl[srqn % dev->dsr->caps.max_srq];
371*4882a593Smuzhiyun else
372*4882a593Smuzhiyun srq = NULL;
373*4882a593Smuzhiyun if (srq)
374*4882a593Smuzhiyun refcount_inc(&srq->refcnt);
375*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->srq_tbl_lock, flags);
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun if (srq && srq->ibsrq.event_handler) {
378*4882a593Smuzhiyun struct ib_srq *ibsrq = &srq->ibsrq;
379*4882a593Smuzhiyun struct ib_event e;
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun e.device = ibsrq->device;
382*4882a593Smuzhiyun e.element.srq = ibsrq;
383*4882a593Smuzhiyun e.event = type; /* 1:1 mapping for now. */
384*4882a593Smuzhiyun ibsrq->event_handler(&e, ibsrq->srq_context);
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun if (srq) {
387*4882a593Smuzhiyun if (refcount_dec_and_test(&srq->refcnt))
388*4882a593Smuzhiyun complete(&srq->free);
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun
pvrdma_dispatch_event(struct pvrdma_dev * dev,int port,enum ib_event_type event)392*4882a593Smuzhiyun static void pvrdma_dispatch_event(struct pvrdma_dev *dev, int port,
393*4882a593Smuzhiyun enum ib_event_type event)
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun struct ib_event ib_event;
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun memset(&ib_event, 0, sizeof(ib_event));
398*4882a593Smuzhiyun ib_event.device = &dev->ib_dev;
399*4882a593Smuzhiyun ib_event.element.port_num = port;
400*4882a593Smuzhiyun ib_event.event = event;
401*4882a593Smuzhiyun ib_dispatch_event(&ib_event);
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun
pvrdma_dev_event(struct pvrdma_dev * dev,u8 port,int type)404*4882a593Smuzhiyun static void pvrdma_dev_event(struct pvrdma_dev *dev, u8 port, int type)
405*4882a593Smuzhiyun {
406*4882a593Smuzhiyun if (port < 1 || port > dev->dsr->caps.phys_port_cnt) {
407*4882a593Smuzhiyun dev_warn(&dev->pdev->dev, "event on port %d\n", port);
408*4882a593Smuzhiyun return;
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun pvrdma_dispatch_event(dev, port, type);
412*4882a593Smuzhiyun }
413*4882a593Smuzhiyun
get_eqe(struct pvrdma_dev * dev,unsigned int i)414*4882a593Smuzhiyun static inline struct pvrdma_eqe *get_eqe(struct pvrdma_dev *dev, unsigned int i)
415*4882a593Smuzhiyun {
416*4882a593Smuzhiyun return (struct pvrdma_eqe *)pvrdma_page_dir_get_ptr(
417*4882a593Smuzhiyun &dev->async_pdir,
418*4882a593Smuzhiyun PAGE_SIZE +
419*4882a593Smuzhiyun sizeof(struct pvrdma_eqe) * i);
420*4882a593Smuzhiyun }
421*4882a593Smuzhiyun
pvrdma_intr1_handler(int irq,void * dev_id)422*4882a593Smuzhiyun static irqreturn_t pvrdma_intr1_handler(int irq, void *dev_id)
423*4882a593Smuzhiyun {
424*4882a593Smuzhiyun struct pvrdma_dev *dev = dev_id;
425*4882a593Smuzhiyun struct pvrdma_ring *ring = &dev->async_ring_state->rx;
426*4882a593Smuzhiyun int ring_slots = (dev->dsr->async_ring_pages.num_pages - 1) *
427*4882a593Smuzhiyun PAGE_SIZE / sizeof(struct pvrdma_eqe);
428*4882a593Smuzhiyun unsigned int head;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun dev_dbg(&dev->pdev->dev, "interrupt 1 (async event) handler\n");
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun /*
433*4882a593Smuzhiyun * Don't process events until the IB device is registered. Otherwise
434*4882a593Smuzhiyun * we'll try to ib_dispatch_event() on an invalid device.
435*4882a593Smuzhiyun */
436*4882a593Smuzhiyun if (!dev->ib_active)
437*4882a593Smuzhiyun return IRQ_HANDLED;
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun while (pvrdma_idx_ring_has_data(ring, ring_slots, &head) > 0) {
440*4882a593Smuzhiyun struct pvrdma_eqe *eqe;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun eqe = get_eqe(dev, head);
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun switch (eqe->type) {
445*4882a593Smuzhiyun case PVRDMA_EVENT_QP_FATAL:
446*4882a593Smuzhiyun case PVRDMA_EVENT_QP_REQ_ERR:
447*4882a593Smuzhiyun case PVRDMA_EVENT_QP_ACCESS_ERR:
448*4882a593Smuzhiyun case PVRDMA_EVENT_COMM_EST:
449*4882a593Smuzhiyun case PVRDMA_EVENT_SQ_DRAINED:
450*4882a593Smuzhiyun case PVRDMA_EVENT_PATH_MIG:
451*4882a593Smuzhiyun case PVRDMA_EVENT_PATH_MIG_ERR:
452*4882a593Smuzhiyun case PVRDMA_EVENT_QP_LAST_WQE_REACHED:
453*4882a593Smuzhiyun pvrdma_qp_event(dev, eqe->info, eqe->type);
454*4882a593Smuzhiyun break;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun case PVRDMA_EVENT_CQ_ERR:
457*4882a593Smuzhiyun pvrdma_cq_event(dev, eqe->info, eqe->type);
458*4882a593Smuzhiyun break;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun case PVRDMA_EVENT_SRQ_ERR:
461*4882a593Smuzhiyun case PVRDMA_EVENT_SRQ_LIMIT_REACHED:
462*4882a593Smuzhiyun pvrdma_srq_event(dev, eqe->info, eqe->type);
463*4882a593Smuzhiyun break;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun case PVRDMA_EVENT_PORT_ACTIVE:
466*4882a593Smuzhiyun case PVRDMA_EVENT_PORT_ERR:
467*4882a593Smuzhiyun case PVRDMA_EVENT_LID_CHANGE:
468*4882a593Smuzhiyun case PVRDMA_EVENT_PKEY_CHANGE:
469*4882a593Smuzhiyun case PVRDMA_EVENT_SM_CHANGE:
470*4882a593Smuzhiyun case PVRDMA_EVENT_CLIENT_REREGISTER:
471*4882a593Smuzhiyun case PVRDMA_EVENT_GID_CHANGE:
472*4882a593Smuzhiyun pvrdma_dev_event(dev, eqe->info, eqe->type);
473*4882a593Smuzhiyun break;
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun case PVRDMA_EVENT_DEVICE_FATAL:
476*4882a593Smuzhiyun pvrdma_dev_event(dev, 1, eqe->type);
477*4882a593Smuzhiyun break;
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun default:
480*4882a593Smuzhiyun break;
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun pvrdma_idx_ring_inc(&ring->cons_head, ring_slots);
484*4882a593Smuzhiyun }
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun return IRQ_HANDLED;
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun
get_cqne(struct pvrdma_dev * dev,unsigned int i)489*4882a593Smuzhiyun static inline struct pvrdma_cqne *get_cqne(struct pvrdma_dev *dev,
490*4882a593Smuzhiyun unsigned int i)
491*4882a593Smuzhiyun {
492*4882a593Smuzhiyun return (struct pvrdma_cqne *)pvrdma_page_dir_get_ptr(
493*4882a593Smuzhiyun &dev->cq_pdir,
494*4882a593Smuzhiyun PAGE_SIZE +
495*4882a593Smuzhiyun sizeof(struct pvrdma_cqne) * i);
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
pvrdma_intrx_handler(int irq,void * dev_id)498*4882a593Smuzhiyun static irqreturn_t pvrdma_intrx_handler(int irq, void *dev_id)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun struct pvrdma_dev *dev = dev_id;
501*4882a593Smuzhiyun struct pvrdma_ring *ring = &dev->cq_ring_state->rx;
502*4882a593Smuzhiyun int ring_slots = (dev->dsr->cq_ring_pages.num_pages - 1) * PAGE_SIZE /
503*4882a593Smuzhiyun sizeof(struct pvrdma_cqne);
504*4882a593Smuzhiyun unsigned int head;
505*4882a593Smuzhiyun unsigned long flags;
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun dev_dbg(&dev->pdev->dev, "interrupt x (completion) handler\n");
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun while (pvrdma_idx_ring_has_data(ring, ring_slots, &head) > 0) {
510*4882a593Smuzhiyun struct pvrdma_cqne *cqne;
511*4882a593Smuzhiyun struct pvrdma_cq *cq;
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun cqne = get_cqne(dev, head);
514*4882a593Smuzhiyun spin_lock_irqsave(&dev->cq_tbl_lock, flags);
515*4882a593Smuzhiyun cq = dev->cq_tbl[cqne->info % dev->dsr->caps.max_cq];
516*4882a593Smuzhiyun if (cq)
517*4882a593Smuzhiyun refcount_inc(&cq->refcnt);
518*4882a593Smuzhiyun spin_unlock_irqrestore(&dev->cq_tbl_lock, flags);
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun if (cq && cq->ibcq.comp_handler)
521*4882a593Smuzhiyun cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
522*4882a593Smuzhiyun if (cq) {
523*4882a593Smuzhiyun if (refcount_dec_and_test(&cq->refcnt))
524*4882a593Smuzhiyun complete(&cq->free);
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun pvrdma_idx_ring_inc(&ring->cons_head, ring_slots);
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun return IRQ_HANDLED;
530*4882a593Smuzhiyun }
531*4882a593Smuzhiyun
pvrdma_free_irq(struct pvrdma_dev * dev)532*4882a593Smuzhiyun static void pvrdma_free_irq(struct pvrdma_dev *dev)
533*4882a593Smuzhiyun {
534*4882a593Smuzhiyun int i;
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun dev_dbg(&dev->pdev->dev, "freeing interrupts\n");
537*4882a593Smuzhiyun for (i = 0; i < dev->nr_vectors; i++)
538*4882a593Smuzhiyun free_irq(pci_irq_vector(dev->pdev, i), dev);
539*4882a593Smuzhiyun }
540*4882a593Smuzhiyun
pvrdma_enable_intrs(struct pvrdma_dev * dev)541*4882a593Smuzhiyun static void pvrdma_enable_intrs(struct pvrdma_dev *dev)
542*4882a593Smuzhiyun {
543*4882a593Smuzhiyun dev_dbg(&dev->pdev->dev, "enable interrupts\n");
544*4882a593Smuzhiyun pvrdma_write_reg(dev, PVRDMA_REG_IMR, 0);
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun
pvrdma_disable_intrs(struct pvrdma_dev * dev)547*4882a593Smuzhiyun static void pvrdma_disable_intrs(struct pvrdma_dev *dev)
548*4882a593Smuzhiyun {
549*4882a593Smuzhiyun dev_dbg(&dev->pdev->dev, "disable interrupts\n");
550*4882a593Smuzhiyun pvrdma_write_reg(dev, PVRDMA_REG_IMR, ~0);
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun
pvrdma_alloc_intrs(struct pvrdma_dev * dev)553*4882a593Smuzhiyun static int pvrdma_alloc_intrs(struct pvrdma_dev *dev)
554*4882a593Smuzhiyun {
555*4882a593Smuzhiyun struct pci_dev *pdev = dev->pdev;
556*4882a593Smuzhiyun int ret = 0, i;
557*4882a593Smuzhiyun
558*4882a593Smuzhiyun ret = pci_alloc_irq_vectors(pdev, 1, PVRDMA_MAX_INTERRUPTS,
559*4882a593Smuzhiyun PCI_IRQ_MSIX);
560*4882a593Smuzhiyun if (ret < 0) {
561*4882a593Smuzhiyun ret = pci_alloc_irq_vectors(pdev, 1, 1,
562*4882a593Smuzhiyun PCI_IRQ_MSI | PCI_IRQ_LEGACY);
563*4882a593Smuzhiyun if (ret < 0)
564*4882a593Smuzhiyun return ret;
565*4882a593Smuzhiyun }
566*4882a593Smuzhiyun dev->nr_vectors = ret;
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun ret = request_irq(pci_irq_vector(dev->pdev, 0), pvrdma_intr0_handler,
569*4882a593Smuzhiyun pdev->msix_enabled ? 0 : IRQF_SHARED, DRV_NAME, dev);
570*4882a593Smuzhiyun if (ret) {
571*4882a593Smuzhiyun dev_err(&dev->pdev->dev,
572*4882a593Smuzhiyun "failed to request interrupt 0\n");
573*4882a593Smuzhiyun goto out_free_vectors;
574*4882a593Smuzhiyun }
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun for (i = 1; i < dev->nr_vectors; i++) {
577*4882a593Smuzhiyun ret = request_irq(pci_irq_vector(dev->pdev, i),
578*4882a593Smuzhiyun i == 1 ? pvrdma_intr1_handler :
579*4882a593Smuzhiyun pvrdma_intrx_handler,
580*4882a593Smuzhiyun 0, DRV_NAME, dev);
581*4882a593Smuzhiyun if (ret) {
582*4882a593Smuzhiyun dev_err(&dev->pdev->dev,
583*4882a593Smuzhiyun "failed to request interrupt %d\n", i);
584*4882a593Smuzhiyun goto free_irqs;
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun }
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun return 0;
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun free_irqs:
591*4882a593Smuzhiyun while (--i >= 0)
592*4882a593Smuzhiyun free_irq(pci_irq_vector(dev->pdev, i), dev);
593*4882a593Smuzhiyun out_free_vectors:
594*4882a593Smuzhiyun pci_free_irq_vectors(pdev);
595*4882a593Smuzhiyun return ret;
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun
pvrdma_free_slots(struct pvrdma_dev * dev)598*4882a593Smuzhiyun static void pvrdma_free_slots(struct pvrdma_dev *dev)
599*4882a593Smuzhiyun {
600*4882a593Smuzhiyun struct pci_dev *pdev = dev->pdev;
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun if (dev->resp_slot)
603*4882a593Smuzhiyun dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->resp_slot,
604*4882a593Smuzhiyun dev->dsr->resp_slot_dma);
605*4882a593Smuzhiyun if (dev->cmd_slot)
606*4882a593Smuzhiyun dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->cmd_slot,
607*4882a593Smuzhiyun dev->dsr->cmd_slot_dma);
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun
pvrdma_add_gid_at_index(struct pvrdma_dev * dev,const union ib_gid * gid,u8 gid_type,int index)610*4882a593Smuzhiyun static int pvrdma_add_gid_at_index(struct pvrdma_dev *dev,
611*4882a593Smuzhiyun const union ib_gid *gid,
612*4882a593Smuzhiyun u8 gid_type,
613*4882a593Smuzhiyun int index)
614*4882a593Smuzhiyun {
615*4882a593Smuzhiyun int ret;
616*4882a593Smuzhiyun union pvrdma_cmd_req req;
617*4882a593Smuzhiyun struct pvrdma_cmd_create_bind *cmd_bind = &req.create_bind;
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun if (!dev->sgid_tbl) {
620*4882a593Smuzhiyun dev_warn(&dev->pdev->dev, "sgid table not initialized\n");
621*4882a593Smuzhiyun return -EINVAL;
622*4882a593Smuzhiyun }
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun memset(cmd_bind, 0, sizeof(*cmd_bind));
625*4882a593Smuzhiyun cmd_bind->hdr.cmd = PVRDMA_CMD_CREATE_BIND;
626*4882a593Smuzhiyun memcpy(cmd_bind->new_gid, gid->raw, 16);
627*4882a593Smuzhiyun cmd_bind->mtu = ib_mtu_enum_to_int(IB_MTU_1024);
628*4882a593Smuzhiyun cmd_bind->vlan = 0xfff;
629*4882a593Smuzhiyun cmd_bind->index = index;
630*4882a593Smuzhiyun cmd_bind->gid_type = gid_type;
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun ret = pvrdma_cmd_post(dev, &req, NULL, 0);
633*4882a593Smuzhiyun if (ret < 0) {
634*4882a593Smuzhiyun dev_warn(&dev->pdev->dev,
635*4882a593Smuzhiyun "could not create binding, error: %d\n", ret);
636*4882a593Smuzhiyun return -EFAULT;
637*4882a593Smuzhiyun }
638*4882a593Smuzhiyun memcpy(&dev->sgid_tbl[index], gid, sizeof(*gid));
639*4882a593Smuzhiyun return 0;
640*4882a593Smuzhiyun }
641*4882a593Smuzhiyun
pvrdma_add_gid(const struct ib_gid_attr * attr,void ** context)642*4882a593Smuzhiyun static int pvrdma_add_gid(const struct ib_gid_attr *attr, void **context)
643*4882a593Smuzhiyun {
644*4882a593Smuzhiyun struct pvrdma_dev *dev = to_vdev(attr->device);
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun return pvrdma_add_gid_at_index(dev, &attr->gid,
647*4882a593Smuzhiyun ib_gid_type_to_pvrdma(attr->gid_type),
648*4882a593Smuzhiyun attr->index);
649*4882a593Smuzhiyun }
650*4882a593Smuzhiyun
pvrdma_del_gid_at_index(struct pvrdma_dev * dev,int index)651*4882a593Smuzhiyun static int pvrdma_del_gid_at_index(struct pvrdma_dev *dev, int index)
652*4882a593Smuzhiyun {
653*4882a593Smuzhiyun int ret;
654*4882a593Smuzhiyun union pvrdma_cmd_req req;
655*4882a593Smuzhiyun struct pvrdma_cmd_destroy_bind *cmd_dest = &req.destroy_bind;
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun /* Update sgid table. */
658*4882a593Smuzhiyun if (!dev->sgid_tbl) {
659*4882a593Smuzhiyun dev_warn(&dev->pdev->dev, "sgid table not initialized\n");
660*4882a593Smuzhiyun return -EINVAL;
661*4882a593Smuzhiyun }
662*4882a593Smuzhiyun
663*4882a593Smuzhiyun memset(cmd_dest, 0, sizeof(*cmd_dest));
664*4882a593Smuzhiyun cmd_dest->hdr.cmd = PVRDMA_CMD_DESTROY_BIND;
665*4882a593Smuzhiyun memcpy(cmd_dest->dest_gid, &dev->sgid_tbl[index], 16);
666*4882a593Smuzhiyun cmd_dest->index = index;
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun ret = pvrdma_cmd_post(dev, &req, NULL, 0);
669*4882a593Smuzhiyun if (ret < 0) {
670*4882a593Smuzhiyun dev_warn(&dev->pdev->dev,
671*4882a593Smuzhiyun "could not destroy binding, error: %d\n", ret);
672*4882a593Smuzhiyun return ret;
673*4882a593Smuzhiyun }
674*4882a593Smuzhiyun memset(&dev->sgid_tbl[index], 0, 16);
675*4882a593Smuzhiyun return 0;
676*4882a593Smuzhiyun }
677*4882a593Smuzhiyun
pvrdma_del_gid(const struct ib_gid_attr * attr,void ** context)678*4882a593Smuzhiyun static int pvrdma_del_gid(const struct ib_gid_attr *attr, void **context)
679*4882a593Smuzhiyun {
680*4882a593Smuzhiyun struct pvrdma_dev *dev = to_vdev(attr->device);
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun dev_dbg(&dev->pdev->dev, "removing gid at index %u from %s",
683*4882a593Smuzhiyun attr->index, dev->netdev->name);
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun return pvrdma_del_gid_at_index(dev, attr->index);
686*4882a593Smuzhiyun }
687*4882a593Smuzhiyun
pvrdma_netdevice_event_handle(struct pvrdma_dev * dev,struct net_device * ndev,unsigned long event)688*4882a593Smuzhiyun static void pvrdma_netdevice_event_handle(struct pvrdma_dev *dev,
689*4882a593Smuzhiyun struct net_device *ndev,
690*4882a593Smuzhiyun unsigned long event)
691*4882a593Smuzhiyun {
692*4882a593Smuzhiyun struct pci_dev *pdev_net;
693*4882a593Smuzhiyun unsigned int slot;
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun switch (event) {
696*4882a593Smuzhiyun case NETDEV_REBOOT:
697*4882a593Smuzhiyun case NETDEV_DOWN:
698*4882a593Smuzhiyun pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ERR);
699*4882a593Smuzhiyun break;
700*4882a593Smuzhiyun case NETDEV_UP:
701*4882a593Smuzhiyun pvrdma_write_reg(dev, PVRDMA_REG_CTL,
702*4882a593Smuzhiyun PVRDMA_DEVICE_CTL_UNQUIESCE);
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun mb();
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun if (pvrdma_read_reg(dev, PVRDMA_REG_ERR))
707*4882a593Smuzhiyun dev_err(&dev->pdev->dev,
708*4882a593Smuzhiyun "failed to activate device during link up\n");
709*4882a593Smuzhiyun else
710*4882a593Smuzhiyun pvrdma_dispatch_event(dev, 1, IB_EVENT_PORT_ACTIVE);
711*4882a593Smuzhiyun break;
712*4882a593Smuzhiyun case NETDEV_UNREGISTER:
713*4882a593Smuzhiyun ib_device_set_netdev(&dev->ib_dev, NULL, 1);
714*4882a593Smuzhiyun dev_put(dev->netdev);
715*4882a593Smuzhiyun dev->netdev = NULL;
716*4882a593Smuzhiyun break;
717*4882a593Smuzhiyun case NETDEV_REGISTER:
718*4882a593Smuzhiyun /* vmxnet3 will have same bus, slot. But func will be 0 */
719*4882a593Smuzhiyun slot = PCI_SLOT(dev->pdev->devfn);
720*4882a593Smuzhiyun pdev_net = pci_get_slot(dev->pdev->bus,
721*4882a593Smuzhiyun PCI_DEVFN(slot, 0));
722*4882a593Smuzhiyun if ((dev->netdev == NULL) &&
723*4882a593Smuzhiyun (pci_get_drvdata(pdev_net) == ndev)) {
724*4882a593Smuzhiyun /* this is our netdev */
725*4882a593Smuzhiyun ib_device_set_netdev(&dev->ib_dev, ndev, 1);
726*4882a593Smuzhiyun dev->netdev = ndev;
727*4882a593Smuzhiyun dev_hold(ndev);
728*4882a593Smuzhiyun }
729*4882a593Smuzhiyun pci_dev_put(pdev_net);
730*4882a593Smuzhiyun break;
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun default:
733*4882a593Smuzhiyun dev_dbg(&dev->pdev->dev, "ignore netdevice event %ld on %s\n",
734*4882a593Smuzhiyun event, dev_name(&dev->ib_dev.dev));
735*4882a593Smuzhiyun break;
736*4882a593Smuzhiyun }
737*4882a593Smuzhiyun }
738*4882a593Smuzhiyun
pvrdma_netdevice_event_work(struct work_struct * work)739*4882a593Smuzhiyun static void pvrdma_netdevice_event_work(struct work_struct *work)
740*4882a593Smuzhiyun {
741*4882a593Smuzhiyun struct pvrdma_netdevice_work *netdev_work;
742*4882a593Smuzhiyun struct pvrdma_dev *dev;
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun netdev_work = container_of(work, struct pvrdma_netdevice_work, work);
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun mutex_lock(&pvrdma_device_list_lock);
747*4882a593Smuzhiyun list_for_each_entry(dev, &pvrdma_device_list, device_link) {
748*4882a593Smuzhiyun if ((netdev_work->event == NETDEV_REGISTER) ||
749*4882a593Smuzhiyun (dev->netdev == netdev_work->event_netdev)) {
750*4882a593Smuzhiyun pvrdma_netdevice_event_handle(dev,
751*4882a593Smuzhiyun netdev_work->event_netdev,
752*4882a593Smuzhiyun netdev_work->event);
753*4882a593Smuzhiyun break;
754*4882a593Smuzhiyun }
755*4882a593Smuzhiyun }
756*4882a593Smuzhiyun mutex_unlock(&pvrdma_device_list_lock);
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun kfree(netdev_work);
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun
pvrdma_netdevice_event(struct notifier_block * this,unsigned long event,void * ptr)761*4882a593Smuzhiyun static int pvrdma_netdevice_event(struct notifier_block *this,
762*4882a593Smuzhiyun unsigned long event, void *ptr)
763*4882a593Smuzhiyun {
764*4882a593Smuzhiyun struct net_device *event_netdev = netdev_notifier_info_to_dev(ptr);
765*4882a593Smuzhiyun struct pvrdma_netdevice_work *netdev_work;
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun netdev_work = kmalloc(sizeof(*netdev_work), GFP_ATOMIC);
768*4882a593Smuzhiyun if (!netdev_work)
769*4882a593Smuzhiyun return NOTIFY_BAD;
770*4882a593Smuzhiyun
771*4882a593Smuzhiyun INIT_WORK(&netdev_work->work, pvrdma_netdevice_event_work);
772*4882a593Smuzhiyun netdev_work->event_netdev = event_netdev;
773*4882a593Smuzhiyun netdev_work->event = event;
774*4882a593Smuzhiyun queue_work(event_wq, &netdev_work->work);
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun return NOTIFY_DONE;
777*4882a593Smuzhiyun }
778*4882a593Smuzhiyun
pvrdma_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)779*4882a593Smuzhiyun static int pvrdma_pci_probe(struct pci_dev *pdev,
780*4882a593Smuzhiyun const struct pci_device_id *id)
781*4882a593Smuzhiyun {
782*4882a593Smuzhiyun struct pci_dev *pdev_net;
783*4882a593Smuzhiyun struct pvrdma_dev *dev;
784*4882a593Smuzhiyun int ret;
785*4882a593Smuzhiyun unsigned long start;
786*4882a593Smuzhiyun unsigned long len;
787*4882a593Smuzhiyun dma_addr_t slot_dma = 0;
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun dev_dbg(&pdev->dev, "initializing driver %s\n", pci_name(pdev));
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun /* Allocate zero-out device */
792*4882a593Smuzhiyun dev = ib_alloc_device(pvrdma_dev, ib_dev);
793*4882a593Smuzhiyun if (!dev) {
794*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to allocate IB device\n");
795*4882a593Smuzhiyun return -ENOMEM;
796*4882a593Smuzhiyun }
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun mutex_lock(&pvrdma_device_list_lock);
799*4882a593Smuzhiyun list_add(&dev->device_link, &pvrdma_device_list);
800*4882a593Smuzhiyun mutex_unlock(&pvrdma_device_list_lock);
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun ret = pvrdma_init_device(dev);
803*4882a593Smuzhiyun if (ret)
804*4882a593Smuzhiyun goto err_free_device;
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun dev->pdev = pdev;
807*4882a593Smuzhiyun pci_set_drvdata(pdev, dev);
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun ret = pci_enable_device(pdev);
810*4882a593Smuzhiyun if (ret) {
811*4882a593Smuzhiyun dev_err(&pdev->dev, "cannot enable PCI device\n");
812*4882a593Smuzhiyun goto err_free_device;
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun dev_dbg(&pdev->dev, "PCI resource flags BAR0 %#lx\n",
816*4882a593Smuzhiyun pci_resource_flags(pdev, 0));
817*4882a593Smuzhiyun dev_dbg(&pdev->dev, "PCI resource len %#llx\n",
818*4882a593Smuzhiyun (unsigned long long)pci_resource_len(pdev, 0));
819*4882a593Smuzhiyun dev_dbg(&pdev->dev, "PCI resource start %#llx\n",
820*4882a593Smuzhiyun (unsigned long long)pci_resource_start(pdev, 0));
821*4882a593Smuzhiyun dev_dbg(&pdev->dev, "PCI resource flags BAR1 %#lx\n",
822*4882a593Smuzhiyun pci_resource_flags(pdev, 1));
823*4882a593Smuzhiyun dev_dbg(&pdev->dev, "PCI resource len %#llx\n",
824*4882a593Smuzhiyun (unsigned long long)pci_resource_len(pdev, 1));
825*4882a593Smuzhiyun dev_dbg(&pdev->dev, "PCI resource start %#llx\n",
826*4882a593Smuzhiyun (unsigned long long)pci_resource_start(pdev, 1));
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
829*4882a593Smuzhiyun !(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
830*4882a593Smuzhiyun dev_err(&pdev->dev, "PCI BAR region not MMIO\n");
831*4882a593Smuzhiyun ret = -ENOMEM;
832*4882a593Smuzhiyun goto err_disable_pdev;
833*4882a593Smuzhiyun }
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun ret = pci_request_regions(pdev, DRV_NAME);
836*4882a593Smuzhiyun if (ret) {
837*4882a593Smuzhiyun dev_err(&pdev->dev, "cannot request PCI resources\n");
838*4882a593Smuzhiyun goto err_disable_pdev;
839*4882a593Smuzhiyun }
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun /* Enable 64-Bit DMA */
842*4882a593Smuzhiyun if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
843*4882a593Smuzhiyun ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
844*4882a593Smuzhiyun if (ret != 0) {
845*4882a593Smuzhiyun dev_err(&pdev->dev,
846*4882a593Smuzhiyun "pci_set_consistent_dma_mask failed\n");
847*4882a593Smuzhiyun goto err_free_resource;
848*4882a593Smuzhiyun }
849*4882a593Smuzhiyun } else {
850*4882a593Smuzhiyun ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
851*4882a593Smuzhiyun if (ret != 0) {
852*4882a593Smuzhiyun dev_err(&pdev->dev,
853*4882a593Smuzhiyun "pci_set_dma_mask failed\n");
854*4882a593Smuzhiyun goto err_free_resource;
855*4882a593Smuzhiyun }
856*4882a593Smuzhiyun }
857*4882a593Smuzhiyun dma_set_max_seg_size(&pdev->dev, UINT_MAX);
858*4882a593Smuzhiyun pci_set_master(pdev);
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun /* Map register space */
861*4882a593Smuzhiyun start = pci_resource_start(dev->pdev, PVRDMA_PCI_RESOURCE_REG);
862*4882a593Smuzhiyun len = pci_resource_len(dev->pdev, PVRDMA_PCI_RESOURCE_REG);
863*4882a593Smuzhiyun dev->regs = ioremap(start, len);
864*4882a593Smuzhiyun if (!dev->regs) {
865*4882a593Smuzhiyun dev_err(&pdev->dev, "register mapping failed\n");
866*4882a593Smuzhiyun ret = -ENOMEM;
867*4882a593Smuzhiyun goto err_free_resource;
868*4882a593Smuzhiyun }
869*4882a593Smuzhiyun
870*4882a593Smuzhiyun /* Setup per-device UAR. */
871*4882a593Smuzhiyun dev->driver_uar.index = 0;
872*4882a593Smuzhiyun dev->driver_uar.pfn =
873*4882a593Smuzhiyun pci_resource_start(dev->pdev, PVRDMA_PCI_RESOURCE_UAR) >>
874*4882a593Smuzhiyun PAGE_SHIFT;
875*4882a593Smuzhiyun dev->driver_uar.map =
876*4882a593Smuzhiyun ioremap(dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
877*4882a593Smuzhiyun if (!dev->driver_uar.map) {
878*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to remap UAR pages\n");
879*4882a593Smuzhiyun ret = -ENOMEM;
880*4882a593Smuzhiyun goto err_unmap_regs;
881*4882a593Smuzhiyun }
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun dev->dsr_version = pvrdma_read_reg(dev, PVRDMA_REG_VERSION);
884*4882a593Smuzhiyun dev_info(&pdev->dev, "device version %d, driver version %d\n",
885*4882a593Smuzhiyun dev->dsr_version, PVRDMA_VERSION);
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun dev->dsr = dma_alloc_coherent(&pdev->dev, sizeof(*dev->dsr),
888*4882a593Smuzhiyun &dev->dsrbase, GFP_KERNEL);
889*4882a593Smuzhiyun if (!dev->dsr) {
890*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to allocate shared region\n");
891*4882a593Smuzhiyun ret = -ENOMEM;
892*4882a593Smuzhiyun goto err_uar_unmap;
893*4882a593Smuzhiyun }
894*4882a593Smuzhiyun
895*4882a593Smuzhiyun /* Setup the shared region */
896*4882a593Smuzhiyun dev->dsr->driver_version = PVRDMA_VERSION;
897*4882a593Smuzhiyun dev->dsr->gos_info.gos_bits = sizeof(void *) == 4 ?
898*4882a593Smuzhiyun PVRDMA_GOS_BITS_32 :
899*4882a593Smuzhiyun PVRDMA_GOS_BITS_64;
900*4882a593Smuzhiyun dev->dsr->gos_info.gos_type = PVRDMA_GOS_TYPE_LINUX;
901*4882a593Smuzhiyun dev->dsr->gos_info.gos_ver = 1;
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun if (dev->dsr_version < PVRDMA_PPN64_VERSION)
904*4882a593Smuzhiyun dev->dsr->uar_pfn = dev->driver_uar.pfn;
905*4882a593Smuzhiyun else
906*4882a593Smuzhiyun dev->dsr->uar_pfn64 = dev->driver_uar.pfn;
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun /* Command slot. */
909*4882a593Smuzhiyun dev->cmd_slot = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
910*4882a593Smuzhiyun &slot_dma, GFP_KERNEL);
911*4882a593Smuzhiyun if (!dev->cmd_slot) {
912*4882a593Smuzhiyun ret = -ENOMEM;
913*4882a593Smuzhiyun goto err_free_dsr;
914*4882a593Smuzhiyun }
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun dev->dsr->cmd_slot_dma = (u64)slot_dma;
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun /* Response slot. */
919*4882a593Smuzhiyun dev->resp_slot = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
920*4882a593Smuzhiyun &slot_dma, GFP_KERNEL);
921*4882a593Smuzhiyun if (!dev->resp_slot) {
922*4882a593Smuzhiyun ret = -ENOMEM;
923*4882a593Smuzhiyun goto err_free_slots;
924*4882a593Smuzhiyun }
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun dev->dsr->resp_slot_dma = (u64)slot_dma;
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun /* Async event ring */
929*4882a593Smuzhiyun dev->dsr->async_ring_pages.num_pages = PVRDMA_NUM_RING_PAGES;
930*4882a593Smuzhiyun ret = pvrdma_page_dir_init(dev, &dev->async_pdir,
931*4882a593Smuzhiyun dev->dsr->async_ring_pages.num_pages, true);
932*4882a593Smuzhiyun if (ret)
933*4882a593Smuzhiyun goto err_free_slots;
934*4882a593Smuzhiyun dev->async_ring_state = dev->async_pdir.pages[0];
935*4882a593Smuzhiyun dev->dsr->async_ring_pages.pdir_dma = dev->async_pdir.dir_dma;
936*4882a593Smuzhiyun
937*4882a593Smuzhiyun /* CQ notification ring */
938*4882a593Smuzhiyun dev->dsr->cq_ring_pages.num_pages = PVRDMA_NUM_RING_PAGES;
939*4882a593Smuzhiyun ret = pvrdma_page_dir_init(dev, &dev->cq_pdir,
940*4882a593Smuzhiyun dev->dsr->cq_ring_pages.num_pages, true);
941*4882a593Smuzhiyun if (ret)
942*4882a593Smuzhiyun goto err_free_async_ring;
943*4882a593Smuzhiyun dev->cq_ring_state = dev->cq_pdir.pages[0];
944*4882a593Smuzhiyun dev->dsr->cq_ring_pages.pdir_dma = dev->cq_pdir.dir_dma;
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun /*
947*4882a593Smuzhiyun * Write the PA of the shared region to the device. The writes must be
948*4882a593Smuzhiyun * ordered such that the high bits are written last. When the writes
949*4882a593Smuzhiyun * complete, the device will have filled out the capabilities.
950*4882a593Smuzhiyun */
951*4882a593Smuzhiyun
952*4882a593Smuzhiyun pvrdma_write_reg(dev, PVRDMA_REG_DSRLOW, (u32)dev->dsrbase);
953*4882a593Smuzhiyun pvrdma_write_reg(dev, PVRDMA_REG_DSRHIGH,
954*4882a593Smuzhiyun (u32)((u64)(dev->dsrbase) >> 32));
955*4882a593Smuzhiyun
956*4882a593Smuzhiyun /* Make sure the write is complete before reading status. */
957*4882a593Smuzhiyun mb();
958*4882a593Smuzhiyun
959*4882a593Smuzhiyun /* The driver supports RoCE V1 and V2. */
960*4882a593Smuzhiyun if (!PVRDMA_SUPPORTED(dev)) {
961*4882a593Smuzhiyun dev_err(&pdev->dev, "driver needs RoCE v1 or v2 support\n");
962*4882a593Smuzhiyun ret = -EFAULT;
963*4882a593Smuzhiyun goto err_free_cq_ring;
964*4882a593Smuzhiyun }
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun /* Paired vmxnet3 will have same bus, slot. But func will be 0 */
967*4882a593Smuzhiyun pdev_net = pci_get_slot(pdev->bus, PCI_DEVFN(PCI_SLOT(pdev->devfn), 0));
968*4882a593Smuzhiyun if (!pdev_net) {
969*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to find paired net device\n");
970*4882a593Smuzhiyun ret = -ENODEV;
971*4882a593Smuzhiyun goto err_free_cq_ring;
972*4882a593Smuzhiyun }
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun if (pdev_net->vendor != PCI_VENDOR_ID_VMWARE ||
975*4882a593Smuzhiyun pdev_net->device != PCI_DEVICE_ID_VMWARE_VMXNET3) {
976*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to find paired vmxnet3 device\n");
977*4882a593Smuzhiyun pci_dev_put(pdev_net);
978*4882a593Smuzhiyun ret = -ENODEV;
979*4882a593Smuzhiyun goto err_free_cq_ring;
980*4882a593Smuzhiyun }
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun dev->netdev = pci_get_drvdata(pdev_net);
983*4882a593Smuzhiyun pci_dev_put(pdev_net);
984*4882a593Smuzhiyun if (!dev->netdev) {
985*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to get vmxnet3 device\n");
986*4882a593Smuzhiyun ret = -ENODEV;
987*4882a593Smuzhiyun goto err_free_cq_ring;
988*4882a593Smuzhiyun }
989*4882a593Smuzhiyun dev_hold(dev->netdev);
990*4882a593Smuzhiyun
991*4882a593Smuzhiyun dev_info(&pdev->dev, "paired device to %s\n", dev->netdev->name);
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun /* Interrupt setup */
994*4882a593Smuzhiyun ret = pvrdma_alloc_intrs(dev);
995*4882a593Smuzhiyun if (ret) {
996*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to allocate interrupts\n");
997*4882a593Smuzhiyun ret = -ENOMEM;
998*4882a593Smuzhiyun goto err_free_cq_ring;
999*4882a593Smuzhiyun }
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun /* Allocate UAR table. */
1002*4882a593Smuzhiyun ret = pvrdma_uar_table_init(dev);
1003*4882a593Smuzhiyun if (ret) {
1004*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to allocate UAR table\n");
1005*4882a593Smuzhiyun ret = -ENOMEM;
1006*4882a593Smuzhiyun goto err_free_intrs;
1007*4882a593Smuzhiyun }
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun /* Allocate GID table */
1010*4882a593Smuzhiyun dev->sgid_tbl = kcalloc(dev->dsr->caps.gid_tbl_len,
1011*4882a593Smuzhiyun sizeof(union ib_gid), GFP_KERNEL);
1012*4882a593Smuzhiyun if (!dev->sgid_tbl) {
1013*4882a593Smuzhiyun ret = -ENOMEM;
1014*4882a593Smuzhiyun goto err_free_uar_table;
1015*4882a593Smuzhiyun }
1016*4882a593Smuzhiyun dev_dbg(&pdev->dev, "gid table len %d\n", dev->dsr->caps.gid_tbl_len);
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun pvrdma_enable_intrs(dev);
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun /* Activate pvrdma device */
1021*4882a593Smuzhiyun pvrdma_write_reg(dev, PVRDMA_REG_CTL, PVRDMA_DEVICE_CTL_ACTIVATE);
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun /* Make sure the write is complete before reading status. */
1024*4882a593Smuzhiyun mb();
1025*4882a593Smuzhiyun
1026*4882a593Smuzhiyun /* Check if device was successfully activated */
1027*4882a593Smuzhiyun ret = pvrdma_read_reg(dev, PVRDMA_REG_ERR);
1028*4882a593Smuzhiyun if (ret != 0) {
1029*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to activate device\n");
1030*4882a593Smuzhiyun ret = -EFAULT;
1031*4882a593Smuzhiyun goto err_disable_intr;
1032*4882a593Smuzhiyun }
1033*4882a593Smuzhiyun
1034*4882a593Smuzhiyun /* Register IB device */
1035*4882a593Smuzhiyun ret = pvrdma_register_device(dev);
1036*4882a593Smuzhiyun if (ret) {
1037*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to register IB device\n");
1038*4882a593Smuzhiyun goto err_disable_intr;
1039*4882a593Smuzhiyun }
1040*4882a593Smuzhiyun
1041*4882a593Smuzhiyun dev->nb_netdev.notifier_call = pvrdma_netdevice_event;
1042*4882a593Smuzhiyun ret = register_netdevice_notifier(&dev->nb_netdev);
1043*4882a593Smuzhiyun if (ret) {
1044*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to register netdevice events\n");
1045*4882a593Smuzhiyun goto err_unreg_ibdev;
1046*4882a593Smuzhiyun }
1047*4882a593Smuzhiyun
1048*4882a593Smuzhiyun dev_info(&pdev->dev, "attached to device\n");
1049*4882a593Smuzhiyun return 0;
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun err_unreg_ibdev:
1052*4882a593Smuzhiyun ib_unregister_device(&dev->ib_dev);
1053*4882a593Smuzhiyun err_disable_intr:
1054*4882a593Smuzhiyun pvrdma_disable_intrs(dev);
1055*4882a593Smuzhiyun kfree(dev->sgid_tbl);
1056*4882a593Smuzhiyun err_free_uar_table:
1057*4882a593Smuzhiyun pvrdma_uar_table_cleanup(dev);
1058*4882a593Smuzhiyun err_free_intrs:
1059*4882a593Smuzhiyun pvrdma_free_irq(dev);
1060*4882a593Smuzhiyun pci_free_irq_vectors(pdev);
1061*4882a593Smuzhiyun err_free_cq_ring:
1062*4882a593Smuzhiyun if (dev->netdev) {
1063*4882a593Smuzhiyun dev_put(dev->netdev);
1064*4882a593Smuzhiyun dev->netdev = NULL;
1065*4882a593Smuzhiyun }
1066*4882a593Smuzhiyun pvrdma_page_dir_cleanup(dev, &dev->cq_pdir);
1067*4882a593Smuzhiyun err_free_async_ring:
1068*4882a593Smuzhiyun pvrdma_page_dir_cleanup(dev, &dev->async_pdir);
1069*4882a593Smuzhiyun err_free_slots:
1070*4882a593Smuzhiyun pvrdma_free_slots(dev);
1071*4882a593Smuzhiyun err_free_dsr:
1072*4882a593Smuzhiyun dma_free_coherent(&pdev->dev, sizeof(*dev->dsr), dev->dsr,
1073*4882a593Smuzhiyun dev->dsrbase);
1074*4882a593Smuzhiyun err_uar_unmap:
1075*4882a593Smuzhiyun iounmap(dev->driver_uar.map);
1076*4882a593Smuzhiyun err_unmap_regs:
1077*4882a593Smuzhiyun iounmap(dev->regs);
1078*4882a593Smuzhiyun err_free_resource:
1079*4882a593Smuzhiyun pci_release_regions(pdev);
1080*4882a593Smuzhiyun err_disable_pdev:
1081*4882a593Smuzhiyun pci_disable_device(pdev);
1082*4882a593Smuzhiyun pci_set_drvdata(pdev, NULL);
1083*4882a593Smuzhiyun err_free_device:
1084*4882a593Smuzhiyun mutex_lock(&pvrdma_device_list_lock);
1085*4882a593Smuzhiyun list_del(&dev->device_link);
1086*4882a593Smuzhiyun mutex_unlock(&pvrdma_device_list_lock);
1087*4882a593Smuzhiyun ib_dealloc_device(&dev->ib_dev);
1088*4882a593Smuzhiyun return ret;
1089*4882a593Smuzhiyun }
1090*4882a593Smuzhiyun
pvrdma_pci_remove(struct pci_dev * pdev)1091*4882a593Smuzhiyun static void pvrdma_pci_remove(struct pci_dev *pdev)
1092*4882a593Smuzhiyun {
1093*4882a593Smuzhiyun struct pvrdma_dev *dev = pci_get_drvdata(pdev);
1094*4882a593Smuzhiyun
1095*4882a593Smuzhiyun if (!dev)
1096*4882a593Smuzhiyun return;
1097*4882a593Smuzhiyun
1098*4882a593Smuzhiyun dev_info(&pdev->dev, "detaching from device\n");
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun unregister_netdevice_notifier(&dev->nb_netdev);
1101*4882a593Smuzhiyun dev->nb_netdev.notifier_call = NULL;
1102*4882a593Smuzhiyun
1103*4882a593Smuzhiyun flush_workqueue(event_wq);
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun if (dev->netdev) {
1106*4882a593Smuzhiyun dev_put(dev->netdev);
1107*4882a593Smuzhiyun dev->netdev = NULL;
1108*4882a593Smuzhiyun }
1109*4882a593Smuzhiyun
1110*4882a593Smuzhiyun /* Unregister ib device */
1111*4882a593Smuzhiyun ib_unregister_device(&dev->ib_dev);
1112*4882a593Smuzhiyun
1113*4882a593Smuzhiyun mutex_lock(&pvrdma_device_list_lock);
1114*4882a593Smuzhiyun list_del(&dev->device_link);
1115*4882a593Smuzhiyun mutex_unlock(&pvrdma_device_list_lock);
1116*4882a593Smuzhiyun
1117*4882a593Smuzhiyun pvrdma_disable_intrs(dev);
1118*4882a593Smuzhiyun pvrdma_free_irq(dev);
1119*4882a593Smuzhiyun pci_free_irq_vectors(pdev);
1120*4882a593Smuzhiyun
1121*4882a593Smuzhiyun /* Deactivate pvrdma device */
1122*4882a593Smuzhiyun pvrdma_write_reg(dev, PVRDMA_REG_CTL, PVRDMA_DEVICE_CTL_RESET);
1123*4882a593Smuzhiyun pvrdma_page_dir_cleanup(dev, &dev->cq_pdir);
1124*4882a593Smuzhiyun pvrdma_page_dir_cleanup(dev, &dev->async_pdir);
1125*4882a593Smuzhiyun pvrdma_free_slots(dev);
1126*4882a593Smuzhiyun dma_free_coherent(&pdev->dev, sizeof(*dev->dsr), dev->dsr,
1127*4882a593Smuzhiyun dev->dsrbase);
1128*4882a593Smuzhiyun
1129*4882a593Smuzhiyun iounmap(dev->regs);
1130*4882a593Smuzhiyun kfree(dev->sgid_tbl);
1131*4882a593Smuzhiyun kfree(dev->cq_tbl);
1132*4882a593Smuzhiyun kfree(dev->srq_tbl);
1133*4882a593Smuzhiyun kfree(dev->qp_tbl);
1134*4882a593Smuzhiyun pvrdma_uar_table_cleanup(dev);
1135*4882a593Smuzhiyun iounmap(dev->driver_uar.map);
1136*4882a593Smuzhiyun
1137*4882a593Smuzhiyun ib_dealloc_device(&dev->ib_dev);
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun /* Free pci resources */
1140*4882a593Smuzhiyun pci_release_regions(pdev);
1141*4882a593Smuzhiyun pci_disable_device(pdev);
1142*4882a593Smuzhiyun pci_set_drvdata(pdev, NULL);
1143*4882a593Smuzhiyun }
1144*4882a593Smuzhiyun
1145*4882a593Smuzhiyun static const struct pci_device_id pvrdma_pci_table[] = {
1146*4882a593Smuzhiyun { PCI_DEVICE(PCI_VENDOR_ID_VMWARE, PCI_DEVICE_ID_VMWARE_PVRDMA), },
1147*4882a593Smuzhiyun { 0 },
1148*4882a593Smuzhiyun };
1149*4882a593Smuzhiyun
1150*4882a593Smuzhiyun MODULE_DEVICE_TABLE(pci, pvrdma_pci_table);
1151*4882a593Smuzhiyun
1152*4882a593Smuzhiyun static struct pci_driver pvrdma_driver = {
1153*4882a593Smuzhiyun .name = DRV_NAME,
1154*4882a593Smuzhiyun .id_table = pvrdma_pci_table,
1155*4882a593Smuzhiyun .probe = pvrdma_pci_probe,
1156*4882a593Smuzhiyun .remove = pvrdma_pci_remove,
1157*4882a593Smuzhiyun };
1158*4882a593Smuzhiyun
pvrdma_init(void)1159*4882a593Smuzhiyun static int __init pvrdma_init(void)
1160*4882a593Smuzhiyun {
1161*4882a593Smuzhiyun int err;
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun event_wq = alloc_ordered_workqueue("pvrdma_event_wq", WQ_MEM_RECLAIM);
1164*4882a593Smuzhiyun if (!event_wq)
1165*4882a593Smuzhiyun return -ENOMEM;
1166*4882a593Smuzhiyun
1167*4882a593Smuzhiyun err = pci_register_driver(&pvrdma_driver);
1168*4882a593Smuzhiyun if (err)
1169*4882a593Smuzhiyun destroy_workqueue(event_wq);
1170*4882a593Smuzhiyun
1171*4882a593Smuzhiyun return err;
1172*4882a593Smuzhiyun }
1173*4882a593Smuzhiyun
pvrdma_cleanup(void)1174*4882a593Smuzhiyun static void __exit pvrdma_cleanup(void)
1175*4882a593Smuzhiyun {
1176*4882a593Smuzhiyun pci_unregister_driver(&pvrdma_driver);
1177*4882a593Smuzhiyun
1178*4882a593Smuzhiyun destroy_workqueue(event_wq);
1179*4882a593Smuzhiyun }
1180*4882a593Smuzhiyun
1181*4882a593Smuzhiyun module_init(pvrdma_init);
1182*4882a593Smuzhiyun module_exit(pvrdma_cleanup);
1183*4882a593Smuzhiyun
1184*4882a593Smuzhiyun MODULE_AUTHOR("VMware, Inc");
1185*4882a593Smuzhiyun MODULE_DESCRIPTION("VMware Paravirtual RDMA driver");
1186*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
1187