1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2012-2016 VMware, Inc. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
5*4882a593Smuzhiyun * modify it under the terms of EITHER the GNU General Public License
6*4882a593Smuzhiyun * version 2 as published by the Free Software Foundation or the BSD
7*4882a593Smuzhiyun * 2-Clause License. This program is distributed in the hope that it
8*4882a593Smuzhiyun * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
9*4882a593Smuzhiyun * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
10*4882a593Smuzhiyun * See the GNU General Public License version 2 for more details at
11*4882a593Smuzhiyun * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License
14*4882a593Smuzhiyun * along with this program available in the file COPYING in the main
15*4882a593Smuzhiyun * directory of this source tree.
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * The BSD 2-Clause License
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
20*4882a593Smuzhiyun * without modification, are permitted provided that the following
21*4882a593Smuzhiyun * conditions are met:
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * - Redistributions of source code must retain the above
24*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
25*4882a593Smuzhiyun * disclaimer.
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
28*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
29*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
30*4882a593Smuzhiyun * provided with the distribution.
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33*4882a593Smuzhiyun * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34*4882a593Smuzhiyun * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35*4882a593Smuzhiyun * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36*4882a593Smuzhiyun * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
37*4882a593Smuzhiyun * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38*4882a593Smuzhiyun * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
39*4882a593Smuzhiyun * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40*4882a593Smuzhiyun * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41*4882a593Smuzhiyun * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42*4882a593Smuzhiyun * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43*4882a593Smuzhiyun * OF THE POSSIBILITY OF SUCH DAMAGE.
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun #ifndef __PVRDMA_H__
47*4882a593Smuzhiyun #define __PVRDMA_H__
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #include <linux/compiler.h>
50*4882a593Smuzhiyun #include <linux/interrupt.h>
51*4882a593Smuzhiyun #include <linux/list.h>
52*4882a593Smuzhiyun #include <linux/mutex.h>
53*4882a593Smuzhiyun #include <linux/pci.h>
54*4882a593Smuzhiyun #include <linux/semaphore.h>
55*4882a593Smuzhiyun #include <linux/workqueue.h>
56*4882a593Smuzhiyun #include <rdma/ib_umem.h>
57*4882a593Smuzhiyun #include <rdma/ib_verbs.h>
58*4882a593Smuzhiyun #include <rdma/vmw_pvrdma-abi.h>
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #include "pvrdma_ring.h"
61*4882a593Smuzhiyun #include "pvrdma_dev_api.h"
62*4882a593Smuzhiyun #include "pvrdma_verbs.h"
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* NOT the same as BIT_MASK(). */
65*4882a593Smuzhiyun #define PVRDMA_MASK(n) ((n << 1) - 1)
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /*
68*4882a593Smuzhiyun * VMware PVRDMA PCI device id.
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun #define PCI_DEVICE_ID_VMWARE_PVRDMA 0x0820
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #define PVRDMA_NUM_RING_PAGES 4
73*4882a593Smuzhiyun #define PVRDMA_QP_NUM_HEADER_PAGES 1
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun struct pvrdma_dev;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun struct pvrdma_page_dir {
78*4882a593Smuzhiyun dma_addr_t dir_dma;
79*4882a593Smuzhiyun u64 *dir;
80*4882a593Smuzhiyun int ntables;
81*4882a593Smuzhiyun u64 **tables;
82*4882a593Smuzhiyun u64 npages;
83*4882a593Smuzhiyun void **pages;
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun struct pvrdma_cq {
87*4882a593Smuzhiyun struct ib_cq ibcq;
88*4882a593Smuzhiyun int offset;
89*4882a593Smuzhiyun spinlock_t cq_lock; /* Poll lock. */
90*4882a593Smuzhiyun struct pvrdma_uar_map *uar;
91*4882a593Smuzhiyun struct ib_umem *umem;
92*4882a593Smuzhiyun struct pvrdma_ring_state *ring_state;
93*4882a593Smuzhiyun struct pvrdma_page_dir pdir;
94*4882a593Smuzhiyun u32 cq_handle;
95*4882a593Smuzhiyun bool is_kernel;
96*4882a593Smuzhiyun refcount_t refcnt;
97*4882a593Smuzhiyun struct completion free;
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun struct pvrdma_id_table {
101*4882a593Smuzhiyun u32 last;
102*4882a593Smuzhiyun u32 top;
103*4882a593Smuzhiyun u32 max;
104*4882a593Smuzhiyun u32 mask;
105*4882a593Smuzhiyun spinlock_t lock; /* Table lock. */
106*4882a593Smuzhiyun unsigned long *table;
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun struct pvrdma_uar_map {
110*4882a593Smuzhiyun unsigned long pfn;
111*4882a593Smuzhiyun void __iomem *map;
112*4882a593Smuzhiyun int index;
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun struct pvrdma_uar_table {
116*4882a593Smuzhiyun struct pvrdma_id_table tbl;
117*4882a593Smuzhiyun int size;
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun struct pvrdma_ucontext {
121*4882a593Smuzhiyun struct ib_ucontext ibucontext;
122*4882a593Smuzhiyun struct pvrdma_dev *dev;
123*4882a593Smuzhiyun struct pvrdma_uar_map uar;
124*4882a593Smuzhiyun u64 ctx_handle;
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun struct pvrdma_pd {
128*4882a593Smuzhiyun struct ib_pd ibpd;
129*4882a593Smuzhiyun u32 pdn;
130*4882a593Smuzhiyun u32 pd_handle;
131*4882a593Smuzhiyun int privileged;
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun struct pvrdma_mr {
135*4882a593Smuzhiyun u32 mr_handle;
136*4882a593Smuzhiyun u64 iova;
137*4882a593Smuzhiyun u64 size;
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun struct pvrdma_user_mr {
141*4882a593Smuzhiyun struct ib_mr ibmr;
142*4882a593Smuzhiyun struct ib_umem *umem;
143*4882a593Smuzhiyun struct pvrdma_mr mmr;
144*4882a593Smuzhiyun struct pvrdma_page_dir pdir;
145*4882a593Smuzhiyun u64 *pages;
146*4882a593Smuzhiyun u32 npages;
147*4882a593Smuzhiyun u32 max_pages;
148*4882a593Smuzhiyun u32 page_shift;
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun struct pvrdma_wq {
152*4882a593Smuzhiyun struct pvrdma_ring *ring;
153*4882a593Smuzhiyun spinlock_t lock; /* Work queue lock. */
154*4882a593Smuzhiyun int wqe_cnt;
155*4882a593Smuzhiyun int wqe_size;
156*4882a593Smuzhiyun int max_sg;
157*4882a593Smuzhiyun int offset;
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun struct pvrdma_ah {
161*4882a593Smuzhiyun struct ib_ah ibah;
162*4882a593Smuzhiyun struct pvrdma_av av;
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun struct pvrdma_srq {
166*4882a593Smuzhiyun struct ib_srq ibsrq;
167*4882a593Smuzhiyun int offset;
168*4882a593Smuzhiyun spinlock_t lock; /* SRQ lock. */
169*4882a593Smuzhiyun int wqe_cnt;
170*4882a593Smuzhiyun int wqe_size;
171*4882a593Smuzhiyun int max_gs;
172*4882a593Smuzhiyun struct ib_umem *umem;
173*4882a593Smuzhiyun struct pvrdma_ring_state *ring;
174*4882a593Smuzhiyun struct pvrdma_page_dir pdir;
175*4882a593Smuzhiyun u32 srq_handle;
176*4882a593Smuzhiyun int npages;
177*4882a593Smuzhiyun refcount_t refcnt;
178*4882a593Smuzhiyun struct completion free;
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun struct pvrdma_qp {
182*4882a593Smuzhiyun struct ib_qp ibqp;
183*4882a593Smuzhiyun u32 qp_handle;
184*4882a593Smuzhiyun u32 qkey;
185*4882a593Smuzhiyun struct pvrdma_wq sq;
186*4882a593Smuzhiyun struct pvrdma_wq rq;
187*4882a593Smuzhiyun struct ib_umem *rumem;
188*4882a593Smuzhiyun struct ib_umem *sumem;
189*4882a593Smuzhiyun struct pvrdma_page_dir pdir;
190*4882a593Smuzhiyun struct pvrdma_srq *srq;
191*4882a593Smuzhiyun int npages;
192*4882a593Smuzhiyun int npages_send;
193*4882a593Smuzhiyun int npages_recv;
194*4882a593Smuzhiyun u32 flags;
195*4882a593Smuzhiyun u8 port;
196*4882a593Smuzhiyun u8 state;
197*4882a593Smuzhiyun bool is_kernel;
198*4882a593Smuzhiyun struct mutex mutex; /* QP state mutex. */
199*4882a593Smuzhiyun refcount_t refcnt;
200*4882a593Smuzhiyun struct completion free;
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun struct pvrdma_dev {
204*4882a593Smuzhiyun /* PCI device-related information. */
205*4882a593Smuzhiyun struct ib_device ib_dev;
206*4882a593Smuzhiyun struct pci_dev *pdev;
207*4882a593Smuzhiyun void __iomem *regs;
208*4882a593Smuzhiyun struct pvrdma_device_shared_region *dsr; /* Shared region pointer */
209*4882a593Smuzhiyun dma_addr_t dsrbase; /* Shared region base address */
210*4882a593Smuzhiyun void *cmd_slot;
211*4882a593Smuzhiyun void *resp_slot;
212*4882a593Smuzhiyun unsigned long flags;
213*4882a593Smuzhiyun struct list_head device_link;
214*4882a593Smuzhiyun unsigned int dsr_version;
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun /* Locking and interrupt information. */
217*4882a593Smuzhiyun spinlock_t cmd_lock; /* Command lock. */
218*4882a593Smuzhiyun struct semaphore cmd_sema;
219*4882a593Smuzhiyun struct completion cmd_done;
220*4882a593Smuzhiyun unsigned int nr_vectors;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun /* RDMA-related device information. */
223*4882a593Smuzhiyun union ib_gid *sgid_tbl;
224*4882a593Smuzhiyun struct pvrdma_ring_state *async_ring_state;
225*4882a593Smuzhiyun struct pvrdma_page_dir async_pdir;
226*4882a593Smuzhiyun struct pvrdma_ring_state *cq_ring_state;
227*4882a593Smuzhiyun struct pvrdma_page_dir cq_pdir;
228*4882a593Smuzhiyun struct pvrdma_cq **cq_tbl;
229*4882a593Smuzhiyun spinlock_t cq_tbl_lock;
230*4882a593Smuzhiyun struct pvrdma_srq **srq_tbl;
231*4882a593Smuzhiyun spinlock_t srq_tbl_lock;
232*4882a593Smuzhiyun struct pvrdma_qp **qp_tbl;
233*4882a593Smuzhiyun spinlock_t qp_tbl_lock;
234*4882a593Smuzhiyun struct pvrdma_uar_table uar_table;
235*4882a593Smuzhiyun struct pvrdma_uar_map driver_uar;
236*4882a593Smuzhiyun __be64 sys_image_guid;
237*4882a593Smuzhiyun spinlock_t desc_lock; /* Device modification lock. */
238*4882a593Smuzhiyun u32 port_cap_mask;
239*4882a593Smuzhiyun struct mutex port_mutex; /* Port modification mutex. */
240*4882a593Smuzhiyun bool ib_active;
241*4882a593Smuzhiyun atomic_t num_qps;
242*4882a593Smuzhiyun atomic_t num_cqs;
243*4882a593Smuzhiyun atomic_t num_srqs;
244*4882a593Smuzhiyun atomic_t num_pds;
245*4882a593Smuzhiyun atomic_t num_ahs;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun /* Network device information. */
248*4882a593Smuzhiyun struct net_device *netdev;
249*4882a593Smuzhiyun struct notifier_block nb_netdev;
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun struct pvrdma_netdevice_work {
253*4882a593Smuzhiyun struct work_struct work;
254*4882a593Smuzhiyun struct net_device *event_netdev;
255*4882a593Smuzhiyun unsigned long event;
256*4882a593Smuzhiyun };
257*4882a593Smuzhiyun
to_vdev(struct ib_device * ibdev)258*4882a593Smuzhiyun static inline struct pvrdma_dev *to_vdev(struct ib_device *ibdev)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun return container_of(ibdev, struct pvrdma_dev, ib_dev);
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun static inline struct
to_vucontext(struct ib_ucontext * ibucontext)264*4882a593Smuzhiyun pvrdma_ucontext *to_vucontext(struct ib_ucontext *ibucontext)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun return container_of(ibucontext, struct pvrdma_ucontext, ibucontext);
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
to_vpd(struct ib_pd * ibpd)269*4882a593Smuzhiyun static inline struct pvrdma_pd *to_vpd(struct ib_pd *ibpd)
270*4882a593Smuzhiyun {
271*4882a593Smuzhiyun return container_of(ibpd, struct pvrdma_pd, ibpd);
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
to_vcq(struct ib_cq * ibcq)274*4882a593Smuzhiyun static inline struct pvrdma_cq *to_vcq(struct ib_cq *ibcq)
275*4882a593Smuzhiyun {
276*4882a593Smuzhiyun return container_of(ibcq, struct pvrdma_cq, ibcq);
277*4882a593Smuzhiyun }
278*4882a593Smuzhiyun
to_vsrq(struct ib_srq * ibsrq)279*4882a593Smuzhiyun static inline struct pvrdma_srq *to_vsrq(struct ib_srq *ibsrq)
280*4882a593Smuzhiyun {
281*4882a593Smuzhiyun return container_of(ibsrq, struct pvrdma_srq, ibsrq);
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
to_vmr(struct ib_mr * ibmr)284*4882a593Smuzhiyun static inline struct pvrdma_user_mr *to_vmr(struct ib_mr *ibmr)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun return container_of(ibmr, struct pvrdma_user_mr, ibmr);
287*4882a593Smuzhiyun }
288*4882a593Smuzhiyun
to_vqp(struct ib_qp * ibqp)289*4882a593Smuzhiyun static inline struct pvrdma_qp *to_vqp(struct ib_qp *ibqp)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun return container_of(ibqp, struct pvrdma_qp, ibqp);
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun
to_vah(struct ib_ah * ibah)294*4882a593Smuzhiyun static inline struct pvrdma_ah *to_vah(struct ib_ah *ibah)
295*4882a593Smuzhiyun {
296*4882a593Smuzhiyun return container_of(ibah, struct pvrdma_ah, ibah);
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun
pvrdma_write_reg(struct pvrdma_dev * dev,u32 reg,u32 val)299*4882a593Smuzhiyun static inline void pvrdma_write_reg(struct pvrdma_dev *dev, u32 reg, u32 val)
300*4882a593Smuzhiyun {
301*4882a593Smuzhiyun writel(cpu_to_le32(val), dev->regs + reg);
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
pvrdma_read_reg(struct pvrdma_dev * dev,u32 reg)304*4882a593Smuzhiyun static inline u32 pvrdma_read_reg(struct pvrdma_dev *dev, u32 reg)
305*4882a593Smuzhiyun {
306*4882a593Smuzhiyun return le32_to_cpu(readl(dev->regs + reg));
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
pvrdma_write_uar_cq(struct pvrdma_dev * dev,u32 val)309*4882a593Smuzhiyun static inline void pvrdma_write_uar_cq(struct pvrdma_dev *dev, u32 val)
310*4882a593Smuzhiyun {
311*4882a593Smuzhiyun writel(cpu_to_le32(val), dev->driver_uar.map + PVRDMA_UAR_CQ_OFFSET);
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun
pvrdma_write_uar_qp(struct pvrdma_dev * dev,u32 val)314*4882a593Smuzhiyun static inline void pvrdma_write_uar_qp(struct pvrdma_dev *dev, u32 val)
315*4882a593Smuzhiyun {
316*4882a593Smuzhiyun writel(cpu_to_le32(val), dev->driver_uar.map + PVRDMA_UAR_QP_OFFSET);
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
pvrdma_page_dir_get_ptr(struct pvrdma_page_dir * pdir,u64 offset)319*4882a593Smuzhiyun static inline void *pvrdma_page_dir_get_ptr(struct pvrdma_page_dir *pdir,
320*4882a593Smuzhiyun u64 offset)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun return pdir->pages[offset / PAGE_SIZE] + (offset % PAGE_SIZE);
323*4882a593Smuzhiyun }
324*4882a593Smuzhiyun
ib_mtu_to_pvrdma(enum ib_mtu mtu)325*4882a593Smuzhiyun static inline enum pvrdma_mtu ib_mtu_to_pvrdma(enum ib_mtu mtu)
326*4882a593Smuzhiyun {
327*4882a593Smuzhiyun return (enum pvrdma_mtu)mtu;
328*4882a593Smuzhiyun }
329*4882a593Smuzhiyun
pvrdma_mtu_to_ib(enum pvrdma_mtu mtu)330*4882a593Smuzhiyun static inline enum ib_mtu pvrdma_mtu_to_ib(enum pvrdma_mtu mtu)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun return (enum ib_mtu)mtu;
333*4882a593Smuzhiyun }
334*4882a593Smuzhiyun
ib_port_state_to_pvrdma(enum ib_port_state state)335*4882a593Smuzhiyun static inline enum pvrdma_port_state ib_port_state_to_pvrdma(
336*4882a593Smuzhiyun enum ib_port_state state)
337*4882a593Smuzhiyun {
338*4882a593Smuzhiyun return (enum pvrdma_port_state)state;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
pvrdma_port_state_to_ib(enum pvrdma_port_state state)341*4882a593Smuzhiyun static inline enum ib_port_state pvrdma_port_state_to_ib(
342*4882a593Smuzhiyun enum pvrdma_port_state state)
343*4882a593Smuzhiyun {
344*4882a593Smuzhiyun return (enum ib_port_state)state;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
ib_port_cap_flags_to_pvrdma(int flags)347*4882a593Smuzhiyun static inline int ib_port_cap_flags_to_pvrdma(int flags)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun return flags & PVRDMA_MASK(PVRDMA_PORT_CAP_FLAGS_MAX);
350*4882a593Smuzhiyun }
351*4882a593Smuzhiyun
pvrdma_port_cap_flags_to_ib(int flags)352*4882a593Smuzhiyun static inline int pvrdma_port_cap_flags_to_ib(int flags)
353*4882a593Smuzhiyun {
354*4882a593Smuzhiyun return flags;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun
ib_port_width_to_pvrdma(enum ib_port_width width)357*4882a593Smuzhiyun static inline enum pvrdma_port_width ib_port_width_to_pvrdma(
358*4882a593Smuzhiyun enum ib_port_width width)
359*4882a593Smuzhiyun {
360*4882a593Smuzhiyun return (enum pvrdma_port_width)width;
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
pvrdma_port_width_to_ib(enum pvrdma_port_width width)363*4882a593Smuzhiyun static inline enum ib_port_width pvrdma_port_width_to_ib(
364*4882a593Smuzhiyun enum pvrdma_port_width width)
365*4882a593Smuzhiyun {
366*4882a593Smuzhiyun return (enum ib_port_width)width;
367*4882a593Smuzhiyun }
368*4882a593Smuzhiyun
ib_port_speed_to_pvrdma(enum ib_port_speed speed)369*4882a593Smuzhiyun static inline enum pvrdma_port_speed ib_port_speed_to_pvrdma(
370*4882a593Smuzhiyun enum ib_port_speed speed)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun return (enum pvrdma_port_speed)speed;
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun
pvrdma_port_speed_to_ib(enum pvrdma_port_speed speed)375*4882a593Smuzhiyun static inline enum ib_port_speed pvrdma_port_speed_to_ib(
376*4882a593Smuzhiyun enum pvrdma_port_speed speed)
377*4882a593Smuzhiyun {
378*4882a593Smuzhiyun return (enum ib_port_speed)speed;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun
ib_qp_attr_mask_to_pvrdma(int attr_mask)381*4882a593Smuzhiyun static inline int ib_qp_attr_mask_to_pvrdma(int attr_mask)
382*4882a593Smuzhiyun {
383*4882a593Smuzhiyun return attr_mask & PVRDMA_MASK(PVRDMA_QP_ATTR_MASK_MAX);
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun
ib_mig_state_to_pvrdma(enum ib_mig_state state)386*4882a593Smuzhiyun static inline enum pvrdma_mig_state ib_mig_state_to_pvrdma(
387*4882a593Smuzhiyun enum ib_mig_state state)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun return (enum pvrdma_mig_state)state;
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun
pvrdma_mig_state_to_ib(enum pvrdma_mig_state state)392*4882a593Smuzhiyun static inline enum ib_mig_state pvrdma_mig_state_to_ib(
393*4882a593Smuzhiyun enum pvrdma_mig_state state)
394*4882a593Smuzhiyun {
395*4882a593Smuzhiyun return (enum ib_mig_state)state;
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun
ib_access_flags_to_pvrdma(int flags)398*4882a593Smuzhiyun static inline int ib_access_flags_to_pvrdma(int flags)
399*4882a593Smuzhiyun {
400*4882a593Smuzhiyun return flags;
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun
pvrdma_access_flags_to_ib(int flags)403*4882a593Smuzhiyun static inline int pvrdma_access_flags_to_ib(int flags)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun return flags & PVRDMA_MASK(PVRDMA_ACCESS_FLAGS_MAX);
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun
ib_qp_type_to_pvrdma(enum ib_qp_type type)408*4882a593Smuzhiyun static inline enum pvrdma_qp_type ib_qp_type_to_pvrdma(enum ib_qp_type type)
409*4882a593Smuzhiyun {
410*4882a593Smuzhiyun return (enum pvrdma_qp_type)type;
411*4882a593Smuzhiyun }
412*4882a593Smuzhiyun
pvrdma_qp_type_to_ib(enum pvrdma_qp_type type)413*4882a593Smuzhiyun static inline enum ib_qp_type pvrdma_qp_type_to_ib(enum pvrdma_qp_type type)
414*4882a593Smuzhiyun {
415*4882a593Smuzhiyun return (enum ib_qp_type)type;
416*4882a593Smuzhiyun }
417*4882a593Smuzhiyun
ib_qp_state_to_pvrdma(enum ib_qp_state state)418*4882a593Smuzhiyun static inline enum pvrdma_qp_state ib_qp_state_to_pvrdma(enum ib_qp_state state)
419*4882a593Smuzhiyun {
420*4882a593Smuzhiyun return (enum pvrdma_qp_state)state;
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun
pvrdma_qp_state_to_ib(enum pvrdma_qp_state state)423*4882a593Smuzhiyun static inline enum ib_qp_state pvrdma_qp_state_to_ib(enum pvrdma_qp_state state)
424*4882a593Smuzhiyun {
425*4882a593Smuzhiyun return (enum ib_qp_state)state;
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun
ib_wr_opcode_to_pvrdma(enum ib_wr_opcode op)428*4882a593Smuzhiyun static inline enum pvrdma_wr_opcode ib_wr_opcode_to_pvrdma(enum ib_wr_opcode op)
429*4882a593Smuzhiyun {
430*4882a593Smuzhiyun switch (op) {
431*4882a593Smuzhiyun case IB_WR_RDMA_WRITE:
432*4882a593Smuzhiyun return PVRDMA_WR_RDMA_WRITE;
433*4882a593Smuzhiyun case IB_WR_RDMA_WRITE_WITH_IMM:
434*4882a593Smuzhiyun return PVRDMA_WR_RDMA_WRITE_WITH_IMM;
435*4882a593Smuzhiyun case IB_WR_SEND:
436*4882a593Smuzhiyun return PVRDMA_WR_SEND;
437*4882a593Smuzhiyun case IB_WR_SEND_WITH_IMM:
438*4882a593Smuzhiyun return PVRDMA_WR_SEND_WITH_IMM;
439*4882a593Smuzhiyun case IB_WR_RDMA_READ:
440*4882a593Smuzhiyun return PVRDMA_WR_RDMA_READ;
441*4882a593Smuzhiyun case IB_WR_ATOMIC_CMP_AND_SWP:
442*4882a593Smuzhiyun return PVRDMA_WR_ATOMIC_CMP_AND_SWP;
443*4882a593Smuzhiyun case IB_WR_ATOMIC_FETCH_AND_ADD:
444*4882a593Smuzhiyun return PVRDMA_WR_ATOMIC_FETCH_AND_ADD;
445*4882a593Smuzhiyun case IB_WR_LSO:
446*4882a593Smuzhiyun return PVRDMA_WR_LSO;
447*4882a593Smuzhiyun case IB_WR_SEND_WITH_INV:
448*4882a593Smuzhiyun return PVRDMA_WR_SEND_WITH_INV;
449*4882a593Smuzhiyun case IB_WR_RDMA_READ_WITH_INV:
450*4882a593Smuzhiyun return PVRDMA_WR_RDMA_READ_WITH_INV;
451*4882a593Smuzhiyun case IB_WR_LOCAL_INV:
452*4882a593Smuzhiyun return PVRDMA_WR_LOCAL_INV;
453*4882a593Smuzhiyun case IB_WR_REG_MR:
454*4882a593Smuzhiyun return PVRDMA_WR_FAST_REG_MR;
455*4882a593Smuzhiyun case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
456*4882a593Smuzhiyun return PVRDMA_WR_MASKED_ATOMIC_CMP_AND_SWP;
457*4882a593Smuzhiyun case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
458*4882a593Smuzhiyun return PVRDMA_WR_MASKED_ATOMIC_FETCH_AND_ADD;
459*4882a593Smuzhiyun case IB_WR_REG_MR_INTEGRITY:
460*4882a593Smuzhiyun return PVRDMA_WR_REG_SIG_MR;
461*4882a593Smuzhiyun default:
462*4882a593Smuzhiyun return PVRDMA_WR_ERROR;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun
pvrdma_wc_status_to_ib(enum pvrdma_wc_status status)466*4882a593Smuzhiyun static inline enum ib_wc_status pvrdma_wc_status_to_ib(
467*4882a593Smuzhiyun enum pvrdma_wc_status status)
468*4882a593Smuzhiyun {
469*4882a593Smuzhiyun return (enum ib_wc_status)status;
470*4882a593Smuzhiyun }
471*4882a593Smuzhiyun
pvrdma_wc_opcode_to_ib(unsigned int opcode)472*4882a593Smuzhiyun static inline int pvrdma_wc_opcode_to_ib(unsigned int opcode)
473*4882a593Smuzhiyun {
474*4882a593Smuzhiyun switch (opcode) {
475*4882a593Smuzhiyun case PVRDMA_WC_SEND:
476*4882a593Smuzhiyun return IB_WC_SEND;
477*4882a593Smuzhiyun case PVRDMA_WC_RDMA_WRITE:
478*4882a593Smuzhiyun return IB_WC_RDMA_WRITE;
479*4882a593Smuzhiyun case PVRDMA_WC_RDMA_READ:
480*4882a593Smuzhiyun return IB_WC_RDMA_READ;
481*4882a593Smuzhiyun case PVRDMA_WC_COMP_SWAP:
482*4882a593Smuzhiyun return IB_WC_COMP_SWAP;
483*4882a593Smuzhiyun case PVRDMA_WC_FETCH_ADD:
484*4882a593Smuzhiyun return IB_WC_FETCH_ADD;
485*4882a593Smuzhiyun case PVRDMA_WC_LOCAL_INV:
486*4882a593Smuzhiyun return IB_WC_LOCAL_INV;
487*4882a593Smuzhiyun case PVRDMA_WC_FAST_REG_MR:
488*4882a593Smuzhiyun return IB_WC_REG_MR;
489*4882a593Smuzhiyun case PVRDMA_WC_MASKED_COMP_SWAP:
490*4882a593Smuzhiyun return IB_WC_MASKED_COMP_SWAP;
491*4882a593Smuzhiyun case PVRDMA_WC_MASKED_FETCH_ADD:
492*4882a593Smuzhiyun return IB_WC_MASKED_FETCH_ADD;
493*4882a593Smuzhiyun case PVRDMA_WC_RECV:
494*4882a593Smuzhiyun return IB_WC_RECV;
495*4882a593Smuzhiyun case PVRDMA_WC_RECV_RDMA_WITH_IMM:
496*4882a593Smuzhiyun return IB_WC_RECV_RDMA_WITH_IMM;
497*4882a593Smuzhiyun default:
498*4882a593Smuzhiyun return IB_WC_SEND;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun
pvrdma_wc_flags_to_ib(int flags)502*4882a593Smuzhiyun static inline int pvrdma_wc_flags_to_ib(int flags)
503*4882a593Smuzhiyun {
504*4882a593Smuzhiyun return flags;
505*4882a593Smuzhiyun }
506*4882a593Smuzhiyun
ib_send_flags_to_pvrdma(int flags)507*4882a593Smuzhiyun static inline int ib_send_flags_to_pvrdma(int flags)
508*4882a593Smuzhiyun {
509*4882a593Smuzhiyun return flags & PVRDMA_MASK(PVRDMA_SEND_FLAGS_MAX);
510*4882a593Smuzhiyun }
511*4882a593Smuzhiyun
pvrdma_network_type_to_ib(enum pvrdma_network_type type)512*4882a593Smuzhiyun static inline int pvrdma_network_type_to_ib(enum pvrdma_network_type type)
513*4882a593Smuzhiyun {
514*4882a593Smuzhiyun switch (type) {
515*4882a593Smuzhiyun case PVRDMA_NETWORK_ROCE_V1:
516*4882a593Smuzhiyun return RDMA_NETWORK_ROCE_V1;
517*4882a593Smuzhiyun case PVRDMA_NETWORK_IPV4:
518*4882a593Smuzhiyun return RDMA_NETWORK_IPV4;
519*4882a593Smuzhiyun case PVRDMA_NETWORK_IPV6:
520*4882a593Smuzhiyun return RDMA_NETWORK_IPV6;
521*4882a593Smuzhiyun default:
522*4882a593Smuzhiyun return RDMA_NETWORK_IPV6;
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun void pvrdma_qp_cap_to_ib(struct ib_qp_cap *dst,
527*4882a593Smuzhiyun const struct pvrdma_qp_cap *src);
528*4882a593Smuzhiyun void ib_qp_cap_to_pvrdma(struct pvrdma_qp_cap *dst,
529*4882a593Smuzhiyun const struct ib_qp_cap *src);
530*4882a593Smuzhiyun void pvrdma_gid_to_ib(union ib_gid *dst, const union pvrdma_gid *src);
531*4882a593Smuzhiyun void ib_gid_to_pvrdma(union pvrdma_gid *dst, const union ib_gid *src);
532*4882a593Smuzhiyun void pvrdma_global_route_to_ib(struct ib_global_route *dst,
533*4882a593Smuzhiyun const struct pvrdma_global_route *src);
534*4882a593Smuzhiyun void ib_global_route_to_pvrdma(struct pvrdma_global_route *dst,
535*4882a593Smuzhiyun const struct ib_global_route *src);
536*4882a593Smuzhiyun void pvrdma_ah_attr_to_rdma(struct rdma_ah_attr *dst,
537*4882a593Smuzhiyun const struct pvrdma_ah_attr *src);
538*4882a593Smuzhiyun void rdma_ah_attr_to_pvrdma(struct pvrdma_ah_attr *dst,
539*4882a593Smuzhiyun const struct rdma_ah_attr *src);
540*4882a593Smuzhiyun u8 ib_gid_type_to_pvrdma(enum ib_gid_type gid_type);
541*4882a593Smuzhiyun
542*4882a593Smuzhiyun int pvrdma_uar_table_init(struct pvrdma_dev *dev);
543*4882a593Smuzhiyun void pvrdma_uar_table_cleanup(struct pvrdma_dev *dev);
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun int pvrdma_uar_alloc(struct pvrdma_dev *dev, struct pvrdma_uar_map *uar);
546*4882a593Smuzhiyun void pvrdma_uar_free(struct pvrdma_dev *dev, struct pvrdma_uar_map *uar);
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun void _pvrdma_flush_cqe(struct pvrdma_qp *qp, struct pvrdma_cq *cq);
549*4882a593Smuzhiyun
550*4882a593Smuzhiyun int pvrdma_page_dir_init(struct pvrdma_dev *dev, struct pvrdma_page_dir *pdir,
551*4882a593Smuzhiyun u64 npages, bool alloc_pages);
552*4882a593Smuzhiyun void pvrdma_page_dir_cleanup(struct pvrdma_dev *dev,
553*4882a593Smuzhiyun struct pvrdma_page_dir *pdir);
554*4882a593Smuzhiyun int pvrdma_page_dir_insert_dma(struct pvrdma_page_dir *pdir, u64 idx,
555*4882a593Smuzhiyun dma_addr_t daddr);
556*4882a593Smuzhiyun int pvrdma_page_dir_insert_umem(struct pvrdma_page_dir *pdir,
557*4882a593Smuzhiyun struct ib_umem *umem, u64 offset);
558*4882a593Smuzhiyun dma_addr_t pvrdma_page_dir_get_dma(struct pvrdma_page_dir *pdir, u64 idx);
559*4882a593Smuzhiyun int pvrdma_page_dir_insert_page_list(struct pvrdma_page_dir *pdir,
560*4882a593Smuzhiyun u64 *page_list, int num_pages);
561*4882a593Smuzhiyun
562*4882a593Smuzhiyun int pvrdma_cmd_post(struct pvrdma_dev *dev, union pvrdma_cmd_req *req,
563*4882a593Smuzhiyun union pvrdma_cmd_resp *rsp, unsigned resp_code);
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun #endif /* __PVRDMA_H__ */
566