1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2005 Cisco Systems. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This software is available to you under a choice of one of two
5*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
6*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
7*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
8*4882a593Smuzhiyun * OpenIB.org BSD license below:
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
11*4882a593Smuzhiyun * without modification, are permitted provided that the following
12*4882a593Smuzhiyun * conditions are met:
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * - Redistributions of source code must retain the above
15*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
16*4882a593Smuzhiyun * disclaimer.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
19*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
20*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
21*4882a593Smuzhiyun * provided with the distribution.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30*4882a593Smuzhiyun * SOFTWARE.
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #ifndef MTHCA_WQE_H
34*4882a593Smuzhiyun #define MTHCA_WQE_H
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #include <linux/types.h>
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun enum {
39*4882a593Smuzhiyun MTHCA_NEXT_DBD = 1 << 7,
40*4882a593Smuzhiyun MTHCA_NEXT_FENCE = 1 << 6,
41*4882a593Smuzhiyun MTHCA_NEXT_CQ_UPDATE = 1 << 3,
42*4882a593Smuzhiyun MTHCA_NEXT_EVENT_GEN = 1 << 2,
43*4882a593Smuzhiyun MTHCA_NEXT_SOLICIT = 1 << 1,
44*4882a593Smuzhiyun MTHCA_NEXT_IP_CSUM = 1 << 4,
45*4882a593Smuzhiyun MTHCA_NEXT_TCP_UDP_CSUM = 1 << 5,
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun MTHCA_MLX_VL15 = 1 << 17,
48*4882a593Smuzhiyun MTHCA_MLX_SLR = 1 << 16
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun enum {
52*4882a593Smuzhiyun MTHCA_INVAL_LKEY = 0x100,
53*4882a593Smuzhiyun MTHCA_TAVOR_MAX_WQES_PER_RECV_DB = 256,
54*4882a593Smuzhiyun MTHCA_ARBEL_MAX_WQES_PER_SEND_DB = 255
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun struct mthca_next_seg {
58*4882a593Smuzhiyun __be32 nda_op; /* [31:6] next WQE [4:0] next opcode */
59*4882a593Smuzhiyun __be32 ee_nds; /* [31:8] next EE [7] DBD [6] F [5:0] next WQE size */
60*4882a593Smuzhiyun __be32 flags; /* [3] CQ [2] Event [1] Solicit */
61*4882a593Smuzhiyun __be32 imm; /* immediate data */
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun struct mthca_tavor_ud_seg {
65*4882a593Smuzhiyun u32 reserved1;
66*4882a593Smuzhiyun __be32 lkey;
67*4882a593Smuzhiyun __be64 av_addr;
68*4882a593Smuzhiyun u32 reserved2[4];
69*4882a593Smuzhiyun __be32 dqpn;
70*4882a593Smuzhiyun __be32 qkey;
71*4882a593Smuzhiyun u32 reserved3[2];
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun struct mthca_arbel_ud_seg {
75*4882a593Smuzhiyun __be32 av[8];
76*4882a593Smuzhiyun __be32 dqpn;
77*4882a593Smuzhiyun __be32 qkey;
78*4882a593Smuzhiyun u32 reserved[2];
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun struct mthca_bind_seg {
82*4882a593Smuzhiyun __be32 flags; /* [31] Atomic [30] rem write [29] rem read */
83*4882a593Smuzhiyun u32 reserved;
84*4882a593Smuzhiyun __be32 new_rkey;
85*4882a593Smuzhiyun __be32 lkey;
86*4882a593Smuzhiyun __be64 addr;
87*4882a593Smuzhiyun __be64 length;
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun struct mthca_raddr_seg {
91*4882a593Smuzhiyun __be64 raddr;
92*4882a593Smuzhiyun __be32 rkey;
93*4882a593Smuzhiyun u32 reserved;
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun struct mthca_atomic_seg {
97*4882a593Smuzhiyun __be64 swap_add;
98*4882a593Smuzhiyun __be64 compare;
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun struct mthca_data_seg {
102*4882a593Smuzhiyun __be32 byte_count;
103*4882a593Smuzhiyun __be32 lkey;
104*4882a593Smuzhiyun __be64 addr;
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun struct mthca_mlx_seg {
108*4882a593Smuzhiyun __be32 nda_op;
109*4882a593Smuzhiyun __be32 nds;
110*4882a593Smuzhiyun __be32 flags; /* [17] VL15 [16] SLR [14:12] static rate
111*4882a593Smuzhiyun [11:8] SL [3] C [2] E */
112*4882a593Smuzhiyun __be16 rlid;
113*4882a593Smuzhiyun __be16 vcrc;
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
mthca_set_data_seg(struct mthca_data_seg * dseg,struct ib_sge * sg)116*4882a593Smuzhiyun static __always_inline void mthca_set_data_seg(struct mthca_data_seg *dseg,
117*4882a593Smuzhiyun struct ib_sge *sg)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun dseg->byte_count = cpu_to_be32(sg->length);
120*4882a593Smuzhiyun dseg->lkey = cpu_to_be32(sg->lkey);
121*4882a593Smuzhiyun dseg->addr = cpu_to_be64(sg->addr);
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
mthca_set_data_seg_inval(struct mthca_data_seg * dseg)124*4882a593Smuzhiyun static __always_inline void mthca_set_data_seg_inval(struct mthca_data_seg *dseg)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun dseg->byte_count = 0;
127*4882a593Smuzhiyun dseg->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
128*4882a593Smuzhiyun dseg->addr = 0;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun #endif /* MTHCA_WQE_H */
132