xref: /OK3568_Linux_fs/kernel/drivers/infiniband/hw/mthca/mthca_reset.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * This software is available to you under a choice of one of two
5*4882a593Smuzhiyun  * licenses.  You may choose to be licensed under the terms of the GNU
6*4882a593Smuzhiyun  * General Public License (GPL) Version 2, available from the file
7*4882a593Smuzhiyun  * COPYING in the main directory of this source tree, or the
8*4882a593Smuzhiyun  * OpenIB.org BSD license below:
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  *     Redistribution and use in source and binary forms, with or
11*4882a593Smuzhiyun  *     without modification, are permitted provided that the following
12*4882a593Smuzhiyun  *     conditions are met:
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  *      - Redistributions of source code must retain the above
15*4882a593Smuzhiyun  *        copyright notice, this list of conditions and the following
16*4882a593Smuzhiyun  *        disclaimer.
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  *      - Redistributions in binary form must reproduce the above
19*4882a593Smuzhiyun  *        copyright notice, this list of conditions and the following
20*4882a593Smuzhiyun  *        disclaimer in the documentation and/or other materials
21*4882a593Smuzhiyun  *        provided with the distribution.
22*4882a593Smuzhiyun  *
23*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24*4882a593Smuzhiyun  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25*4882a593Smuzhiyun  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26*4882a593Smuzhiyun  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27*4882a593Smuzhiyun  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28*4882a593Smuzhiyun  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29*4882a593Smuzhiyun  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30*4882a593Smuzhiyun  * SOFTWARE.
31*4882a593Smuzhiyun  */
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #include <linux/errno.h>
34*4882a593Smuzhiyun #include <linux/pci.h>
35*4882a593Smuzhiyun #include <linux/delay.h>
36*4882a593Smuzhiyun #include <linux/slab.h>
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun #include "mthca_dev.h"
39*4882a593Smuzhiyun #include "mthca_cmd.h"
40*4882a593Smuzhiyun 
mthca_reset(struct mthca_dev * mdev)41*4882a593Smuzhiyun int mthca_reset(struct mthca_dev *mdev)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun 	int i;
44*4882a593Smuzhiyun 	int err = 0;
45*4882a593Smuzhiyun 	u32 *hca_header    = NULL;
46*4882a593Smuzhiyun 	u32 *bridge_header = NULL;
47*4882a593Smuzhiyun 	struct pci_dev *bridge = NULL;
48*4882a593Smuzhiyun 	int bridge_pcix_cap = 0;
49*4882a593Smuzhiyun 	int hca_pcie_cap = 0;
50*4882a593Smuzhiyun 	int hca_pcix_cap = 0;
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun 	u16 devctl;
53*4882a593Smuzhiyun 	u16 linkctl;
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun #define MTHCA_RESET_OFFSET 0xf0010
56*4882a593Smuzhiyun #define MTHCA_RESET_VALUE  swab32(1)
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	/*
59*4882a593Smuzhiyun 	 * Reset the chip.  This is somewhat ugly because we have to
60*4882a593Smuzhiyun 	 * save off the PCI header before reset and then restore it
61*4882a593Smuzhiyun 	 * after the chip reboots.  We skip config space offsets 22
62*4882a593Smuzhiyun 	 * and 23 since those have a special meaning.
63*4882a593Smuzhiyun 	 *
64*4882a593Smuzhiyun 	 * To make matters worse, for Tavor (PCI-X HCA) we have to
65*4882a593Smuzhiyun 	 * find the associated bridge device and save off its PCI
66*4882a593Smuzhiyun 	 * header as well.
67*4882a593Smuzhiyun 	 */
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	if (!(mdev->mthca_flags & MTHCA_FLAG_PCIE)) {
70*4882a593Smuzhiyun 		/* Look for the bridge -- its device ID will be 2 more
71*4882a593Smuzhiyun 		   than HCA's device ID. */
72*4882a593Smuzhiyun 		while ((bridge = pci_get_device(mdev->pdev->vendor,
73*4882a593Smuzhiyun 						mdev->pdev->device + 2,
74*4882a593Smuzhiyun 						bridge)) != NULL) {
75*4882a593Smuzhiyun 			if (bridge->hdr_type    == PCI_HEADER_TYPE_BRIDGE &&
76*4882a593Smuzhiyun 			    bridge->subordinate == mdev->pdev->bus) {
77*4882a593Smuzhiyun 				mthca_dbg(mdev, "Found bridge: %s\n",
78*4882a593Smuzhiyun 					  pci_name(bridge));
79*4882a593Smuzhiyun 				break;
80*4882a593Smuzhiyun 			}
81*4882a593Smuzhiyun 		}
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 		if (!bridge) {
84*4882a593Smuzhiyun 			/*
85*4882a593Smuzhiyun 			 * Didn't find a bridge for a Tavor device --
86*4882a593Smuzhiyun 			 * assume we're in no-bridge mode and hope for
87*4882a593Smuzhiyun 			 * the best.
88*4882a593Smuzhiyun 			 */
89*4882a593Smuzhiyun 			mthca_warn(mdev, "No bridge found for %s\n",
90*4882a593Smuzhiyun 				  pci_name(mdev->pdev));
91*4882a593Smuzhiyun 		}
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun 	}
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	/* For Arbel do we need to save off the full 4K PCI Express header?? */
96*4882a593Smuzhiyun 	hca_header = kmalloc(256, GFP_KERNEL);
97*4882a593Smuzhiyun 	if (!hca_header) {
98*4882a593Smuzhiyun 		err = -ENOMEM;
99*4882a593Smuzhiyun 		goto put_dev;
100*4882a593Smuzhiyun 	}
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 	for (i = 0; i < 64; ++i) {
103*4882a593Smuzhiyun 		if (i == 22 || i == 23)
104*4882a593Smuzhiyun 			continue;
105*4882a593Smuzhiyun 		if (pci_read_config_dword(mdev->pdev, i * 4, hca_header + i)) {
106*4882a593Smuzhiyun 			err = -ENODEV;
107*4882a593Smuzhiyun 			mthca_err(mdev, "Couldn't save HCA "
108*4882a593Smuzhiyun 				  "PCI header, aborting.\n");
109*4882a593Smuzhiyun 			goto free_hca;
110*4882a593Smuzhiyun 		}
111*4882a593Smuzhiyun 	}
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	hca_pcix_cap = pci_find_capability(mdev->pdev, PCI_CAP_ID_PCIX);
114*4882a593Smuzhiyun 	hca_pcie_cap = pci_pcie_cap(mdev->pdev);
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	if (bridge) {
117*4882a593Smuzhiyun 		bridge_header = kmalloc(256, GFP_KERNEL);
118*4882a593Smuzhiyun 		if (!bridge_header) {
119*4882a593Smuzhiyun 			err = -ENOMEM;
120*4882a593Smuzhiyun 			goto free_hca;
121*4882a593Smuzhiyun 		}
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 		for (i = 0; i < 64; ++i) {
124*4882a593Smuzhiyun 			if (i == 22 || i == 23)
125*4882a593Smuzhiyun 				continue;
126*4882a593Smuzhiyun 			if (pci_read_config_dword(bridge, i * 4, bridge_header + i)) {
127*4882a593Smuzhiyun 				err = -ENODEV;
128*4882a593Smuzhiyun 				mthca_err(mdev, "Couldn't save HCA bridge "
129*4882a593Smuzhiyun 					  "PCI header, aborting.\n");
130*4882a593Smuzhiyun 				goto free_bh;
131*4882a593Smuzhiyun 			}
132*4882a593Smuzhiyun 		}
133*4882a593Smuzhiyun 		bridge_pcix_cap = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
134*4882a593Smuzhiyun 		if (!bridge_pcix_cap) {
135*4882a593Smuzhiyun 				err = -ENODEV;
136*4882a593Smuzhiyun 				mthca_err(mdev, "Couldn't locate HCA bridge "
137*4882a593Smuzhiyun 					  "PCI-X capability, aborting.\n");
138*4882a593Smuzhiyun 				goto free_bh;
139*4882a593Smuzhiyun 		}
140*4882a593Smuzhiyun 	}
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	/* actually hit reset */
143*4882a593Smuzhiyun 	{
144*4882a593Smuzhiyun 		void __iomem *reset = ioremap(pci_resource_start(mdev->pdev, 0) +
145*4882a593Smuzhiyun 					      MTHCA_RESET_OFFSET, 4);
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 		if (!reset) {
148*4882a593Smuzhiyun 			err = -ENOMEM;
149*4882a593Smuzhiyun 			mthca_err(mdev, "Couldn't map HCA reset register, "
150*4882a593Smuzhiyun 				  "aborting.\n");
151*4882a593Smuzhiyun 			goto free_bh;
152*4882a593Smuzhiyun 		}
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 		writel(MTHCA_RESET_VALUE, reset);
155*4882a593Smuzhiyun 		iounmap(reset);
156*4882a593Smuzhiyun 	}
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	/* Docs say to wait one second before accessing device */
159*4882a593Smuzhiyun 	msleep(1000);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	/* Now wait for PCI device to start responding again */
162*4882a593Smuzhiyun 	{
163*4882a593Smuzhiyun 		u32 v;
164*4882a593Smuzhiyun 		int c = 0;
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 		for (c = 0; c < 100; ++c) {
167*4882a593Smuzhiyun 			if (pci_read_config_dword(bridge ? bridge : mdev->pdev, 0, &v)) {
168*4882a593Smuzhiyun 				err = -ENODEV;
169*4882a593Smuzhiyun 				mthca_err(mdev, "Couldn't access HCA after reset, "
170*4882a593Smuzhiyun 					  "aborting.\n");
171*4882a593Smuzhiyun 				goto free_bh;
172*4882a593Smuzhiyun 			}
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 			if (v != 0xffffffff)
175*4882a593Smuzhiyun 				goto good;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 			msleep(100);
178*4882a593Smuzhiyun 		}
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 		err = -ENODEV;
181*4882a593Smuzhiyun 		mthca_err(mdev, "PCI device did not come back after reset, "
182*4882a593Smuzhiyun 			  "aborting.\n");
183*4882a593Smuzhiyun 		goto free_bh;
184*4882a593Smuzhiyun 	}
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun good:
187*4882a593Smuzhiyun 	/* Now restore the PCI headers */
188*4882a593Smuzhiyun 	if (bridge) {
189*4882a593Smuzhiyun 		if (pci_write_config_dword(bridge, bridge_pcix_cap + 0x8,
190*4882a593Smuzhiyun 				 bridge_header[(bridge_pcix_cap + 0x8) / 4])) {
191*4882a593Smuzhiyun 			err = -ENODEV;
192*4882a593Smuzhiyun 			mthca_err(mdev, "Couldn't restore HCA bridge Upstream "
193*4882a593Smuzhiyun 				  "split transaction control, aborting.\n");
194*4882a593Smuzhiyun 			goto free_bh;
195*4882a593Smuzhiyun 		}
196*4882a593Smuzhiyun 		if (pci_write_config_dword(bridge, bridge_pcix_cap + 0xc,
197*4882a593Smuzhiyun 				 bridge_header[(bridge_pcix_cap + 0xc) / 4])) {
198*4882a593Smuzhiyun 			err = -ENODEV;
199*4882a593Smuzhiyun 			mthca_err(mdev, "Couldn't restore HCA bridge Downstream "
200*4882a593Smuzhiyun 				  "split transaction control, aborting.\n");
201*4882a593Smuzhiyun 			goto free_bh;
202*4882a593Smuzhiyun 		}
203*4882a593Smuzhiyun 		/*
204*4882a593Smuzhiyun 		 * Bridge control register is at 0x3e, so we'll
205*4882a593Smuzhiyun 		 * naturally restore it last in this loop.
206*4882a593Smuzhiyun 		 */
207*4882a593Smuzhiyun 		for (i = 0; i < 16; ++i) {
208*4882a593Smuzhiyun 			if (i * 4 == PCI_COMMAND)
209*4882a593Smuzhiyun 				continue;
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun 			if (pci_write_config_dword(bridge, i * 4, bridge_header[i])) {
212*4882a593Smuzhiyun 				err = -ENODEV;
213*4882a593Smuzhiyun 				mthca_err(mdev, "Couldn't restore HCA bridge reg %x, "
214*4882a593Smuzhiyun 					  "aborting.\n", i);
215*4882a593Smuzhiyun 				goto free_bh;
216*4882a593Smuzhiyun 			}
217*4882a593Smuzhiyun 		}
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 		if (pci_write_config_dword(bridge, PCI_COMMAND,
220*4882a593Smuzhiyun 					   bridge_header[PCI_COMMAND / 4])) {
221*4882a593Smuzhiyun 			err = -ENODEV;
222*4882a593Smuzhiyun 			mthca_err(mdev, "Couldn't restore HCA bridge COMMAND, "
223*4882a593Smuzhiyun 				  "aborting.\n");
224*4882a593Smuzhiyun 			goto free_bh;
225*4882a593Smuzhiyun 		}
226*4882a593Smuzhiyun 	}
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 	if (hca_pcix_cap) {
229*4882a593Smuzhiyun 		if (pci_write_config_dword(mdev->pdev, hca_pcix_cap,
230*4882a593Smuzhiyun 				 hca_header[hca_pcix_cap / 4])) {
231*4882a593Smuzhiyun 			err = -ENODEV;
232*4882a593Smuzhiyun 			mthca_err(mdev, "Couldn't restore HCA PCI-X "
233*4882a593Smuzhiyun 				  "command register, aborting.\n");
234*4882a593Smuzhiyun 			goto free_bh;
235*4882a593Smuzhiyun 		}
236*4882a593Smuzhiyun 	}
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun 	if (hca_pcie_cap) {
239*4882a593Smuzhiyun 		devctl = hca_header[(hca_pcie_cap + PCI_EXP_DEVCTL) / 4];
240*4882a593Smuzhiyun 		if (pcie_capability_write_word(mdev->pdev, PCI_EXP_DEVCTL,
241*4882a593Smuzhiyun 					       devctl)) {
242*4882a593Smuzhiyun 			err = -ENODEV;
243*4882a593Smuzhiyun 			mthca_err(mdev, "Couldn't restore HCA PCI Express "
244*4882a593Smuzhiyun 				  "Device Control register, aborting.\n");
245*4882a593Smuzhiyun 			goto free_bh;
246*4882a593Smuzhiyun 		}
247*4882a593Smuzhiyun 		linkctl = hca_header[(hca_pcie_cap + PCI_EXP_LNKCTL) / 4];
248*4882a593Smuzhiyun 		if (pcie_capability_write_word(mdev->pdev, PCI_EXP_LNKCTL,
249*4882a593Smuzhiyun 					       linkctl)) {
250*4882a593Smuzhiyun 			err = -ENODEV;
251*4882a593Smuzhiyun 			mthca_err(mdev, "Couldn't restore HCA PCI Express "
252*4882a593Smuzhiyun 				  "Link control register, aborting.\n");
253*4882a593Smuzhiyun 			goto free_bh;
254*4882a593Smuzhiyun 		}
255*4882a593Smuzhiyun 	}
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	for (i = 0; i < 16; ++i) {
258*4882a593Smuzhiyun 		if (i * 4 == PCI_COMMAND)
259*4882a593Smuzhiyun 			continue;
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 		if (pci_write_config_dword(mdev->pdev, i * 4, hca_header[i])) {
262*4882a593Smuzhiyun 			err = -ENODEV;
263*4882a593Smuzhiyun 			mthca_err(mdev, "Couldn't restore HCA reg %x, "
264*4882a593Smuzhiyun 				  "aborting.\n", i);
265*4882a593Smuzhiyun 			goto free_bh;
266*4882a593Smuzhiyun 		}
267*4882a593Smuzhiyun 	}
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	if (pci_write_config_dword(mdev->pdev, PCI_COMMAND,
270*4882a593Smuzhiyun 				   hca_header[PCI_COMMAND / 4])) {
271*4882a593Smuzhiyun 		err = -ENODEV;
272*4882a593Smuzhiyun 		mthca_err(mdev, "Couldn't restore HCA COMMAND, "
273*4882a593Smuzhiyun 			  "aborting.\n");
274*4882a593Smuzhiyun 	}
275*4882a593Smuzhiyun free_bh:
276*4882a593Smuzhiyun 	kfree(bridge_header);
277*4882a593Smuzhiyun free_hca:
278*4882a593Smuzhiyun 	kfree(hca_header);
279*4882a593Smuzhiyun put_dev:
280*4882a593Smuzhiyun 	pci_dev_put(bridge);
281*4882a593Smuzhiyun 	return err;
282*4882a593Smuzhiyun }
283