1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3*4882a593Smuzhiyun * Copyright (c) 2005 Cisco Systems. All rights reserved.
4*4882a593Smuzhiyun * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This software is available to you under a choice of one of two
7*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
8*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
9*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
10*4882a593Smuzhiyun * OpenIB.org BSD license below:
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
13*4882a593Smuzhiyun * without modification, are permitted provided that the following
14*4882a593Smuzhiyun * conditions are met:
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * - Redistributions of source code must retain the above
17*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
18*4882a593Smuzhiyun * disclaimer.
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
21*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
22*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
23*4882a593Smuzhiyun * provided with the distribution.
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32*4882a593Smuzhiyun * SOFTWARE.
33*4882a593Smuzhiyun */
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #include <linux/mm.h>
36*4882a593Smuzhiyun #include <linux/scatterlist.h>
37*4882a593Smuzhiyun #include <linux/sched.h>
38*4882a593Smuzhiyun #include <linux/slab.h>
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #include <asm/page.h>
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun #include "mthca_memfree.h"
43*4882a593Smuzhiyun #include "mthca_dev.h"
44*4882a593Smuzhiyun #include "mthca_cmd.h"
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /*
47*4882a593Smuzhiyun * We allocate in as big chunks as we can, up to a maximum of 256 KB
48*4882a593Smuzhiyun * per chunk.
49*4882a593Smuzhiyun */
50*4882a593Smuzhiyun enum {
51*4882a593Smuzhiyun MTHCA_ICM_ALLOC_SIZE = 1 << 18,
52*4882a593Smuzhiyun MTHCA_TABLE_CHUNK_SIZE = 1 << 18
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun struct mthca_user_db_table {
56*4882a593Smuzhiyun struct mutex mutex;
57*4882a593Smuzhiyun struct {
58*4882a593Smuzhiyun u64 uvirt;
59*4882a593Smuzhiyun struct scatterlist mem;
60*4882a593Smuzhiyun int refcount;
61*4882a593Smuzhiyun } page[];
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
mthca_free_icm_pages(struct mthca_dev * dev,struct mthca_icm_chunk * chunk)64*4882a593Smuzhiyun static void mthca_free_icm_pages(struct mthca_dev *dev, struct mthca_icm_chunk *chunk)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun int i;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun if (chunk->nsg > 0)
69*4882a593Smuzhiyun pci_unmap_sg(dev->pdev, chunk->mem, chunk->npages,
70*4882a593Smuzhiyun PCI_DMA_BIDIRECTIONAL);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun for (i = 0; i < chunk->npages; ++i)
73*4882a593Smuzhiyun __free_pages(sg_page(&chunk->mem[i]),
74*4882a593Smuzhiyun get_order(chunk->mem[i].length));
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
mthca_free_icm_coherent(struct mthca_dev * dev,struct mthca_icm_chunk * chunk)77*4882a593Smuzhiyun static void mthca_free_icm_coherent(struct mthca_dev *dev, struct mthca_icm_chunk *chunk)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun int i;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun for (i = 0; i < chunk->npages; ++i) {
82*4882a593Smuzhiyun dma_free_coherent(&dev->pdev->dev, chunk->mem[i].length,
83*4882a593Smuzhiyun lowmem_page_address(sg_page(&chunk->mem[i])),
84*4882a593Smuzhiyun sg_dma_address(&chunk->mem[i]));
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
mthca_free_icm(struct mthca_dev * dev,struct mthca_icm * icm,int coherent)88*4882a593Smuzhiyun void mthca_free_icm(struct mthca_dev *dev, struct mthca_icm *icm, int coherent)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun struct mthca_icm_chunk *chunk, *tmp;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun if (!icm)
93*4882a593Smuzhiyun return;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun list_for_each_entry_safe(chunk, tmp, &icm->chunk_list, list) {
96*4882a593Smuzhiyun if (coherent)
97*4882a593Smuzhiyun mthca_free_icm_coherent(dev, chunk);
98*4882a593Smuzhiyun else
99*4882a593Smuzhiyun mthca_free_icm_pages(dev, chunk);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun kfree(chunk);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun kfree(icm);
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
mthca_alloc_icm_pages(struct scatterlist * mem,int order,gfp_t gfp_mask)107*4882a593Smuzhiyun static int mthca_alloc_icm_pages(struct scatterlist *mem, int order, gfp_t gfp_mask)
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun struct page *page;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /*
112*4882a593Smuzhiyun * Use __GFP_ZERO because buggy firmware assumes ICM pages are
113*4882a593Smuzhiyun * cleared, and subtle failures are seen if they aren't.
114*4882a593Smuzhiyun */
115*4882a593Smuzhiyun page = alloc_pages(gfp_mask | __GFP_ZERO, order);
116*4882a593Smuzhiyun if (!page)
117*4882a593Smuzhiyun return -ENOMEM;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun sg_set_page(mem, page, PAGE_SIZE << order, 0);
120*4882a593Smuzhiyun return 0;
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
mthca_alloc_icm_coherent(struct device * dev,struct scatterlist * mem,int order,gfp_t gfp_mask)123*4882a593Smuzhiyun static int mthca_alloc_icm_coherent(struct device *dev, struct scatterlist *mem,
124*4882a593Smuzhiyun int order, gfp_t gfp_mask)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun void *buf = dma_alloc_coherent(dev, PAGE_SIZE << order, &sg_dma_address(mem),
127*4882a593Smuzhiyun gfp_mask);
128*4882a593Smuzhiyun if (!buf)
129*4882a593Smuzhiyun return -ENOMEM;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun sg_set_buf(mem, buf, PAGE_SIZE << order);
132*4882a593Smuzhiyun BUG_ON(mem->offset);
133*4882a593Smuzhiyun sg_dma_len(mem) = PAGE_SIZE << order;
134*4882a593Smuzhiyun return 0;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
mthca_alloc_icm(struct mthca_dev * dev,int npages,gfp_t gfp_mask,int coherent)137*4882a593Smuzhiyun struct mthca_icm *mthca_alloc_icm(struct mthca_dev *dev, int npages,
138*4882a593Smuzhiyun gfp_t gfp_mask, int coherent)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun struct mthca_icm *icm;
141*4882a593Smuzhiyun struct mthca_icm_chunk *chunk = NULL;
142*4882a593Smuzhiyun int cur_order;
143*4882a593Smuzhiyun int ret;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun /* We use sg_set_buf for coherent allocs, which assumes low memory */
146*4882a593Smuzhiyun BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM));
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun icm = kmalloc(sizeof *icm, gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
149*4882a593Smuzhiyun if (!icm)
150*4882a593Smuzhiyun return icm;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun icm->refcount = 0;
153*4882a593Smuzhiyun INIT_LIST_HEAD(&icm->chunk_list);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun cur_order = get_order(MTHCA_ICM_ALLOC_SIZE);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun while (npages > 0) {
158*4882a593Smuzhiyun if (!chunk) {
159*4882a593Smuzhiyun chunk = kmalloc(sizeof *chunk,
160*4882a593Smuzhiyun gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN));
161*4882a593Smuzhiyun if (!chunk)
162*4882a593Smuzhiyun goto fail;
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun sg_init_table(chunk->mem, MTHCA_ICM_CHUNK_LEN);
165*4882a593Smuzhiyun chunk->npages = 0;
166*4882a593Smuzhiyun chunk->nsg = 0;
167*4882a593Smuzhiyun list_add_tail(&chunk->list, &icm->chunk_list);
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun while (1 << cur_order > npages)
171*4882a593Smuzhiyun --cur_order;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun if (coherent)
174*4882a593Smuzhiyun ret = mthca_alloc_icm_coherent(&dev->pdev->dev,
175*4882a593Smuzhiyun &chunk->mem[chunk->npages],
176*4882a593Smuzhiyun cur_order, gfp_mask);
177*4882a593Smuzhiyun else
178*4882a593Smuzhiyun ret = mthca_alloc_icm_pages(&chunk->mem[chunk->npages],
179*4882a593Smuzhiyun cur_order, gfp_mask);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun if (!ret) {
182*4882a593Smuzhiyun ++chunk->npages;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun if (coherent)
185*4882a593Smuzhiyun ++chunk->nsg;
186*4882a593Smuzhiyun else if (chunk->npages == MTHCA_ICM_CHUNK_LEN) {
187*4882a593Smuzhiyun chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
188*4882a593Smuzhiyun chunk->npages,
189*4882a593Smuzhiyun PCI_DMA_BIDIRECTIONAL);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun if (chunk->nsg <= 0)
192*4882a593Smuzhiyun goto fail;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun if (chunk->npages == MTHCA_ICM_CHUNK_LEN)
196*4882a593Smuzhiyun chunk = NULL;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun npages -= 1 << cur_order;
199*4882a593Smuzhiyun } else {
200*4882a593Smuzhiyun --cur_order;
201*4882a593Smuzhiyun if (cur_order < 0)
202*4882a593Smuzhiyun goto fail;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun if (!coherent && chunk) {
207*4882a593Smuzhiyun chunk->nsg = pci_map_sg(dev->pdev, chunk->mem,
208*4882a593Smuzhiyun chunk->npages,
209*4882a593Smuzhiyun PCI_DMA_BIDIRECTIONAL);
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun if (chunk->nsg <= 0)
212*4882a593Smuzhiyun goto fail;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun return icm;
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun fail:
218*4882a593Smuzhiyun mthca_free_icm(dev, icm, coherent);
219*4882a593Smuzhiyun return NULL;
220*4882a593Smuzhiyun }
221*4882a593Smuzhiyun
mthca_table_get(struct mthca_dev * dev,struct mthca_icm_table * table,int obj)222*4882a593Smuzhiyun int mthca_table_get(struct mthca_dev *dev, struct mthca_icm_table *table, int obj)
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun int i = (obj & (table->num_obj - 1)) * table->obj_size / MTHCA_TABLE_CHUNK_SIZE;
225*4882a593Smuzhiyun int ret = 0;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun mutex_lock(&table->mutex);
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun if (table->icm[i]) {
230*4882a593Smuzhiyun ++table->icm[i]->refcount;
231*4882a593Smuzhiyun goto out;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun table->icm[i] = mthca_alloc_icm(dev, MTHCA_TABLE_CHUNK_SIZE >> PAGE_SHIFT,
235*4882a593Smuzhiyun (table->lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
236*4882a593Smuzhiyun __GFP_NOWARN, table->coherent);
237*4882a593Smuzhiyun if (!table->icm[i]) {
238*4882a593Smuzhiyun ret = -ENOMEM;
239*4882a593Smuzhiyun goto out;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun if (mthca_MAP_ICM(dev, table->icm[i],
243*4882a593Smuzhiyun table->virt + i * MTHCA_TABLE_CHUNK_SIZE)) {
244*4882a593Smuzhiyun mthca_free_icm(dev, table->icm[i], table->coherent);
245*4882a593Smuzhiyun table->icm[i] = NULL;
246*4882a593Smuzhiyun ret = -ENOMEM;
247*4882a593Smuzhiyun goto out;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun ++table->icm[i]->refcount;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun out:
253*4882a593Smuzhiyun mutex_unlock(&table->mutex);
254*4882a593Smuzhiyun return ret;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
mthca_table_put(struct mthca_dev * dev,struct mthca_icm_table * table,int obj)257*4882a593Smuzhiyun void mthca_table_put(struct mthca_dev *dev, struct mthca_icm_table *table, int obj)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun int i;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun if (!mthca_is_memfree(dev))
262*4882a593Smuzhiyun return;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun i = (obj & (table->num_obj - 1)) * table->obj_size / MTHCA_TABLE_CHUNK_SIZE;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun mutex_lock(&table->mutex);
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun if (--table->icm[i]->refcount == 0) {
269*4882a593Smuzhiyun mthca_UNMAP_ICM(dev, table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
270*4882a593Smuzhiyun MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE);
271*4882a593Smuzhiyun mthca_free_icm(dev, table->icm[i], table->coherent);
272*4882a593Smuzhiyun table->icm[i] = NULL;
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun mutex_unlock(&table->mutex);
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun
mthca_table_find(struct mthca_icm_table * table,int obj,dma_addr_t * dma_handle)278*4882a593Smuzhiyun void *mthca_table_find(struct mthca_icm_table *table, int obj, dma_addr_t *dma_handle)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun int idx, offset, dma_offset, i;
281*4882a593Smuzhiyun struct mthca_icm_chunk *chunk;
282*4882a593Smuzhiyun struct mthca_icm *icm;
283*4882a593Smuzhiyun struct page *page = NULL;
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun if (!table->lowmem)
286*4882a593Smuzhiyun return NULL;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun mutex_lock(&table->mutex);
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun idx = (obj & (table->num_obj - 1)) * table->obj_size;
291*4882a593Smuzhiyun icm = table->icm[idx / MTHCA_TABLE_CHUNK_SIZE];
292*4882a593Smuzhiyun dma_offset = offset = idx % MTHCA_TABLE_CHUNK_SIZE;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun if (!icm)
295*4882a593Smuzhiyun goto out;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun list_for_each_entry(chunk, &icm->chunk_list, list) {
298*4882a593Smuzhiyun for (i = 0; i < chunk->npages; ++i) {
299*4882a593Smuzhiyun if (dma_handle && dma_offset >= 0) {
300*4882a593Smuzhiyun if (sg_dma_len(&chunk->mem[i]) > dma_offset)
301*4882a593Smuzhiyun *dma_handle = sg_dma_address(&chunk->mem[i]) +
302*4882a593Smuzhiyun dma_offset;
303*4882a593Smuzhiyun dma_offset -= sg_dma_len(&chunk->mem[i]);
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun /* DMA mapping can merge pages but not split them,
306*4882a593Smuzhiyun * so if we found the page, dma_handle has already
307*4882a593Smuzhiyun * been assigned to. */
308*4882a593Smuzhiyun if (chunk->mem[i].length > offset) {
309*4882a593Smuzhiyun page = sg_page(&chunk->mem[i]);
310*4882a593Smuzhiyun goto out;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun offset -= chunk->mem[i].length;
313*4882a593Smuzhiyun }
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun out:
317*4882a593Smuzhiyun mutex_unlock(&table->mutex);
318*4882a593Smuzhiyun return page ? lowmem_page_address(page) + offset : NULL;
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun
mthca_table_get_range(struct mthca_dev * dev,struct mthca_icm_table * table,int start,int end)321*4882a593Smuzhiyun int mthca_table_get_range(struct mthca_dev *dev, struct mthca_icm_table *table,
322*4882a593Smuzhiyun int start, int end)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun int inc = MTHCA_TABLE_CHUNK_SIZE / table->obj_size;
325*4882a593Smuzhiyun int i, err;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun for (i = start; i <= end; i += inc) {
328*4882a593Smuzhiyun err = mthca_table_get(dev, table, i);
329*4882a593Smuzhiyun if (err)
330*4882a593Smuzhiyun goto fail;
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun return 0;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun fail:
336*4882a593Smuzhiyun while (i > start) {
337*4882a593Smuzhiyun i -= inc;
338*4882a593Smuzhiyun mthca_table_put(dev, table, i);
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun return err;
342*4882a593Smuzhiyun }
343*4882a593Smuzhiyun
mthca_table_put_range(struct mthca_dev * dev,struct mthca_icm_table * table,int start,int end)344*4882a593Smuzhiyun void mthca_table_put_range(struct mthca_dev *dev, struct mthca_icm_table *table,
345*4882a593Smuzhiyun int start, int end)
346*4882a593Smuzhiyun {
347*4882a593Smuzhiyun int i;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun if (!mthca_is_memfree(dev))
350*4882a593Smuzhiyun return;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun for (i = start; i <= end; i += MTHCA_TABLE_CHUNK_SIZE / table->obj_size)
353*4882a593Smuzhiyun mthca_table_put(dev, table, i);
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun
mthca_alloc_icm_table(struct mthca_dev * dev,u64 virt,int obj_size,int nobj,int reserved,int use_lowmem,int use_coherent)356*4882a593Smuzhiyun struct mthca_icm_table *mthca_alloc_icm_table(struct mthca_dev *dev,
357*4882a593Smuzhiyun u64 virt, int obj_size,
358*4882a593Smuzhiyun int nobj, int reserved,
359*4882a593Smuzhiyun int use_lowmem, int use_coherent)
360*4882a593Smuzhiyun {
361*4882a593Smuzhiyun struct mthca_icm_table *table;
362*4882a593Smuzhiyun int obj_per_chunk;
363*4882a593Smuzhiyun int num_icm;
364*4882a593Smuzhiyun unsigned chunk_size;
365*4882a593Smuzhiyun int i;
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun obj_per_chunk = MTHCA_TABLE_CHUNK_SIZE / obj_size;
368*4882a593Smuzhiyun num_icm = DIV_ROUND_UP(nobj, obj_per_chunk);
369*4882a593Smuzhiyun
370*4882a593Smuzhiyun table = kmalloc(struct_size(table, icm, num_icm), GFP_KERNEL);
371*4882a593Smuzhiyun if (!table)
372*4882a593Smuzhiyun return NULL;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun table->virt = virt;
375*4882a593Smuzhiyun table->num_icm = num_icm;
376*4882a593Smuzhiyun table->num_obj = nobj;
377*4882a593Smuzhiyun table->obj_size = obj_size;
378*4882a593Smuzhiyun table->lowmem = use_lowmem;
379*4882a593Smuzhiyun table->coherent = use_coherent;
380*4882a593Smuzhiyun mutex_init(&table->mutex);
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun for (i = 0; i < num_icm; ++i)
383*4882a593Smuzhiyun table->icm[i] = NULL;
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun for (i = 0; i * MTHCA_TABLE_CHUNK_SIZE < reserved * obj_size; ++i) {
386*4882a593Smuzhiyun chunk_size = MTHCA_TABLE_CHUNK_SIZE;
387*4882a593Smuzhiyun if ((i + 1) * MTHCA_TABLE_CHUNK_SIZE > nobj * obj_size)
388*4882a593Smuzhiyun chunk_size = nobj * obj_size - i * MTHCA_TABLE_CHUNK_SIZE;
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun table->icm[i] = mthca_alloc_icm(dev, chunk_size >> PAGE_SHIFT,
391*4882a593Smuzhiyun (use_lowmem ? GFP_KERNEL : GFP_HIGHUSER) |
392*4882a593Smuzhiyun __GFP_NOWARN, use_coherent);
393*4882a593Smuzhiyun if (!table->icm[i])
394*4882a593Smuzhiyun goto err;
395*4882a593Smuzhiyun if (mthca_MAP_ICM(dev, table->icm[i],
396*4882a593Smuzhiyun virt + i * MTHCA_TABLE_CHUNK_SIZE)) {
397*4882a593Smuzhiyun mthca_free_icm(dev, table->icm[i], table->coherent);
398*4882a593Smuzhiyun table->icm[i] = NULL;
399*4882a593Smuzhiyun goto err;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun /*
403*4882a593Smuzhiyun * Add a reference to this ICM chunk so that it never
404*4882a593Smuzhiyun * gets freed (since it contains reserved firmware objects).
405*4882a593Smuzhiyun */
406*4882a593Smuzhiyun ++table->icm[i]->refcount;
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun return table;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun err:
412*4882a593Smuzhiyun for (i = 0; i < num_icm; ++i)
413*4882a593Smuzhiyun if (table->icm[i]) {
414*4882a593Smuzhiyun mthca_UNMAP_ICM(dev, virt + i * MTHCA_TABLE_CHUNK_SIZE,
415*4882a593Smuzhiyun MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE);
416*4882a593Smuzhiyun mthca_free_icm(dev, table->icm[i], table->coherent);
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun kfree(table);
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun return NULL;
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun
mthca_free_icm_table(struct mthca_dev * dev,struct mthca_icm_table * table)424*4882a593Smuzhiyun void mthca_free_icm_table(struct mthca_dev *dev, struct mthca_icm_table *table)
425*4882a593Smuzhiyun {
426*4882a593Smuzhiyun int i;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun for (i = 0; i < table->num_icm; ++i)
429*4882a593Smuzhiyun if (table->icm[i]) {
430*4882a593Smuzhiyun mthca_UNMAP_ICM(dev,
431*4882a593Smuzhiyun table->virt + i * MTHCA_TABLE_CHUNK_SIZE,
432*4882a593Smuzhiyun MTHCA_TABLE_CHUNK_SIZE / MTHCA_ICM_PAGE_SIZE);
433*4882a593Smuzhiyun mthca_free_icm(dev, table->icm[i], table->coherent);
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun kfree(table);
437*4882a593Smuzhiyun }
438*4882a593Smuzhiyun
mthca_uarc_virt(struct mthca_dev * dev,struct mthca_uar * uar,int page)439*4882a593Smuzhiyun static u64 mthca_uarc_virt(struct mthca_dev *dev, struct mthca_uar *uar, int page)
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun return dev->uar_table.uarc_base +
442*4882a593Smuzhiyun uar->index * dev->uar_table.uarc_size +
443*4882a593Smuzhiyun page * MTHCA_ICM_PAGE_SIZE;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
mthca_map_user_db(struct mthca_dev * dev,struct mthca_uar * uar,struct mthca_user_db_table * db_tab,int index,u64 uaddr)446*4882a593Smuzhiyun int mthca_map_user_db(struct mthca_dev *dev, struct mthca_uar *uar,
447*4882a593Smuzhiyun struct mthca_user_db_table *db_tab, int index, u64 uaddr)
448*4882a593Smuzhiyun {
449*4882a593Smuzhiyun struct page *pages[1];
450*4882a593Smuzhiyun int ret = 0;
451*4882a593Smuzhiyun int i;
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun if (!mthca_is_memfree(dev))
454*4882a593Smuzhiyun return 0;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun if (index < 0 || index > dev->uar_table.uarc_size / 8)
457*4882a593Smuzhiyun return -EINVAL;
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun mutex_lock(&db_tab->mutex);
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun i = index / MTHCA_DB_REC_PER_PAGE;
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun if ((db_tab->page[i].refcount >= MTHCA_DB_REC_PER_PAGE) ||
464*4882a593Smuzhiyun (db_tab->page[i].uvirt && db_tab->page[i].uvirt != uaddr) ||
465*4882a593Smuzhiyun (uaddr & 4095)) {
466*4882a593Smuzhiyun ret = -EINVAL;
467*4882a593Smuzhiyun goto out;
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun if (db_tab->page[i].refcount) {
471*4882a593Smuzhiyun ++db_tab->page[i].refcount;
472*4882a593Smuzhiyun goto out;
473*4882a593Smuzhiyun }
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun ret = pin_user_pages_fast(uaddr & PAGE_MASK, 1,
476*4882a593Smuzhiyun FOLL_WRITE | FOLL_LONGTERM, pages);
477*4882a593Smuzhiyun if (ret < 0)
478*4882a593Smuzhiyun goto out;
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun sg_set_page(&db_tab->page[i].mem, pages[0], MTHCA_ICM_PAGE_SIZE,
481*4882a593Smuzhiyun uaddr & ~PAGE_MASK);
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun ret = pci_map_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
484*4882a593Smuzhiyun if (ret < 0) {
485*4882a593Smuzhiyun unpin_user_page(pages[0]);
486*4882a593Smuzhiyun goto out;
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun ret = mthca_MAP_ICM_page(dev, sg_dma_address(&db_tab->page[i].mem),
490*4882a593Smuzhiyun mthca_uarc_virt(dev, uar, i));
491*4882a593Smuzhiyun if (ret) {
492*4882a593Smuzhiyun pci_unmap_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
493*4882a593Smuzhiyun unpin_user_page(sg_page(&db_tab->page[i].mem));
494*4882a593Smuzhiyun goto out;
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun db_tab->page[i].uvirt = uaddr;
498*4882a593Smuzhiyun db_tab->page[i].refcount = 1;
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun out:
501*4882a593Smuzhiyun mutex_unlock(&db_tab->mutex);
502*4882a593Smuzhiyun return ret;
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun
mthca_unmap_user_db(struct mthca_dev * dev,struct mthca_uar * uar,struct mthca_user_db_table * db_tab,int index)505*4882a593Smuzhiyun void mthca_unmap_user_db(struct mthca_dev *dev, struct mthca_uar *uar,
506*4882a593Smuzhiyun struct mthca_user_db_table *db_tab, int index)
507*4882a593Smuzhiyun {
508*4882a593Smuzhiyun if (!mthca_is_memfree(dev))
509*4882a593Smuzhiyun return;
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun /*
512*4882a593Smuzhiyun * To make our bookkeeping simpler, we don't unmap DB
513*4882a593Smuzhiyun * pages until we clean up the whole db table.
514*4882a593Smuzhiyun */
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun mutex_lock(&db_tab->mutex);
517*4882a593Smuzhiyun
518*4882a593Smuzhiyun --db_tab->page[index / MTHCA_DB_REC_PER_PAGE].refcount;
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun mutex_unlock(&db_tab->mutex);
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun
mthca_init_user_db_tab(struct mthca_dev * dev)523*4882a593Smuzhiyun struct mthca_user_db_table *mthca_init_user_db_tab(struct mthca_dev *dev)
524*4882a593Smuzhiyun {
525*4882a593Smuzhiyun struct mthca_user_db_table *db_tab;
526*4882a593Smuzhiyun int npages;
527*4882a593Smuzhiyun int i;
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun if (!mthca_is_memfree(dev))
530*4882a593Smuzhiyun return NULL;
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun npages = dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE;
533*4882a593Smuzhiyun db_tab = kmalloc(struct_size(db_tab, page, npages), GFP_KERNEL);
534*4882a593Smuzhiyun if (!db_tab)
535*4882a593Smuzhiyun return ERR_PTR(-ENOMEM);
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun mutex_init(&db_tab->mutex);
538*4882a593Smuzhiyun for (i = 0; i < npages; ++i) {
539*4882a593Smuzhiyun db_tab->page[i].refcount = 0;
540*4882a593Smuzhiyun db_tab->page[i].uvirt = 0;
541*4882a593Smuzhiyun sg_init_table(&db_tab->page[i].mem, 1);
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun return db_tab;
545*4882a593Smuzhiyun }
546*4882a593Smuzhiyun
mthca_cleanup_user_db_tab(struct mthca_dev * dev,struct mthca_uar * uar,struct mthca_user_db_table * db_tab)547*4882a593Smuzhiyun void mthca_cleanup_user_db_tab(struct mthca_dev *dev, struct mthca_uar *uar,
548*4882a593Smuzhiyun struct mthca_user_db_table *db_tab)
549*4882a593Smuzhiyun {
550*4882a593Smuzhiyun int i;
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun if (!mthca_is_memfree(dev))
553*4882a593Smuzhiyun return;
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun for (i = 0; i < dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE; ++i) {
556*4882a593Smuzhiyun if (db_tab->page[i].uvirt) {
557*4882a593Smuzhiyun mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, uar, i), 1);
558*4882a593Smuzhiyun pci_unmap_sg(dev->pdev, &db_tab->page[i].mem, 1, PCI_DMA_TODEVICE);
559*4882a593Smuzhiyun unpin_user_page(sg_page(&db_tab->page[i].mem));
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun kfree(db_tab);
564*4882a593Smuzhiyun }
565*4882a593Smuzhiyun
mthca_alloc_db(struct mthca_dev * dev,enum mthca_db_type type,u32 qn,__be32 ** db)566*4882a593Smuzhiyun int mthca_alloc_db(struct mthca_dev *dev, enum mthca_db_type type,
567*4882a593Smuzhiyun u32 qn, __be32 **db)
568*4882a593Smuzhiyun {
569*4882a593Smuzhiyun int group;
570*4882a593Smuzhiyun int start, end, dir;
571*4882a593Smuzhiyun int i, j;
572*4882a593Smuzhiyun struct mthca_db_page *page;
573*4882a593Smuzhiyun int ret = 0;
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun mutex_lock(&dev->db_tab->mutex);
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun switch (type) {
578*4882a593Smuzhiyun case MTHCA_DB_TYPE_CQ_ARM:
579*4882a593Smuzhiyun case MTHCA_DB_TYPE_SQ:
580*4882a593Smuzhiyun group = 0;
581*4882a593Smuzhiyun start = 0;
582*4882a593Smuzhiyun end = dev->db_tab->max_group1;
583*4882a593Smuzhiyun dir = 1;
584*4882a593Smuzhiyun break;
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun case MTHCA_DB_TYPE_CQ_SET_CI:
587*4882a593Smuzhiyun case MTHCA_DB_TYPE_RQ:
588*4882a593Smuzhiyun case MTHCA_DB_TYPE_SRQ:
589*4882a593Smuzhiyun group = 1;
590*4882a593Smuzhiyun start = dev->db_tab->npages - 1;
591*4882a593Smuzhiyun end = dev->db_tab->min_group2;
592*4882a593Smuzhiyun dir = -1;
593*4882a593Smuzhiyun break;
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun default:
596*4882a593Smuzhiyun ret = -EINVAL;
597*4882a593Smuzhiyun goto out;
598*4882a593Smuzhiyun }
599*4882a593Smuzhiyun
600*4882a593Smuzhiyun for (i = start; i != end; i += dir)
601*4882a593Smuzhiyun if (dev->db_tab->page[i].db_rec &&
602*4882a593Smuzhiyun !bitmap_full(dev->db_tab->page[i].used,
603*4882a593Smuzhiyun MTHCA_DB_REC_PER_PAGE)) {
604*4882a593Smuzhiyun page = dev->db_tab->page + i;
605*4882a593Smuzhiyun goto found;
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun for (i = start; i != end; i += dir)
609*4882a593Smuzhiyun if (!dev->db_tab->page[i].db_rec) {
610*4882a593Smuzhiyun page = dev->db_tab->page + i;
611*4882a593Smuzhiyun goto alloc;
612*4882a593Smuzhiyun }
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun if (dev->db_tab->max_group1 >= dev->db_tab->min_group2 - 1) {
615*4882a593Smuzhiyun ret = -ENOMEM;
616*4882a593Smuzhiyun goto out;
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun if (group == 0)
620*4882a593Smuzhiyun ++dev->db_tab->max_group1;
621*4882a593Smuzhiyun else
622*4882a593Smuzhiyun --dev->db_tab->min_group2;
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun page = dev->db_tab->page + end;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun alloc:
627*4882a593Smuzhiyun page->db_rec = dma_alloc_coherent(&dev->pdev->dev,
628*4882a593Smuzhiyun MTHCA_ICM_PAGE_SIZE, &page->mapping,
629*4882a593Smuzhiyun GFP_KERNEL);
630*4882a593Smuzhiyun if (!page->db_rec) {
631*4882a593Smuzhiyun ret = -ENOMEM;
632*4882a593Smuzhiyun goto out;
633*4882a593Smuzhiyun }
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun ret = mthca_MAP_ICM_page(dev, page->mapping,
636*4882a593Smuzhiyun mthca_uarc_virt(dev, &dev->driver_uar, i));
637*4882a593Smuzhiyun if (ret) {
638*4882a593Smuzhiyun dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
639*4882a593Smuzhiyun page->db_rec, page->mapping);
640*4882a593Smuzhiyun goto out;
641*4882a593Smuzhiyun }
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun bitmap_zero(page->used, MTHCA_DB_REC_PER_PAGE);
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun found:
646*4882a593Smuzhiyun j = find_first_zero_bit(page->used, MTHCA_DB_REC_PER_PAGE);
647*4882a593Smuzhiyun set_bit(j, page->used);
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun if (group == 1)
650*4882a593Smuzhiyun j = MTHCA_DB_REC_PER_PAGE - 1 - j;
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun ret = i * MTHCA_DB_REC_PER_PAGE + j;
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun page->db_rec[j] = cpu_to_be64((qn << 8) | (type << 5));
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun *db = (__be32 *) &page->db_rec[j];
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun out:
659*4882a593Smuzhiyun mutex_unlock(&dev->db_tab->mutex);
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun return ret;
662*4882a593Smuzhiyun }
663*4882a593Smuzhiyun
mthca_free_db(struct mthca_dev * dev,int type,int db_index)664*4882a593Smuzhiyun void mthca_free_db(struct mthca_dev *dev, int type, int db_index)
665*4882a593Smuzhiyun {
666*4882a593Smuzhiyun int i, j;
667*4882a593Smuzhiyun struct mthca_db_page *page;
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun i = db_index / MTHCA_DB_REC_PER_PAGE;
670*4882a593Smuzhiyun j = db_index % MTHCA_DB_REC_PER_PAGE;
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun page = dev->db_tab->page + i;
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun mutex_lock(&dev->db_tab->mutex);
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun page->db_rec[j] = 0;
677*4882a593Smuzhiyun if (i >= dev->db_tab->min_group2)
678*4882a593Smuzhiyun j = MTHCA_DB_REC_PER_PAGE - 1 - j;
679*4882a593Smuzhiyun clear_bit(j, page->used);
680*4882a593Smuzhiyun
681*4882a593Smuzhiyun if (bitmap_empty(page->used, MTHCA_DB_REC_PER_PAGE) &&
682*4882a593Smuzhiyun i >= dev->db_tab->max_group1 - 1) {
683*4882a593Smuzhiyun mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, &dev->driver_uar, i), 1);
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
686*4882a593Smuzhiyun page->db_rec, page->mapping);
687*4882a593Smuzhiyun page->db_rec = NULL;
688*4882a593Smuzhiyun
689*4882a593Smuzhiyun if (i == dev->db_tab->max_group1) {
690*4882a593Smuzhiyun --dev->db_tab->max_group1;
691*4882a593Smuzhiyun /* XXX may be able to unmap more pages now */
692*4882a593Smuzhiyun }
693*4882a593Smuzhiyun if (i == dev->db_tab->min_group2)
694*4882a593Smuzhiyun ++dev->db_tab->min_group2;
695*4882a593Smuzhiyun }
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun mutex_unlock(&dev->db_tab->mutex);
698*4882a593Smuzhiyun }
699*4882a593Smuzhiyun
mthca_init_db_tab(struct mthca_dev * dev)700*4882a593Smuzhiyun int mthca_init_db_tab(struct mthca_dev *dev)
701*4882a593Smuzhiyun {
702*4882a593Smuzhiyun int i;
703*4882a593Smuzhiyun
704*4882a593Smuzhiyun if (!mthca_is_memfree(dev))
705*4882a593Smuzhiyun return 0;
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun dev->db_tab = kmalloc(sizeof *dev->db_tab, GFP_KERNEL);
708*4882a593Smuzhiyun if (!dev->db_tab)
709*4882a593Smuzhiyun return -ENOMEM;
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun mutex_init(&dev->db_tab->mutex);
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun dev->db_tab->npages = dev->uar_table.uarc_size / MTHCA_ICM_PAGE_SIZE;
714*4882a593Smuzhiyun dev->db_tab->max_group1 = 0;
715*4882a593Smuzhiyun dev->db_tab->min_group2 = dev->db_tab->npages - 1;
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun dev->db_tab->page = kmalloc_array(dev->db_tab->npages,
718*4882a593Smuzhiyun sizeof(*dev->db_tab->page),
719*4882a593Smuzhiyun GFP_KERNEL);
720*4882a593Smuzhiyun if (!dev->db_tab->page) {
721*4882a593Smuzhiyun kfree(dev->db_tab);
722*4882a593Smuzhiyun return -ENOMEM;
723*4882a593Smuzhiyun }
724*4882a593Smuzhiyun
725*4882a593Smuzhiyun for (i = 0; i < dev->db_tab->npages; ++i)
726*4882a593Smuzhiyun dev->db_tab->page[i].db_rec = NULL;
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun return 0;
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun
mthca_cleanup_db_tab(struct mthca_dev * dev)731*4882a593Smuzhiyun void mthca_cleanup_db_tab(struct mthca_dev *dev)
732*4882a593Smuzhiyun {
733*4882a593Smuzhiyun int i;
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun if (!mthca_is_memfree(dev))
736*4882a593Smuzhiyun return;
737*4882a593Smuzhiyun
738*4882a593Smuzhiyun /*
739*4882a593Smuzhiyun * Because we don't always free our UARC pages when they
740*4882a593Smuzhiyun * become empty to make mthca_free_db() simpler we need to
741*4882a593Smuzhiyun * make a sweep through the doorbell pages and free any
742*4882a593Smuzhiyun * leftover pages now.
743*4882a593Smuzhiyun */
744*4882a593Smuzhiyun for (i = 0; i < dev->db_tab->npages; ++i) {
745*4882a593Smuzhiyun if (!dev->db_tab->page[i].db_rec)
746*4882a593Smuzhiyun continue;
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun if (!bitmap_empty(dev->db_tab->page[i].used, MTHCA_DB_REC_PER_PAGE))
749*4882a593Smuzhiyun mthca_warn(dev, "Kernel UARC page %d not empty\n", i);
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun mthca_UNMAP_ICM(dev, mthca_uarc_virt(dev, &dev->driver_uar, i), 1);
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun dma_free_coherent(&dev->pdev->dev, MTHCA_ICM_PAGE_SIZE,
754*4882a593Smuzhiyun dev->db_tab->page[i].db_rec,
755*4882a593Smuzhiyun dev->db_tab->page[i].mapping);
756*4882a593Smuzhiyun }
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun kfree(dev->db_tab->page);
759*4882a593Smuzhiyun kfree(dev->db_tab);
760*4882a593Smuzhiyun }
761