1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3*4882a593Smuzhiyun * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4*4882a593Smuzhiyun * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
5*4882a593Smuzhiyun * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
6*4882a593Smuzhiyun * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This software is available to you under a choice of one of two
9*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
10*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
11*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
12*4882a593Smuzhiyun * OpenIB.org BSD license below:
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
15*4882a593Smuzhiyun * without modification, are permitted provided that the following
16*4882a593Smuzhiyun * conditions are met:
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * - Redistributions of source code must retain the above
19*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
20*4882a593Smuzhiyun * disclaimer.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
23*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
24*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
25*4882a593Smuzhiyun * provided with the distribution.
26*4882a593Smuzhiyun *
27*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
28*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
29*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
30*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
31*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
32*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34*4882a593Smuzhiyun * SOFTWARE.
35*4882a593Smuzhiyun */
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #ifndef MTHCA_DEV_H
38*4882a593Smuzhiyun #define MTHCA_DEV_H
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #include <linux/spinlock.h>
41*4882a593Smuzhiyun #include <linux/kernel.h>
42*4882a593Smuzhiyun #include <linux/pci.h>
43*4882a593Smuzhiyun #include <linux/dma-mapping.h>
44*4882a593Smuzhiyun #include <linux/timer.h>
45*4882a593Smuzhiyun #include <linux/mutex.h>
46*4882a593Smuzhiyun #include <linux/list.h>
47*4882a593Smuzhiyun #include <linux/semaphore.h>
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #include "mthca_provider.h"
50*4882a593Smuzhiyun #include "mthca_doorbell.h"
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define DRV_NAME "ib_mthca"
53*4882a593Smuzhiyun #define PFX DRV_NAME ": "
54*4882a593Smuzhiyun #define DRV_VERSION "1.0"
55*4882a593Smuzhiyun #define DRV_RELDATE "April 4, 2008"
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun enum {
58*4882a593Smuzhiyun MTHCA_FLAG_DDR_HIDDEN = 1 << 1,
59*4882a593Smuzhiyun MTHCA_FLAG_SRQ = 1 << 2,
60*4882a593Smuzhiyun MTHCA_FLAG_MSI_X = 1 << 3,
61*4882a593Smuzhiyun MTHCA_FLAG_NO_LAM = 1 << 4,
62*4882a593Smuzhiyun MTHCA_FLAG_FMR = 1 << 5,
63*4882a593Smuzhiyun MTHCA_FLAG_MEMFREE = 1 << 6,
64*4882a593Smuzhiyun MTHCA_FLAG_PCIE = 1 << 7,
65*4882a593Smuzhiyun MTHCA_FLAG_SINAI_OPT = 1 << 8
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun enum {
69*4882a593Smuzhiyun MTHCA_MAX_PORTS = 2
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun enum {
73*4882a593Smuzhiyun MTHCA_BOARD_ID_LEN = 64
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun enum {
77*4882a593Smuzhiyun MTHCA_EQ_CONTEXT_SIZE = 0x40,
78*4882a593Smuzhiyun MTHCA_CQ_CONTEXT_SIZE = 0x40,
79*4882a593Smuzhiyun MTHCA_QP_CONTEXT_SIZE = 0x200,
80*4882a593Smuzhiyun MTHCA_RDB_ENTRY_SIZE = 0x20,
81*4882a593Smuzhiyun MTHCA_AV_SIZE = 0x20,
82*4882a593Smuzhiyun MTHCA_MGM_ENTRY_SIZE = 0x100,
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Arbel FW gives us these, but we need them for Tavor */
85*4882a593Smuzhiyun MTHCA_MPT_ENTRY_SIZE = 0x40,
86*4882a593Smuzhiyun MTHCA_MTT_SEG_SIZE = 0x40,
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun MTHCA_QP_PER_MGM = 4 * (MTHCA_MGM_ENTRY_SIZE / 16 - 2)
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun enum {
92*4882a593Smuzhiyun MTHCA_EQ_CMD,
93*4882a593Smuzhiyun MTHCA_EQ_ASYNC,
94*4882a593Smuzhiyun MTHCA_EQ_COMP,
95*4882a593Smuzhiyun MTHCA_NUM_EQ
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun enum {
99*4882a593Smuzhiyun MTHCA_OPCODE_NOP = 0x00,
100*4882a593Smuzhiyun MTHCA_OPCODE_RDMA_WRITE = 0x08,
101*4882a593Smuzhiyun MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
102*4882a593Smuzhiyun MTHCA_OPCODE_SEND = 0x0a,
103*4882a593Smuzhiyun MTHCA_OPCODE_SEND_IMM = 0x0b,
104*4882a593Smuzhiyun MTHCA_OPCODE_RDMA_READ = 0x10,
105*4882a593Smuzhiyun MTHCA_OPCODE_ATOMIC_CS = 0x11,
106*4882a593Smuzhiyun MTHCA_OPCODE_ATOMIC_FA = 0x12,
107*4882a593Smuzhiyun MTHCA_OPCODE_BIND_MW = 0x18,
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun enum {
111*4882a593Smuzhiyun MTHCA_CMD_USE_EVENTS = 1 << 0,
112*4882a593Smuzhiyun MTHCA_CMD_POST_DOORBELLS = 1 << 1
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun enum {
116*4882a593Smuzhiyun MTHCA_CMD_NUM_DBELL_DWORDS = 8
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun struct mthca_cmd {
120*4882a593Smuzhiyun struct dma_pool *pool;
121*4882a593Smuzhiyun struct mutex hcr_mutex;
122*4882a593Smuzhiyun struct semaphore poll_sem;
123*4882a593Smuzhiyun struct semaphore event_sem;
124*4882a593Smuzhiyun int max_cmds;
125*4882a593Smuzhiyun spinlock_t context_lock;
126*4882a593Smuzhiyun int free_head;
127*4882a593Smuzhiyun struct mthca_cmd_context *context;
128*4882a593Smuzhiyun u16 token_mask;
129*4882a593Smuzhiyun u32 flags;
130*4882a593Smuzhiyun void __iomem *dbell_map;
131*4882a593Smuzhiyun u16 dbell_offsets[MTHCA_CMD_NUM_DBELL_DWORDS];
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun struct mthca_limits {
135*4882a593Smuzhiyun int num_ports;
136*4882a593Smuzhiyun int vl_cap;
137*4882a593Smuzhiyun int mtu_cap;
138*4882a593Smuzhiyun int gid_table_len;
139*4882a593Smuzhiyun int pkey_table_len;
140*4882a593Smuzhiyun int local_ca_ack_delay;
141*4882a593Smuzhiyun int num_uars;
142*4882a593Smuzhiyun int max_sg;
143*4882a593Smuzhiyun int num_qps;
144*4882a593Smuzhiyun int max_wqes;
145*4882a593Smuzhiyun int max_desc_sz;
146*4882a593Smuzhiyun int max_qp_init_rdma;
147*4882a593Smuzhiyun int reserved_qps;
148*4882a593Smuzhiyun int num_srqs;
149*4882a593Smuzhiyun int max_srq_wqes;
150*4882a593Smuzhiyun int max_srq_sge;
151*4882a593Smuzhiyun int reserved_srqs;
152*4882a593Smuzhiyun int num_eecs;
153*4882a593Smuzhiyun int reserved_eecs;
154*4882a593Smuzhiyun int num_cqs;
155*4882a593Smuzhiyun int max_cqes;
156*4882a593Smuzhiyun int reserved_cqs;
157*4882a593Smuzhiyun int num_eqs;
158*4882a593Smuzhiyun int reserved_eqs;
159*4882a593Smuzhiyun int num_mpts;
160*4882a593Smuzhiyun int num_mtt_segs;
161*4882a593Smuzhiyun int mtt_seg_size;
162*4882a593Smuzhiyun int fmr_reserved_mtts;
163*4882a593Smuzhiyun int reserved_mtts;
164*4882a593Smuzhiyun int reserved_mrws;
165*4882a593Smuzhiyun int reserved_uars;
166*4882a593Smuzhiyun int num_mgms;
167*4882a593Smuzhiyun int num_amgms;
168*4882a593Smuzhiyun int reserved_mcgs;
169*4882a593Smuzhiyun int num_pds;
170*4882a593Smuzhiyun int reserved_pds;
171*4882a593Smuzhiyun u32 page_size_cap;
172*4882a593Smuzhiyun u32 flags;
173*4882a593Smuzhiyun u16 stat_rate_support;
174*4882a593Smuzhiyun u8 port_width_cap;
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun struct mthca_alloc {
178*4882a593Smuzhiyun u32 last;
179*4882a593Smuzhiyun u32 top;
180*4882a593Smuzhiyun u32 max;
181*4882a593Smuzhiyun u32 mask;
182*4882a593Smuzhiyun spinlock_t lock;
183*4882a593Smuzhiyun unsigned long *table;
184*4882a593Smuzhiyun };
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun struct mthca_array {
187*4882a593Smuzhiyun struct {
188*4882a593Smuzhiyun void **page;
189*4882a593Smuzhiyun int used;
190*4882a593Smuzhiyun } *page_list;
191*4882a593Smuzhiyun };
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun struct mthca_uar_table {
194*4882a593Smuzhiyun struct mthca_alloc alloc;
195*4882a593Smuzhiyun u64 uarc_base;
196*4882a593Smuzhiyun int uarc_size;
197*4882a593Smuzhiyun };
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun struct mthca_pd_table {
200*4882a593Smuzhiyun struct mthca_alloc alloc;
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun struct mthca_buddy {
204*4882a593Smuzhiyun unsigned long **bits;
205*4882a593Smuzhiyun int *num_free;
206*4882a593Smuzhiyun int max_order;
207*4882a593Smuzhiyun spinlock_t lock;
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun struct mthca_mr_table {
211*4882a593Smuzhiyun struct mthca_alloc mpt_alloc;
212*4882a593Smuzhiyun struct mthca_buddy mtt_buddy;
213*4882a593Smuzhiyun struct mthca_buddy *fmr_mtt_buddy;
214*4882a593Smuzhiyun u64 mtt_base;
215*4882a593Smuzhiyun u64 mpt_base;
216*4882a593Smuzhiyun struct mthca_icm_table *mtt_table;
217*4882a593Smuzhiyun struct mthca_icm_table *mpt_table;
218*4882a593Smuzhiyun struct {
219*4882a593Smuzhiyun void __iomem *mpt_base;
220*4882a593Smuzhiyun void __iomem *mtt_base;
221*4882a593Smuzhiyun struct mthca_buddy mtt_buddy;
222*4882a593Smuzhiyun } tavor_fmr;
223*4882a593Smuzhiyun };
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun struct mthca_eq_table {
226*4882a593Smuzhiyun struct mthca_alloc alloc;
227*4882a593Smuzhiyun void __iomem *clr_int;
228*4882a593Smuzhiyun u32 clr_mask;
229*4882a593Smuzhiyun u32 arm_mask;
230*4882a593Smuzhiyun struct mthca_eq eq[MTHCA_NUM_EQ];
231*4882a593Smuzhiyun u64 icm_virt;
232*4882a593Smuzhiyun struct page *icm_page;
233*4882a593Smuzhiyun dma_addr_t icm_dma;
234*4882a593Smuzhiyun int have_irq;
235*4882a593Smuzhiyun u8 inta_pin;
236*4882a593Smuzhiyun };
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun struct mthca_cq_table {
239*4882a593Smuzhiyun struct mthca_alloc alloc;
240*4882a593Smuzhiyun spinlock_t lock;
241*4882a593Smuzhiyun struct mthca_array cq;
242*4882a593Smuzhiyun struct mthca_icm_table *table;
243*4882a593Smuzhiyun };
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun struct mthca_srq_table {
246*4882a593Smuzhiyun struct mthca_alloc alloc;
247*4882a593Smuzhiyun spinlock_t lock;
248*4882a593Smuzhiyun struct mthca_array srq;
249*4882a593Smuzhiyun struct mthca_icm_table *table;
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun struct mthca_qp_table {
253*4882a593Smuzhiyun struct mthca_alloc alloc;
254*4882a593Smuzhiyun u32 rdb_base;
255*4882a593Smuzhiyun int rdb_shift;
256*4882a593Smuzhiyun int sqp_start;
257*4882a593Smuzhiyun spinlock_t lock;
258*4882a593Smuzhiyun struct mthca_array qp;
259*4882a593Smuzhiyun struct mthca_icm_table *qp_table;
260*4882a593Smuzhiyun struct mthca_icm_table *eqp_table;
261*4882a593Smuzhiyun struct mthca_icm_table *rdb_table;
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun struct mthca_av_table {
265*4882a593Smuzhiyun struct dma_pool *pool;
266*4882a593Smuzhiyun int num_ddr_avs;
267*4882a593Smuzhiyun u64 ddr_av_base;
268*4882a593Smuzhiyun void __iomem *av_map;
269*4882a593Smuzhiyun struct mthca_alloc alloc;
270*4882a593Smuzhiyun };
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun struct mthca_mcg_table {
273*4882a593Smuzhiyun struct mutex mutex;
274*4882a593Smuzhiyun struct mthca_alloc alloc;
275*4882a593Smuzhiyun struct mthca_icm_table *table;
276*4882a593Smuzhiyun };
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun struct mthca_catas_err {
279*4882a593Smuzhiyun u64 addr;
280*4882a593Smuzhiyun u32 __iomem *map;
281*4882a593Smuzhiyun u32 size;
282*4882a593Smuzhiyun struct timer_list timer;
283*4882a593Smuzhiyun struct list_head list;
284*4882a593Smuzhiyun };
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun extern struct mutex mthca_device_mutex;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun struct mthca_dev {
289*4882a593Smuzhiyun struct ib_device ib_dev;
290*4882a593Smuzhiyun struct pci_dev *pdev;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun int hca_type;
293*4882a593Smuzhiyun unsigned long mthca_flags;
294*4882a593Smuzhiyun unsigned long device_cap_flags;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun u32 rev_id;
297*4882a593Smuzhiyun char board_id[MTHCA_BOARD_ID_LEN];
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun /* firmware info */
300*4882a593Smuzhiyun u64 fw_ver;
301*4882a593Smuzhiyun union {
302*4882a593Smuzhiyun struct {
303*4882a593Smuzhiyun u64 fw_start;
304*4882a593Smuzhiyun u64 fw_end;
305*4882a593Smuzhiyun } tavor;
306*4882a593Smuzhiyun struct {
307*4882a593Smuzhiyun u64 clr_int_base;
308*4882a593Smuzhiyun u64 eq_arm_base;
309*4882a593Smuzhiyun u64 eq_set_ci_base;
310*4882a593Smuzhiyun struct mthca_icm *fw_icm;
311*4882a593Smuzhiyun struct mthca_icm *aux_icm;
312*4882a593Smuzhiyun u16 fw_pages;
313*4882a593Smuzhiyun } arbel;
314*4882a593Smuzhiyun } fw;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun u64 ddr_start;
317*4882a593Smuzhiyun u64 ddr_end;
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun MTHCA_DECLARE_DOORBELL_LOCK(doorbell_lock)
320*4882a593Smuzhiyun struct mutex cap_mask_mutex;
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun void __iomem *hcr;
323*4882a593Smuzhiyun void __iomem *kar;
324*4882a593Smuzhiyun void __iomem *clr_base;
325*4882a593Smuzhiyun union {
326*4882a593Smuzhiyun struct {
327*4882a593Smuzhiyun void __iomem *ecr_base;
328*4882a593Smuzhiyun } tavor;
329*4882a593Smuzhiyun struct {
330*4882a593Smuzhiyun void __iomem *eq_arm;
331*4882a593Smuzhiyun void __iomem *eq_set_ci_base;
332*4882a593Smuzhiyun } arbel;
333*4882a593Smuzhiyun } eq_regs;
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun struct mthca_cmd cmd;
336*4882a593Smuzhiyun struct mthca_limits limits;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun struct mthca_uar_table uar_table;
339*4882a593Smuzhiyun struct mthca_pd_table pd_table;
340*4882a593Smuzhiyun struct mthca_mr_table mr_table;
341*4882a593Smuzhiyun struct mthca_eq_table eq_table;
342*4882a593Smuzhiyun struct mthca_cq_table cq_table;
343*4882a593Smuzhiyun struct mthca_srq_table srq_table;
344*4882a593Smuzhiyun struct mthca_qp_table qp_table;
345*4882a593Smuzhiyun struct mthca_av_table av_table;
346*4882a593Smuzhiyun struct mthca_mcg_table mcg_table;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun struct mthca_catas_err catas_err;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun struct mthca_uar driver_uar;
351*4882a593Smuzhiyun struct mthca_db_table *db_tab;
352*4882a593Smuzhiyun struct mthca_pd driver_pd;
353*4882a593Smuzhiyun struct mthca_mr driver_mr;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun struct ib_mad_agent *send_agent[MTHCA_MAX_PORTS][2];
356*4882a593Smuzhiyun struct ib_ah *sm_ah[MTHCA_MAX_PORTS];
357*4882a593Smuzhiyun spinlock_t sm_lock;
358*4882a593Smuzhiyun u8 rate[MTHCA_MAX_PORTS];
359*4882a593Smuzhiyun bool active;
360*4882a593Smuzhiyun };
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun #ifdef CONFIG_INFINIBAND_MTHCA_DEBUG
363*4882a593Smuzhiyun extern int mthca_debug_level;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun #define mthca_dbg(mdev, format, arg...) \
366*4882a593Smuzhiyun do { \
367*4882a593Smuzhiyun if (mthca_debug_level) \
368*4882a593Smuzhiyun dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \
369*4882a593Smuzhiyun } while (0)
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun #else /* CONFIG_INFINIBAND_MTHCA_DEBUG */
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun #define mthca_dbg(mdev, format, arg...) do { (void) mdev; } while (0)
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun #endif /* CONFIG_INFINIBAND_MTHCA_DEBUG */
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun #define mthca_err(mdev, format, arg...) \
378*4882a593Smuzhiyun dev_err(&mdev->pdev->dev, format, ## arg)
379*4882a593Smuzhiyun #define mthca_info(mdev, format, arg...) \
380*4882a593Smuzhiyun dev_info(&mdev->pdev->dev, format, ## arg)
381*4882a593Smuzhiyun #define mthca_warn(mdev, format, arg...) \
382*4882a593Smuzhiyun dev_warn(&mdev->pdev->dev, format, ## arg)
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun extern void __buggy_use_of_MTHCA_GET(void);
385*4882a593Smuzhiyun extern void __buggy_use_of_MTHCA_PUT(void);
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun #define MTHCA_GET(dest, source, offset) \
388*4882a593Smuzhiyun do { \
389*4882a593Smuzhiyun void *__p = (char *) (source) + (offset); \
390*4882a593Smuzhiyun switch (sizeof (dest)) { \
391*4882a593Smuzhiyun case 1: (dest) = *(u8 *) __p; break; \
392*4882a593Smuzhiyun case 2: (dest) = be16_to_cpup(__p); break; \
393*4882a593Smuzhiyun case 4: (dest) = be32_to_cpup(__p); break; \
394*4882a593Smuzhiyun case 8: (dest) = be64_to_cpup(__p); break; \
395*4882a593Smuzhiyun default: __buggy_use_of_MTHCA_GET(); \
396*4882a593Smuzhiyun } \
397*4882a593Smuzhiyun } while (0)
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun #define MTHCA_PUT(dest, source, offset) \
400*4882a593Smuzhiyun do { \
401*4882a593Smuzhiyun void *__d = ((char *) (dest) + (offset)); \
402*4882a593Smuzhiyun switch (sizeof(source)) { \
403*4882a593Smuzhiyun case 1: *(u8 *) __d = (source); break; \
404*4882a593Smuzhiyun case 2: *(__be16 *) __d = cpu_to_be16(source); break; \
405*4882a593Smuzhiyun case 4: *(__be32 *) __d = cpu_to_be32(source); break; \
406*4882a593Smuzhiyun case 8: *(__be64 *) __d = cpu_to_be64(source); break; \
407*4882a593Smuzhiyun default: __buggy_use_of_MTHCA_PUT(); \
408*4882a593Smuzhiyun } \
409*4882a593Smuzhiyun } while (0)
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun int mthca_reset(struct mthca_dev *mdev);
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun u32 mthca_alloc(struct mthca_alloc *alloc);
414*4882a593Smuzhiyun void mthca_free(struct mthca_alloc *alloc, u32 obj);
415*4882a593Smuzhiyun int mthca_alloc_init(struct mthca_alloc *alloc, u32 num, u32 mask,
416*4882a593Smuzhiyun u32 reserved);
417*4882a593Smuzhiyun void mthca_alloc_cleanup(struct mthca_alloc *alloc);
418*4882a593Smuzhiyun void *mthca_array_get(struct mthca_array *array, int index);
419*4882a593Smuzhiyun int mthca_array_set(struct mthca_array *array, int index, void *value);
420*4882a593Smuzhiyun void mthca_array_clear(struct mthca_array *array, int index);
421*4882a593Smuzhiyun int mthca_array_init(struct mthca_array *array, int nent);
422*4882a593Smuzhiyun void mthca_array_cleanup(struct mthca_array *array, int nent);
423*4882a593Smuzhiyun int mthca_buf_alloc(struct mthca_dev *dev, int size, int max_direct,
424*4882a593Smuzhiyun union mthca_buf *buf, int *is_direct, struct mthca_pd *pd,
425*4882a593Smuzhiyun int hca_write, struct mthca_mr *mr);
426*4882a593Smuzhiyun void mthca_buf_free(struct mthca_dev *dev, int size, union mthca_buf *buf,
427*4882a593Smuzhiyun int is_direct, struct mthca_mr *mr);
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun int mthca_init_uar_table(struct mthca_dev *dev);
430*4882a593Smuzhiyun int mthca_init_pd_table(struct mthca_dev *dev);
431*4882a593Smuzhiyun int mthca_init_mr_table(struct mthca_dev *dev);
432*4882a593Smuzhiyun int mthca_init_eq_table(struct mthca_dev *dev);
433*4882a593Smuzhiyun int mthca_init_cq_table(struct mthca_dev *dev);
434*4882a593Smuzhiyun int mthca_init_srq_table(struct mthca_dev *dev);
435*4882a593Smuzhiyun int mthca_init_qp_table(struct mthca_dev *dev);
436*4882a593Smuzhiyun int mthca_init_av_table(struct mthca_dev *dev);
437*4882a593Smuzhiyun int mthca_init_mcg_table(struct mthca_dev *dev);
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun void mthca_cleanup_uar_table(struct mthca_dev *dev);
440*4882a593Smuzhiyun void mthca_cleanup_pd_table(struct mthca_dev *dev);
441*4882a593Smuzhiyun void mthca_cleanup_mr_table(struct mthca_dev *dev);
442*4882a593Smuzhiyun void mthca_cleanup_eq_table(struct mthca_dev *dev);
443*4882a593Smuzhiyun void mthca_cleanup_cq_table(struct mthca_dev *dev);
444*4882a593Smuzhiyun void mthca_cleanup_srq_table(struct mthca_dev *dev);
445*4882a593Smuzhiyun void mthca_cleanup_qp_table(struct mthca_dev *dev);
446*4882a593Smuzhiyun void mthca_cleanup_av_table(struct mthca_dev *dev);
447*4882a593Smuzhiyun void mthca_cleanup_mcg_table(struct mthca_dev *dev);
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun int mthca_register_device(struct mthca_dev *dev);
450*4882a593Smuzhiyun void mthca_unregister_device(struct mthca_dev *dev);
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun void mthca_start_catas_poll(struct mthca_dev *dev);
453*4882a593Smuzhiyun void mthca_stop_catas_poll(struct mthca_dev *dev);
454*4882a593Smuzhiyun int __mthca_restart_one(struct pci_dev *pdev);
455*4882a593Smuzhiyun int mthca_catas_init(void);
456*4882a593Smuzhiyun void mthca_catas_cleanup(void);
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun int mthca_uar_alloc(struct mthca_dev *dev, struct mthca_uar *uar);
459*4882a593Smuzhiyun void mthca_uar_free(struct mthca_dev *dev, struct mthca_uar *uar);
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun int mthca_pd_alloc(struct mthca_dev *dev, int privileged, struct mthca_pd *pd);
462*4882a593Smuzhiyun void mthca_pd_free(struct mthca_dev *dev, struct mthca_pd *pd);
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun int mthca_write_mtt_size(struct mthca_dev *dev);
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size);
467*4882a593Smuzhiyun void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt);
468*4882a593Smuzhiyun int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
469*4882a593Smuzhiyun int start_index, u64 *buffer_list, int list_len);
470*4882a593Smuzhiyun int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
471*4882a593Smuzhiyun u64 iova, u64 total_size, u32 access, struct mthca_mr *mr);
472*4882a593Smuzhiyun int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
473*4882a593Smuzhiyun u32 access, struct mthca_mr *mr);
474*4882a593Smuzhiyun int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
475*4882a593Smuzhiyun u64 *buffer_list, int buffer_size_shift,
476*4882a593Smuzhiyun int list_len, u64 iova, u64 total_size,
477*4882a593Smuzhiyun u32 access, struct mthca_mr *mr);
478*4882a593Smuzhiyun void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr);
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun int mthca_map_eq_icm(struct mthca_dev *dev, u64 icm_virt);
481*4882a593Smuzhiyun void mthca_unmap_eq_icm(struct mthca_dev *dev);
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
484*4882a593Smuzhiyun struct ib_wc *entry);
485*4882a593Smuzhiyun int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
486*4882a593Smuzhiyun int mthca_arbel_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags);
487*4882a593Smuzhiyun int mthca_init_cq(struct mthca_dev *dev, int nent,
488*4882a593Smuzhiyun struct mthca_ucontext *ctx, u32 pdn,
489*4882a593Smuzhiyun struct mthca_cq *cq);
490*4882a593Smuzhiyun void mthca_free_cq(struct mthca_dev *dev,
491*4882a593Smuzhiyun struct mthca_cq *cq);
492*4882a593Smuzhiyun void mthca_cq_completion(struct mthca_dev *dev, u32 cqn);
493*4882a593Smuzhiyun void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
494*4882a593Smuzhiyun enum ib_event_type event_type);
495*4882a593Smuzhiyun void mthca_cq_clean(struct mthca_dev *dev, struct mthca_cq *cq, u32 qpn,
496*4882a593Smuzhiyun struct mthca_srq *srq);
497*4882a593Smuzhiyun void mthca_cq_resize_copy_cqes(struct mthca_cq *cq);
498*4882a593Smuzhiyun int mthca_alloc_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int nent);
499*4882a593Smuzhiyun void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq_buf *buf, int cqe);
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun int mthca_alloc_srq(struct mthca_dev *dev, struct mthca_pd *pd,
502*4882a593Smuzhiyun struct ib_srq_attr *attr, struct mthca_srq *srq,
503*4882a593Smuzhiyun struct ib_udata *udata);
504*4882a593Smuzhiyun void mthca_free_srq(struct mthca_dev *dev, struct mthca_srq *srq);
505*4882a593Smuzhiyun int mthca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
506*4882a593Smuzhiyun enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
507*4882a593Smuzhiyun int mthca_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr);
508*4882a593Smuzhiyun int mthca_max_srq_sge(struct mthca_dev *dev);
509*4882a593Smuzhiyun void mthca_srq_event(struct mthca_dev *dev, u32 srqn,
510*4882a593Smuzhiyun enum ib_event_type event_type);
511*4882a593Smuzhiyun void mthca_free_srq_wqe(struct mthca_srq *srq, u32 wqe_addr);
512*4882a593Smuzhiyun int mthca_tavor_post_srq_recv(struct ib_srq *srq, const struct ib_recv_wr *wr,
513*4882a593Smuzhiyun const struct ib_recv_wr **bad_wr);
514*4882a593Smuzhiyun int mthca_arbel_post_srq_recv(struct ib_srq *srq, const struct ib_recv_wr *wr,
515*4882a593Smuzhiyun const struct ib_recv_wr **bad_wr);
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
518*4882a593Smuzhiyun enum ib_event_type event_type);
519*4882a593Smuzhiyun int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
520*4882a593Smuzhiyun struct ib_qp_init_attr *qp_init_attr);
521*4882a593Smuzhiyun int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
522*4882a593Smuzhiyun struct ib_udata *udata);
523*4882a593Smuzhiyun int mthca_tavor_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
524*4882a593Smuzhiyun const struct ib_send_wr **bad_wr);
525*4882a593Smuzhiyun int mthca_tavor_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
526*4882a593Smuzhiyun const struct ib_recv_wr **bad_wr);
527*4882a593Smuzhiyun int mthca_arbel_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
528*4882a593Smuzhiyun const struct ib_send_wr **bad_wr);
529*4882a593Smuzhiyun int mthca_arbel_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
530*4882a593Smuzhiyun const struct ib_recv_wr **bad_wr);
531*4882a593Smuzhiyun void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
532*4882a593Smuzhiyun int index, int *dbd, __be32 *new_wqe);
533*4882a593Smuzhiyun int mthca_alloc_qp(struct mthca_dev *dev,
534*4882a593Smuzhiyun struct mthca_pd *pd,
535*4882a593Smuzhiyun struct mthca_cq *send_cq,
536*4882a593Smuzhiyun struct mthca_cq *recv_cq,
537*4882a593Smuzhiyun enum ib_qp_type type,
538*4882a593Smuzhiyun enum ib_sig_type send_policy,
539*4882a593Smuzhiyun struct ib_qp_cap *cap,
540*4882a593Smuzhiyun struct mthca_qp *qp,
541*4882a593Smuzhiyun struct ib_udata *udata);
542*4882a593Smuzhiyun int mthca_alloc_sqp(struct mthca_dev *dev,
543*4882a593Smuzhiyun struct mthca_pd *pd,
544*4882a593Smuzhiyun struct mthca_cq *send_cq,
545*4882a593Smuzhiyun struct mthca_cq *recv_cq,
546*4882a593Smuzhiyun enum ib_sig_type send_policy,
547*4882a593Smuzhiyun struct ib_qp_cap *cap,
548*4882a593Smuzhiyun int qpn,
549*4882a593Smuzhiyun int port,
550*4882a593Smuzhiyun struct mthca_qp *qp,
551*4882a593Smuzhiyun struct ib_udata *udata);
552*4882a593Smuzhiyun void mthca_free_qp(struct mthca_dev *dev, struct mthca_qp *qp);
553*4882a593Smuzhiyun int mthca_create_ah(struct mthca_dev *dev,
554*4882a593Smuzhiyun struct mthca_pd *pd,
555*4882a593Smuzhiyun struct rdma_ah_attr *ah_attr,
556*4882a593Smuzhiyun struct mthca_ah *ah);
557*4882a593Smuzhiyun int mthca_destroy_ah(struct mthca_dev *dev, struct mthca_ah *ah);
558*4882a593Smuzhiyun int mthca_read_ah(struct mthca_dev *dev, struct mthca_ah *ah,
559*4882a593Smuzhiyun struct ib_ud_header *header);
560*4882a593Smuzhiyun int mthca_ah_query(struct ib_ah *ibah, struct rdma_ah_attr *attr);
561*4882a593Smuzhiyun int mthca_ah_grh_present(struct mthca_ah *ah);
562*4882a593Smuzhiyun u8 mthca_get_rate(struct mthca_dev *dev, int static_rate, u8 port);
563*4882a593Smuzhiyun enum ib_rate mthca_rate_to_ib(struct mthca_dev *dev, u8 mthca_rate, u8 port);
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun int mthca_multicast_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
566*4882a593Smuzhiyun int mthca_multicast_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid);
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun int mthca_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num,
569*4882a593Smuzhiyun const struct ib_wc *in_wc, const struct ib_grh *in_grh,
570*4882a593Smuzhiyun const struct ib_mad *in, struct ib_mad *out,
571*4882a593Smuzhiyun size_t *out_mad_size, u16 *out_mad_pkey_index);
572*4882a593Smuzhiyun int mthca_create_agents(struct mthca_dev *dev);
573*4882a593Smuzhiyun void mthca_free_agents(struct mthca_dev *dev);
574*4882a593Smuzhiyun
to_mdev(struct ib_device * ibdev)575*4882a593Smuzhiyun static inline struct mthca_dev *to_mdev(struct ib_device *ibdev)
576*4882a593Smuzhiyun {
577*4882a593Smuzhiyun return container_of(ibdev, struct mthca_dev, ib_dev);
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun
mthca_is_memfree(struct mthca_dev * dev)580*4882a593Smuzhiyun static inline int mthca_is_memfree(struct mthca_dev *dev)
581*4882a593Smuzhiyun {
582*4882a593Smuzhiyun return dev->mthca_flags & MTHCA_FLAG_MEMFREE;
583*4882a593Smuzhiyun }
584*4882a593Smuzhiyun
585*4882a593Smuzhiyun #endif /* MTHCA_DEV_H */
586