1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2005 Cisco Systems. All rights reserved.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This software is available to you under a choice of one of two
5*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
6*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
7*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
8*4882a593Smuzhiyun * OpenIB.org BSD license below:
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
11*4882a593Smuzhiyun * without modification, are permitted provided that the following
12*4882a593Smuzhiyun * conditions are met:
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * - Redistributions of source code must retain the above
15*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
16*4882a593Smuzhiyun * disclaimer.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
19*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
20*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
21*4882a593Smuzhiyun * provided with the distribution.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30*4882a593Smuzhiyun * SOFTWARE.
31*4882a593Smuzhiyun */
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #include <linux/jiffies.h>
34*4882a593Smuzhiyun #include <linux/module.h>
35*4882a593Smuzhiyun #include <linux/timer.h>
36*4882a593Smuzhiyun #include <linux/workqueue.h>
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #include "mthca_dev.h"
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun enum {
41*4882a593Smuzhiyun MTHCA_CATAS_POLL_INTERVAL = 5 * HZ,
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun MTHCA_CATAS_TYPE_INTERNAL = 0,
44*4882a593Smuzhiyun MTHCA_CATAS_TYPE_UPLINK = 3,
45*4882a593Smuzhiyun MTHCA_CATAS_TYPE_DDR = 4,
46*4882a593Smuzhiyun MTHCA_CATAS_TYPE_PARITY = 5,
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static DEFINE_SPINLOCK(catas_lock);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static LIST_HEAD(catas_list);
52*4882a593Smuzhiyun static struct workqueue_struct *catas_wq;
53*4882a593Smuzhiyun static struct work_struct catas_work;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun static int catas_reset_disable;
56*4882a593Smuzhiyun module_param_named(catas_reset_disable, catas_reset_disable, int, 0644);
57*4882a593Smuzhiyun MODULE_PARM_DESC(catas_reset_disable, "disable reset on catastrophic event if nonzero");
58*4882a593Smuzhiyun
catas_reset(struct work_struct * work)59*4882a593Smuzhiyun static void catas_reset(struct work_struct *work)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun struct mthca_dev *dev, *tmpdev;
62*4882a593Smuzhiyun LIST_HEAD(tlist);
63*4882a593Smuzhiyun int ret;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun mutex_lock(&mthca_device_mutex);
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun spin_lock_irq(&catas_lock);
68*4882a593Smuzhiyun list_splice_init(&catas_list, &tlist);
69*4882a593Smuzhiyun spin_unlock_irq(&catas_lock);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun list_for_each_entry_safe(dev, tmpdev, &tlist, catas_err.list) {
72*4882a593Smuzhiyun struct pci_dev *pdev = dev->pdev;
73*4882a593Smuzhiyun ret = __mthca_restart_one(dev->pdev);
74*4882a593Smuzhiyun /* 'dev' now is not valid */
75*4882a593Smuzhiyun if (ret)
76*4882a593Smuzhiyun printk(KERN_ERR "mthca %s: Reset failed (%d)\n",
77*4882a593Smuzhiyun pci_name(pdev), ret);
78*4882a593Smuzhiyun else {
79*4882a593Smuzhiyun struct mthca_dev *d = pci_get_drvdata(pdev);
80*4882a593Smuzhiyun mthca_dbg(d, "Reset succeeded\n");
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun mutex_unlock(&mthca_device_mutex);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
handle_catas(struct mthca_dev * dev)87*4882a593Smuzhiyun static void handle_catas(struct mthca_dev *dev)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun struct ib_event event;
90*4882a593Smuzhiyun unsigned long flags;
91*4882a593Smuzhiyun const char *type;
92*4882a593Smuzhiyun int i;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun event.device = &dev->ib_dev;
95*4882a593Smuzhiyun event.event = IB_EVENT_DEVICE_FATAL;
96*4882a593Smuzhiyun event.element.port_num = 0;
97*4882a593Smuzhiyun dev->active = false;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun ib_dispatch_event(&event);
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun switch (swab32(readl(dev->catas_err.map)) >> 24) {
102*4882a593Smuzhiyun case MTHCA_CATAS_TYPE_INTERNAL:
103*4882a593Smuzhiyun type = "internal error";
104*4882a593Smuzhiyun break;
105*4882a593Smuzhiyun case MTHCA_CATAS_TYPE_UPLINK:
106*4882a593Smuzhiyun type = "uplink bus error";
107*4882a593Smuzhiyun break;
108*4882a593Smuzhiyun case MTHCA_CATAS_TYPE_DDR:
109*4882a593Smuzhiyun type = "DDR data error";
110*4882a593Smuzhiyun break;
111*4882a593Smuzhiyun case MTHCA_CATAS_TYPE_PARITY:
112*4882a593Smuzhiyun type = "internal parity error";
113*4882a593Smuzhiyun break;
114*4882a593Smuzhiyun default:
115*4882a593Smuzhiyun type = "unknown error";
116*4882a593Smuzhiyun break;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun mthca_err(dev, "Catastrophic error detected: %s\n", type);
120*4882a593Smuzhiyun for (i = 0; i < dev->catas_err.size; ++i)
121*4882a593Smuzhiyun mthca_err(dev, " buf[%02x]: %08x\n",
122*4882a593Smuzhiyun i, swab32(readl(dev->catas_err.map + i)));
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun if (catas_reset_disable)
125*4882a593Smuzhiyun return;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun spin_lock_irqsave(&catas_lock, flags);
128*4882a593Smuzhiyun list_add(&dev->catas_err.list, &catas_list);
129*4882a593Smuzhiyun queue_work(catas_wq, &catas_work);
130*4882a593Smuzhiyun spin_unlock_irqrestore(&catas_lock, flags);
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
poll_catas(struct timer_list * t)133*4882a593Smuzhiyun static void poll_catas(struct timer_list *t)
134*4882a593Smuzhiyun {
135*4882a593Smuzhiyun struct mthca_dev *dev = from_timer(dev, t, catas_err.timer);
136*4882a593Smuzhiyun int i;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun for (i = 0; i < dev->catas_err.size; ++i)
139*4882a593Smuzhiyun if (readl(dev->catas_err.map + i)) {
140*4882a593Smuzhiyun handle_catas(dev);
141*4882a593Smuzhiyun return;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun mod_timer(&dev->catas_err.timer,
145*4882a593Smuzhiyun round_jiffies(jiffies + MTHCA_CATAS_POLL_INTERVAL));
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun
mthca_start_catas_poll(struct mthca_dev * dev)148*4882a593Smuzhiyun void mthca_start_catas_poll(struct mthca_dev *dev)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun phys_addr_t addr;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun timer_setup(&dev->catas_err.timer, poll_catas, 0);
153*4882a593Smuzhiyun dev->catas_err.map = NULL;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun addr = pci_resource_start(dev->pdev, 0) +
156*4882a593Smuzhiyun ((pci_resource_len(dev->pdev, 0) - 1) &
157*4882a593Smuzhiyun dev->catas_err.addr);
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun dev->catas_err.map = ioremap(addr, dev->catas_err.size * 4);
160*4882a593Smuzhiyun if (!dev->catas_err.map) {
161*4882a593Smuzhiyun mthca_warn(dev, "couldn't map catastrophic error region "
162*4882a593Smuzhiyun "at 0x%llx/0x%x\n", (unsigned long long) addr,
163*4882a593Smuzhiyun dev->catas_err.size * 4);
164*4882a593Smuzhiyun return;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun dev->catas_err.timer.expires = jiffies + MTHCA_CATAS_POLL_INTERVAL;
168*4882a593Smuzhiyun INIT_LIST_HEAD(&dev->catas_err.list);
169*4882a593Smuzhiyun add_timer(&dev->catas_err.timer);
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
mthca_stop_catas_poll(struct mthca_dev * dev)172*4882a593Smuzhiyun void mthca_stop_catas_poll(struct mthca_dev *dev)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun del_timer_sync(&dev->catas_err.timer);
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun if (dev->catas_err.map)
177*4882a593Smuzhiyun iounmap(dev->catas_err.map);
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun spin_lock_irq(&catas_lock);
180*4882a593Smuzhiyun list_del(&dev->catas_err.list);
181*4882a593Smuzhiyun spin_unlock_irq(&catas_lock);
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
mthca_catas_init(void)184*4882a593Smuzhiyun int __init mthca_catas_init(void)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun INIT_WORK(&catas_work, catas_reset);
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun catas_wq = alloc_ordered_workqueue("mthca_catas", WQ_MEM_RECLAIM);
189*4882a593Smuzhiyun if (!catas_wq)
190*4882a593Smuzhiyun return -ENOMEM;
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun return 0;
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
mthca_catas_cleanup(void)195*4882a593Smuzhiyun void mthca_catas_cleanup(void)
196*4882a593Smuzhiyun {
197*4882a593Smuzhiyun destroy_workqueue(catas_wq);
198*4882a593Smuzhiyun }
199