1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3*4882a593Smuzhiyun * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * This software is available to you under a choice of one of two
6*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
7*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
8*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
9*4882a593Smuzhiyun * OpenIB.org BSD license below:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or
12*4882a593Smuzhiyun * without modification, are permitted provided that the following
13*4882a593Smuzhiyun * conditions are met:
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * - Redistributions of source code must retain the above
16*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
17*4882a593Smuzhiyun * disclaimer.
18*4882a593Smuzhiyun *
19*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above
20*4882a593Smuzhiyun * copyright notice, this list of conditions and the following
21*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials
22*4882a593Smuzhiyun * provided with the distribution.
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31*4882a593Smuzhiyun * SOFTWARE.
32*4882a593Smuzhiyun */
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #include <linux/module.h>
35*4882a593Smuzhiyun #include <linux/init.h>
36*4882a593Smuzhiyun #include <linux/slab.h>
37*4882a593Smuzhiyun #include <linux/errno.h>
38*4882a593Smuzhiyun #include <linux/netdevice.h>
39*4882a593Smuzhiyun #include <linux/inetdevice.h>
40*4882a593Smuzhiyun #include <linux/rtnetlink.h>
41*4882a593Smuzhiyun #include <linux/if_vlan.h>
42*4882a593Smuzhiyun #include <linux/sched/mm.h>
43*4882a593Smuzhiyun #include <linux/sched/task.h>
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #include <net/ipv6.h>
46*4882a593Smuzhiyun #include <net/addrconf.h>
47*4882a593Smuzhiyun #include <net/devlink.h>
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #include <rdma/ib_smi.h>
50*4882a593Smuzhiyun #include <rdma/ib_user_verbs.h>
51*4882a593Smuzhiyun #include <rdma/ib_addr.h>
52*4882a593Smuzhiyun #include <rdma/ib_cache.h>
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #include <net/bonding.h>
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #include <linux/mlx4/driver.h>
57*4882a593Smuzhiyun #include <linux/mlx4/cmd.h>
58*4882a593Smuzhiyun #include <linux/mlx4/qp.h>
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun #include "mlx4_ib.h"
61*4882a593Smuzhiyun #include <rdma/mlx4-abi.h>
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #define DRV_NAME MLX4_IB_DRV_NAME
64*4882a593Smuzhiyun #define DRV_VERSION "4.0-0"
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #define MLX4_IB_FLOW_MAX_PRIO 0xFFF
67*4882a593Smuzhiyun #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
68*4882a593Smuzhiyun #define MLX4_IB_CARD_REV_A0 0xA0
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun MODULE_AUTHOR("Roland Dreier");
71*4882a593Smuzhiyun MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
72*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun int mlx4_ib_sm_guid_assign = 0;
75*4882a593Smuzhiyun module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
76*4882a593Smuzhiyun MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun static const char mlx4_ib_version[] =
79*4882a593Smuzhiyun DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
80*4882a593Smuzhiyun DRV_VERSION "\n";
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
83*4882a593Smuzhiyun static enum rdma_link_layer mlx4_ib_port_link_layer(struct ib_device *device,
84*4882a593Smuzhiyun u8 port_num);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun static struct workqueue_struct *wq;
87*4882a593Smuzhiyun
init_query_mad(struct ib_smp * mad)88*4882a593Smuzhiyun static void init_query_mad(struct ib_smp *mad)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun mad->base_version = 1;
91*4882a593Smuzhiyun mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
92*4882a593Smuzhiyun mad->class_version = 1;
93*4882a593Smuzhiyun mad->method = IB_MGMT_METHOD_GET;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
check_flow_steering_support(struct mlx4_dev * dev)96*4882a593Smuzhiyun static int check_flow_steering_support(struct mlx4_dev *dev)
97*4882a593Smuzhiyun {
98*4882a593Smuzhiyun int eth_num_ports = 0;
99*4882a593Smuzhiyun int ib_num_ports = 0;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun if (dmfs) {
104*4882a593Smuzhiyun int i;
105*4882a593Smuzhiyun mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
106*4882a593Smuzhiyun eth_num_ports++;
107*4882a593Smuzhiyun mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
108*4882a593Smuzhiyun ib_num_ports++;
109*4882a593Smuzhiyun dmfs &= (!ib_num_ports ||
110*4882a593Smuzhiyun (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
111*4882a593Smuzhiyun (!eth_num_ports ||
112*4882a593Smuzhiyun (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
113*4882a593Smuzhiyun if (ib_num_ports && mlx4_is_mfunc(dev)) {
114*4882a593Smuzhiyun pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
115*4882a593Smuzhiyun dmfs = 0;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun return dmfs;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
num_ib_ports(struct mlx4_dev * dev)121*4882a593Smuzhiyun static int num_ib_ports(struct mlx4_dev *dev)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun int ib_ports = 0;
124*4882a593Smuzhiyun int i;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
127*4882a593Smuzhiyun ib_ports++;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun return ib_ports;
130*4882a593Smuzhiyun }
131*4882a593Smuzhiyun
mlx4_ib_get_netdev(struct ib_device * device,u8 port_num)132*4882a593Smuzhiyun static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun struct mlx4_ib_dev *ibdev = to_mdev(device);
135*4882a593Smuzhiyun struct net_device *dev;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun rcu_read_lock();
138*4882a593Smuzhiyun dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun if (dev) {
141*4882a593Smuzhiyun if (mlx4_is_bonded(ibdev->dev)) {
142*4882a593Smuzhiyun struct net_device *upper = NULL;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun upper = netdev_master_upper_dev_get_rcu(dev);
145*4882a593Smuzhiyun if (upper) {
146*4882a593Smuzhiyun struct net_device *active;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun active = bond_option_active_slave_get_rcu(netdev_priv(upper));
149*4882a593Smuzhiyun if (active)
150*4882a593Smuzhiyun dev = active;
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun if (dev)
155*4882a593Smuzhiyun dev_hold(dev);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun rcu_read_unlock();
158*4882a593Smuzhiyun return dev;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
mlx4_ib_update_gids_v1(struct gid_entry * gids,struct mlx4_ib_dev * ibdev,u8 port_num)161*4882a593Smuzhiyun static int mlx4_ib_update_gids_v1(struct gid_entry *gids,
162*4882a593Smuzhiyun struct mlx4_ib_dev *ibdev,
163*4882a593Smuzhiyun u8 port_num)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
166*4882a593Smuzhiyun int err;
167*4882a593Smuzhiyun struct mlx4_dev *dev = ibdev->dev;
168*4882a593Smuzhiyun int i;
169*4882a593Smuzhiyun union ib_gid *gid_tbl;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(dev);
172*4882a593Smuzhiyun if (IS_ERR(mailbox))
173*4882a593Smuzhiyun return -ENOMEM;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun gid_tbl = mailbox->buf;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
178*4882a593Smuzhiyun memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun err = mlx4_cmd(dev, mailbox->dma,
181*4882a593Smuzhiyun MLX4_SET_PORT_GID_TABLE << 8 | port_num,
182*4882a593Smuzhiyun 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
183*4882a593Smuzhiyun MLX4_CMD_WRAPPED);
184*4882a593Smuzhiyun if (mlx4_is_bonded(dev))
185*4882a593Smuzhiyun err += mlx4_cmd(dev, mailbox->dma,
186*4882a593Smuzhiyun MLX4_SET_PORT_GID_TABLE << 8 | 2,
187*4882a593Smuzhiyun 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
188*4882a593Smuzhiyun MLX4_CMD_WRAPPED);
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, mailbox);
191*4882a593Smuzhiyun return err;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
mlx4_ib_update_gids_v1_v2(struct gid_entry * gids,struct mlx4_ib_dev * ibdev,u8 port_num)194*4882a593Smuzhiyun static int mlx4_ib_update_gids_v1_v2(struct gid_entry *gids,
195*4882a593Smuzhiyun struct mlx4_ib_dev *ibdev,
196*4882a593Smuzhiyun u8 port_num)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
199*4882a593Smuzhiyun int err;
200*4882a593Smuzhiyun struct mlx4_dev *dev = ibdev->dev;
201*4882a593Smuzhiyun int i;
202*4882a593Smuzhiyun struct {
203*4882a593Smuzhiyun union ib_gid gid;
204*4882a593Smuzhiyun __be32 rsrvd1[2];
205*4882a593Smuzhiyun __be16 rsrvd2;
206*4882a593Smuzhiyun u8 type;
207*4882a593Smuzhiyun u8 version;
208*4882a593Smuzhiyun __be32 rsrvd3;
209*4882a593Smuzhiyun } *gid_tbl;
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(dev);
212*4882a593Smuzhiyun if (IS_ERR(mailbox))
213*4882a593Smuzhiyun return -ENOMEM;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun gid_tbl = mailbox->buf;
216*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
217*4882a593Smuzhiyun memcpy(&gid_tbl[i].gid, &gids[i].gid, sizeof(union ib_gid));
218*4882a593Smuzhiyun if (gids[i].gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) {
219*4882a593Smuzhiyun gid_tbl[i].version = 2;
220*4882a593Smuzhiyun if (!ipv6_addr_v4mapped((struct in6_addr *)&gids[i].gid))
221*4882a593Smuzhiyun gid_tbl[i].type = 1;
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun err = mlx4_cmd(dev, mailbox->dma,
226*4882a593Smuzhiyun MLX4_SET_PORT_ROCE_ADDR << 8 | port_num,
227*4882a593Smuzhiyun 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
228*4882a593Smuzhiyun MLX4_CMD_WRAPPED);
229*4882a593Smuzhiyun if (mlx4_is_bonded(dev))
230*4882a593Smuzhiyun err += mlx4_cmd(dev, mailbox->dma,
231*4882a593Smuzhiyun MLX4_SET_PORT_ROCE_ADDR << 8 | 2,
232*4882a593Smuzhiyun 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
233*4882a593Smuzhiyun MLX4_CMD_WRAPPED);
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev, mailbox);
236*4882a593Smuzhiyun return err;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun
mlx4_ib_update_gids(struct gid_entry * gids,struct mlx4_ib_dev * ibdev,u8 port_num)239*4882a593Smuzhiyun static int mlx4_ib_update_gids(struct gid_entry *gids,
240*4882a593Smuzhiyun struct mlx4_ib_dev *ibdev,
241*4882a593Smuzhiyun u8 port_num)
242*4882a593Smuzhiyun {
243*4882a593Smuzhiyun if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
244*4882a593Smuzhiyun return mlx4_ib_update_gids_v1_v2(gids, ibdev, port_num);
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun return mlx4_ib_update_gids_v1(gids, ibdev, port_num);
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun
free_gid_entry(struct gid_entry * entry)249*4882a593Smuzhiyun static void free_gid_entry(struct gid_entry *entry)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun memset(&entry->gid, 0, sizeof(entry->gid));
252*4882a593Smuzhiyun kfree(entry->ctx);
253*4882a593Smuzhiyun entry->ctx = NULL;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun
mlx4_ib_add_gid(const struct ib_gid_attr * attr,void ** context)256*4882a593Smuzhiyun static int mlx4_ib_add_gid(const struct ib_gid_attr *attr, void **context)
257*4882a593Smuzhiyun {
258*4882a593Smuzhiyun struct mlx4_ib_dev *ibdev = to_mdev(attr->device);
259*4882a593Smuzhiyun struct mlx4_ib_iboe *iboe = &ibdev->iboe;
260*4882a593Smuzhiyun struct mlx4_port_gid_table *port_gid_table;
261*4882a593Smuzhiyun int free = -1, found = -1;
262*4882a593Smuzhiyun int ret = 0;
263*4882a593Smuzhiyun int hw_update = 0;
264*4882a593Smuzhiyun int i;
265*4882a593Smuzhiyun struct gid_entry *gids = NULL;
266*4882a593Smuzhiyun u16 vlan_id = 0xffff;
267*4882a593Smuzhiyun u8 mac[ETH_ALEN];
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun if (!rdma_cap_roce_gid_table(attr->device, attr->port_num))
270*4882a593Smuzhiyun return -EINVAL;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun if (attr->port_num > MLX4_MAX_PORTS)
273*4882a593Smuzhiyun return -EINVAL;
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun if (!context)
276*4882a593Smuzhiyun return -EINVAL;
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun ret = rdma_read_gid_l2_fields(attr, &vlan_id, &mac[0]);
279*4882a593Smuzhiyun if (ret)
280*4882a593Smuzhiyun return ret;
281*4882a593Smuzhiyun port_gid_table = &iboe->gids[attr->port_num - 1];
282*4882a593Smuzhiyun spin_lock_bh(&iboe->lock);
283*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
284*4882a593Smuzhiyun if (!memcmp(&port_gid_table->gids[i].gid,
285*4882a593Smuzhiyun &attr->gid, sizeof(attr->gid)) &&
286*4882a593Smuzhiyun port_gid_table->gids[i].gid_type == attr->gid_type &&
287*4882a593Smuzhiyun port_gid_table->gids[i].vlan_id == vlan_id) {
288*4882a593Smuzhiyun found = i;
289*4882a593Smuzhiyun break;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun if (free < 0 && rdma_is_zero_gid(&port_gid_table->gids[i].gid))
292*4882a593Smuzhiyun free = i; /* HW has space */
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun if (found < 0) {
296*4882a593Smuzhiyun if (free < 0) {
297*4882a593Smuzhiyun ret = -ENOSPC;
298*4882a593Smuzhiyun } else {
299*4882a593Smuzhiyun port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
300*4882a593Smuzhiyun if (!port_gid_table->gids[free].ctx) {
301*4882a593Smuzhiyun ret = -ENOMEM;
302*4882a593Smuzhiyun } else {
303*4882a593Smuzhiyun *context = port_gid_table->gids[free].ctx;
304*4882a593Smuzhiyun memcpy(&port_gid_table->gids[free].gid,
305*4882a593Smuzhiyun &attr->gid, sizeof(attr->gid));
306*4882a593Smuzhiyun port_gid_table->gids[free].gid_type = attr->gid_type;
307*4882a593Smuzhiyun port_gid_table->gids[free].vlan_id = vlan_id;
308*4882a593Smuzhiyun port_gid_table->gids[free].ctx->real_index = free;
309*4882a593Smuzhiyun port_gid_table->gids[free].ctx->refcount = 1;
310*4882a593Smuzhiyun hw_update = 1;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun } else {
314*4882a593Smuzhiyun struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
315*4882a593Smuzhiyun *context = ctx;
316*4882a593Smuzhiyun ctx->refcount++;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun if (!ret && hw_update) {
319*4882a593Smuzhiyun gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids),
320*4882a593Smuzhiyun GFP_ATOMIC);
321*4882a593Smuzhiyun if (!gids) {
322*4882a593Smuzhiyun ret = -ENOMEM;
323*4882a593Smuzhiyun *context = NULL;
324*4882a593Smuzhiyun free_gid_entry(&port_gid_table->gids[free]);
325*4882a593Smuzhiyun } else {
326*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
327*4882a593Smuzhiyun memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
328*4882a593Smuzhiyun gids[i].gid_type = port_gid_table->gids[i].gid_type;
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun }
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun spin_unlock_bh(&iboe->lock);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun if (!ret && hw_update) {
335*4882a593Smuzhiyun ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num);
336*4882a593Smuzhiyun if (ret) {
337*4882a593Smuzhiyun spin_lock_bh(&iboe->lock);
338*4882a593Smuzhiyun *context = NULL;
339*4882a593Smuzhiyun free_gid_entry(&port_gid_table->gids[free]);
340*4882a593Smuzhiyun spin_unlock_bh(&iboe->lock);
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun kfree(gids);
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun return ret;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
mlx4_ib_del_gid(const struct ib_gid_attr * attr,void ** context)348*4882a593Smuzhiyun static int mlx4_ib_del_gid(const struct ib_gid_attr *attr, void **context)
349*4882a593Smuzhiyun {
350*4882a593Smuzhiyun struct gid_cache_context *ctx = *context;
351*4882a593Smuzhiyun struct mlx4_ib_dev *ibdev = to_mdev(attr->device);
352*4882a593Smuzhiyun struct mlx4_ib_iboe *iboe = &ibdev->iboe;
353*4882a593Smuzhiyun struct mlx4_port_gid_table *port_gid_table;
354*4882a593Smuzhiyun int ret = 0;
355*4882a593Smuzhiyun int hw_update = 0;
356*4882a593Smuzhiyun struct gid_entry *gids = NULL;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun if (!rdma_cap_roce_gid_table(attr->device, attr->port_num))
359*4882a593Smuzhiyun return -EINVAL;
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun if (attr->port_num > MLX4_MAX_PORTS)
362*4882a593Smuzhiyun return -EINVAL;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun port_gid_table = &iboe->gids[attr->port_num - 1];
365*4882a593Smuzhiyun spin_lock_bh(&iboe->lock);
366*4882a593Smuzhiyun if (ctx) {
367*4882a593Smuzhiyun ctx->refcount--;
368*4882a593Smuzhiyun if (!ctx->refcount) {
369*4882a593Smuzhiyun unsigned int real_index = ctx->real_index;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun free_gid_entry(&port_gid_table->gids[real_index]);
372*4882a593Smuzhiyun hw_update = 1;
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun if (!ret && hw_update) {
376*4882a593Smuzhiyun int i;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun gids = kmalloc_array(MLX4_MAX_PORT_GIDS, sizeof(*gids),
379*4882a593Smuzhiyun GFP_ATOMIC);
380*4882a593Smuzhiyun if (!gids) {
381*4882a593Smuzhiyun ret = -ENOMEM;
382*4882a593Smuzhiyun } else {
383*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_PORT_GIDS; i++) {
384*4882a593Smuzhiyun memcpy(&gids[i].gid,
385*4882a593Smuzhiyun &port_gid_table->gids[i].gid,
386*4882a593Smuzhiyun sizeof(union ib_gid));
387*4882a593Smuzhiyun gids[i].gid_type =
388*4882a593Smuzhiyun port_gid_table->gids[i].gid_type;
389*4882a593Smuzhiyun }
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun spin_unlock_bh(&iboe->lock);
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun if (!ret && hw_update) {
395*4882a593Smuzhiyun ret = mlx4_ib_update_gids(gids, ibdev, attr->port_num);
396*4882a593Smuzhiyun kfree(gids);
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun return ret;
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun
mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev * ibdev,const struct ib_gid_attr * attr)401*4882a593Smuzhiyun int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
402*4882a593Smuzhiyun const struct ib_gid_attr *attr)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun struct mlx4_ib_iboe *iboe = &ibdev->iboe;
405*4882a593Smuzhiyun struct gid_cache_context *ctx = NULL;
406*4882a593Smuzhiyun struct mlx4_port_gid_table *port_gid_table;
407*4882a593Smuzhiyun int real_index = -EINVAL;
408*4882a593Smuzhiyun int i;
409*4882a593Smuzhiyun unsigned long flags;
410*4882a593Smuzhiyun u8 port_num = attr->port_num;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun if (port_num > MLX4_MAX_PORTS)
413*4882a593Smuzhiyun return -EINVAL;
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun if (mlx4_is_bonded(ibdev->dev))
416*4882a593Smuzhiyun port_num = 1;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
419*4882a593Smuzhiyun return attr->index;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun spin_lock_irqsave(&iboe->lock, flags);
422*4882a593Smuzhiyun port_gid_table = &iboe->gids[port_num - 1];
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
425*4882a593Smuzhiyun if (!memcmp(&port_gid_table->gids[i].gid,
426*4882a593Smuzhiyun &attr->gid, sizeof(attr->gid)) &&
427*4882a593Smuzhiyun attr->gid_type == port_gid_table->gids[i].gid_type) {
428*4882a593Smuzhiyun ctx = port_gid_table->gids[i].ctx;
429*4882a593Smuzhiyun break;
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun if (ctx)
432*4882a593Smuzhiyun real_index = ctx->real_index;
433*4882a593Smuzhiyun spin_unlock_irqrestore(&iboe->lock, flags);
434*4882a593Smuzhiyun return real_index;
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun
mlx4_ib_query_device(struct ib_device * ibdev,struct ib_device_attr * props,struct ib_udata * uhw)437*4882a593Smuzhiyun static int mlx4_ib_query_device(struct ib_device *ibdev,
438*4882a593Smuzhiyun struct ib_device_attr *props,
439*4882a593Smuzhiyun struct ib_udata *uhw)
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun struct mlx4_ib_dev *dev = to_mdev(ibdev);
442*4882a593Smuzhiyun struct ib_smp *in_mad = NULL;
443*4882a593Smuzhiyun struct ib_smp *out_mad = NULL;
444*4882a593Smuzhiyun int err;
445*4882a593Smuzhiyun int have_ib_ports;
446*4882a593Smuzhiyun struct mlx4_uverbs_ex_query_device cmd;
447*4882a593Smuzhiyun struct mlx4_uverbs_ex_query_device_resp resp = {};
448*4882a593Smuzhiyun struct mlx4_clock_params clock_params;
449*4882a593Smuzhiyun
450*4882a593Smuzhiyun if (uhw->inlen) {
451*4882a593Smuzhiyun if (uhw->inlen < sizeof(cmd))
452*4882a593Smuzhiyun return -EINVAL;
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
455*4882a593Smuzhiyun if (err)
456*4882a593Smuzhiyun return err;
457*4882a593Smuzhiyun
458*4882a593Smuzhiyun if (cmd.comp_mask)
459*4882a593Smuzhiyun return -EINVAL;
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun if (cmd.reserved)
462*4882a593Smuzhiyun return -EINVAL;
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun resp.response_length = offsetof(typeof(resp), response_length) +
466*4882a593Smuzhiyun sizeof(resp.response_length);
467*4882a593Smuzhiyun in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
468*4882a593Smuzhiyun out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
469*4882a593Smuzhiyun err = -ENOMEM;
470*4882a593Smuzhiyun if (!in_mad || !out_mad)
471*4882a593Smuzhiyun goto out;
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun init_query_mad(in_mad);
474*4882a593Smuzhiyun in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
477*4882a593Smuzhiyun 1, NULL, NULL, in_mad, out_mad);
478*4882a593Smuzhiyun if (err)
479*4882a593Smuzhiyun goto out;
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun memset(props, 0, sizeof *props);
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun have_ib_ports = num_ib_ports(dev->dev);
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun props->fw_ver = dev->dev->caps.fw_ver;
486*4882a593Smuzhiyun props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
487*4882a593Smuzhiyun IB_DEVICE_PORT_ACTIVE_EVENT |
488*4882a593Smuzhiyun IB_DEVICE_SYS_IMAGE_GUID |
489*4882a593Smuzhiyun IB_DEVICE_RC_RNR_NAK_GEN |
490*4882a593Smuzhiyun IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
491*4882a593Smuzhiyun if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
492*4882a593Smuzhiyun props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
493*4882a593Smuzhiyun if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
494*4882a593Smuzhiyun props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
495*4882a593Smuzhiyun if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
496*4882a593Smuzhiyun props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
497*4882a593Smuzhiyun if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
498*4882a593Smuzhiyun props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
499*4882a593Smuzhiyun if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
500*4882a593Smuzhiyun props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
501*4882a593Smuzhiyun if (dev->dev->caps.max_gso_sz &&
502*4882a593Smuzhiyun (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
503*4882a593Smuzhiyun (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
504*4882a593Smuzhiyun props->device_cap_flags |= IB_DEVICE_UD_TSO;
505*4882a593Smuzhiyun if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
506*4882a593Smuzhiyun props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
507*4882a593Smuzhiyun if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
508*4882a593Smuzhiyun (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
509*4882a593Smuzhiyun (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
510*4882a593Smuzhiyun props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
511*4882a593Smuzhiyun if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
512*4882a593Smuzhiyun props->device_cap_flags |= IB_DEVICE_XRC;
513*4882a593Smuzhiyun if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
514*4882a593Smuzhiyun props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
515*4882a593Smuzhiyun if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
516*4882a593Smuzhiyun if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
517*4882a593Smuzhiyun props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
518*4882a593Smuzhiyun else
519*4882a593Smuzhiyun props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
522*4882a593Smuzhiyun props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
527*4882a593Smuzhiyun 0xffffff;
528*4882a593Smuzhiyun props->vendor_part_id = dev->dev->persist->pdev->device;
529*4882a593Smuzhiyun props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
530*4882a593Smuzhiyun memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun props->max_mr_size = ~0ull;
533*4882a593Smuzhiyun props->page_size_cap = dev->dev->caps.page_size_cap;
534*4882a593Smuzhiyun props->max_qp = dev->dev->quotas.qp;
535*4882a593Smuzhiyun props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
536*4882a593Smuzhiyun props->max_send_sge =
537*4882a593Smuzhiyun min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg);
538*4882a593Smuzhiyun props->max_recv_sge =
539*4882a593Smuzhiyun min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg);
540*4882a593Smuzhiyun props->max_sge_rd = MLX4_MAX_SGE_RD;
541*4882a593Smuzhiyun props->max_cq = dev->dev->quotas.cq;
542*4882a593Smuzhiyun props->max_cqe = dev->dev->caps.max_cqes;
543*4882a593Smuzhiyun props->max_mr = dev->dev->quotas.mpt;
544*4882a593Smuzhiyun props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
545*4882a593Smuzhiyun props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
546*4882a593Smuzhiyun props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
547*4882a593Smuzhiyun props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
548*4882a593Smuzhiyun props->max_srq = dev->dev->quotas.srq;
549*4882a593Smuzhiyun props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
550*4882a593Smuzhiyun props->max_srq_sge = dev->dev->caps.max_srq_sge;
551*4882a593Smuzhiyun props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
552*4882a593Smuzhiyun props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
553*4882a593Smuzhiyun props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
554*4882a593Smuzhiyun IB_ATOMIC_HCA : IB_ATOMIC_NONE;
555*4882a593Smuzhiyun props->masked_atomic_cap = props->atomic_cap;
556*4882a593Smuzhiyun props->max_pkeys = dev->dev->caps.pkey_table_len[1];
557*4882a593Smuzhiyun props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
558*4882a593Smuzhiyun props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
559*4882a593Smuzhiyun props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
560*4882a593Smuzhiyun props->max_mcast_grp;
561*4882a593Smuzhiyun props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
562*4882a593Smuzhiyun props->timestamp_mask = 0xFFFFFFFFFFFFULL;
563*4882a593Smuzhiyun props->max_ah = INT_MAX;
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun if (mlx4_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET ||
566*4882a593Smuzhiyun mlx4_ib_port_link_layer(ibdev, 2) == IB_LINK_LAYER_ETHERNET) {
567*4882a593Smuzhiyun if (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) {
568*4882a593Smuzhiyun props->rss_caps.max_rwq_indirection_tables =
569*4882a593Smuzhiyun props->max_qp;
570*4882a593Smuzhiyun props->rss_caps.max_rwq_indirection_table_size =
571*4882a593Smuzhiyun dev->dev->caps.max_rss_tbl_sz;
572*4882a593Smuzhiyun props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
573*4882a593Smuzhiyun props->max_wq_type_rq = props->max_qp;
574*4882a593Smuzhiyun }
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)
577*4882a593Smuzhiyun props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun props->cq_caps.max_cq_moderation_count = MLX4_MAX_CQ_COUNT;
581*4882a593Smuzhiyun props->cq_caps.max_cq_moderation_period = MLX4_MAX_CQ_PERIOD;
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
584*4882a593Smuzhiyun resp.response_length += sizeof(resp.hca_core_clock_offset);
585*4882a593Smuzhiyun if (!mlx4_get_internal_clock_params(dev->dev, &clock_params)) {
586*4882a593Smuzhiyun resp.comp_mask |= MLX4_IB_QUERY_DEV_RESP_MASK_CORE_CLOCK_OFFSET;
587*4882a593Smuzhiyun resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
588*4882a593Smuzhiyun }
589*4882a593Smuzhiyun }
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun if (uhw->outlen >= resp.response_length +
592*4882a593Smuzhiyun sizeof(resp.max_inl_recv_sz)) {
593*4882a593Smuzhiyun resp.response_length += sizeof(resp.max_inl_recv_sz);
594*4882a593Smuzhiyun resp.max_inl_recv_sz = dev->dev->caps.max_rq_sg *
595*4882a593Smuzhiyun sizeof(struct mlx4_wqe_data_seg);
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun if (offsetofend(typeof(resp), rss_caps) <= uhw->outlen) {
599*4882a593Smuzhiyun if (props->rss_caps.supported_qpts) {
600*4882a593Smuzhiyun resp.rss_caps.rx_hash_function =
601*4882a593Smuzhiyun MLX4_IB_RX_HASH_FUNC_TOEPLITZ;
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun resp.rss_caps.rx_hash_fields_mask =
604*4882a593Smuzhiyun MLX4_IB_RX_HASH_SRC_IPV4 |
605*4882a593Smuzhiyun MLX4_IB_RX_HASH_DST_IPV4 |
606*4882a593Smuzhiyun MLX4_IB_RX_HASH_SRC_IPV6 |
607*4882a593Smuzhiyun MLX4_IB_RX_HASH_DST_IPV6 |
608*4882a593Smuzhiyun MLX4_IB_RX_HASH_SRC_PORT_TCP |
609*4882a593Smuzhiyun MLX4_IB_RX_HASH_DST_PORT_TCP |
610*4882a593Smuzhiyun MLX4_IB_RX_HASH_SRC_PORT_UDP |
611*4882a593Smuzhiyun MLX4_IB_RX_HASH_DST_PORT_UDP;
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun if (dev->dev->caps.tunnel_offload_mode ==
614*4882a593Smuzhiyun MLX4_TUNNEL_OFFLOAD_MODE_VXLAN)
615*4882a593Smuzhiyun resp.rss_caps.rx_hash_fields_mask |=
616*4882a593Smuzhiyun MLX4_IB_RX_HASH_INNER;
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun resp.response_length = offsetof(typeof(resp), rss_caps) +
619*4882a593Smuzhiyun sizeof(resp.rss_caps);
620*4882a593Smuzhiyun }
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun if (offsetofend(typeof(resp), tso_caps) <= uhw->outlen) {
623*4882a593Smuzhiyun if (dev->dev->caps.max_gso_sz &&
624*4882a593Smuzhiyun ((mlx4_ib_port_link_layer(ibdev, 1) ==
625*4882a593Smuzhiyun IB_LINK_LAYER_ETHERNET) ||
626*4882a593Smuzhiyun (mlx4_ib_port_link_layer(ibdev, 2) ==
627*4882a593Smuzhiyun IB_LINK_LAYER_ETHERNET))) {
628*4882a593Smuzhiyun resp.tso_caps.max_tso = dev->dev->caps.max_gso_sz;
629*4882a593Smuzhiyun resp.tso_caps.supported_qpts |=
630*4882a593Smuzhiyun 1 << IB_QPT_RAW_PACKET;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun resp.response_length = offsetof(typeof(resp), tso_caps) +
633*4882a593Smuzhiyun sizeof(resp.tso_caps);
634*4882a593Smuzhiyun }
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun if (uhw->outlen) {
637*4882a593Smuzhiyun err = ib_copy_to_udata(uhw, &resp, resp.response_length);
638*4882a593Smuzhiyun if (err)
639*4882a593Smuzhiyun goto out;
640*4882a593Smuzhiyun }
641*4882a593Smuzhiyun out:
642*4882a593Smuzhiyun kfree(in_mad);
643*4882a593Smuzhiyun kfree(out_mad);
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun return err;
646*4882a593Smuzhiyun }
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun static enum rdma_link_layer
mlx4_ib_port_link_layer(struct ib_device * device,u8 port_num)649*4882a593Smuzhiyun mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
650*4882a593Smuzhiyun {
651*4882a593Smuzhiyun struct mlx4_dev *dev = to_mdev(device)->dev;
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
654*4882a593Smuzhiyun IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
655*4882a593Smuzhiyun }
656*4882a593Smuzhiyun
ib_link_query_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props,int netw_view)657*4882a593Smuzhiyun static int ib_link_query_port(struct ib_device *ibdev, u8 port,
658*4882a593Smuzhiyun struct ib_port_attr *props, int netw_view)
659*4882a593Smuzhiyun {
660*4882a593Smuzhiyun struct ib_smp *in_mad = NULL;
661*4882a593Smuzhiyun struct ib_smp *out_mad = NULL;
662*4882a593Smuzhiyun int ext_active_speed;
663*4882a593Smuzhiyun int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
664*4882a593Smuzhiyun int err = -ENOMEM;
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
667*4882a593Smuzhiyun out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
668*4882a593Smuzhiyun if (!in_mad || !out_mad)
669*4882a593Smuzhiyun goto out;
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun init_query_mad(in_mad);
672*4882a593Smuzhiyun in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
673*4882a593Smuzhiyun in_mad->attr_mod = cpu_to_be32(port);
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
676*4882a593Smuzhiyun mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
677*4882a593Smuzhiyun
678*4882a593Smuzhiyun err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
679*4882a593Smuzhiyun in_mad, out_mad);
680*4882a593Smuzhiyun if (err)
681*4882a593Smuzhiyun goto out;
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun
684*4882a593Smuzhiyun props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
685*4882a593Smuzhiyun props->lmc = out_mad->data[34] & 0x7;
686*4882a593Smuzhiyun props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
687*4882a593Smuzhiyun props->sm_sl = out_mad->data[36] & 0xf;
688*4882a593Smuzhiyun props->state = out_mad->data[32] & 0xf;
689*4882a593Smuzhiyun props->phys_state = out_mad->data[33] >> 4;
690*4882a593Smuzhiyun props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
691*4882a593Smuzhiyun if (netw_view)
692*4882a593Smuzhiyun props->gid_tbl_len = out_mad->data[50];
693*4882a593Smuzhiyun else
694*4882a593Smuzhiyun props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
695*4882a593Smuzhiyun props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
696*4882a593Smuzhiyun props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
697*4882a593Smuzhiyun props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
698*4882a593Smuzhiyun props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
699*4882a593Smuzhiyun props->active_width = out_mad->data[31] & 0xf;
700*4882a593Smuzhiyun props->active_speed = out_mad->data[35] >> 4;
701*4882a593Smuzhiyun props->max_mtu = out_mad->data[41] & 0xf;
702*4882a593Smuzhiyun props->active_mtu = out_mad->data[36] >> 4;
703*4882a593Smuzhiyun props->subnet_timeout = out_mad->data[51] & 0x1f;
704*4882a593Smuzhiyun props->max_vl_num = out_mad->data[37] >> 4;
705*4882a593Smuzhiyun props->init_type_reply = out_mad->data[41] >> 4;
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun /* Check if extended speeds (EDR/FDR/...) are supported */
708*4882a593Smuzhiyun if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
709*4882a593Smuzhiyun ext_active_speed = out_mad->data[62] >> 4;
710*4882a593Smuzhiyun
711*4882a593Smuzhiyun switch (ext_active_speed) {
712*4882a593Smuzhiyun case 1:
713*4882a593Smuzhiyun props->active_speed = IB_SPEED_FDR;
714*4882a593Smuzhiyun break;
715*4882a593Smuzhiyun case 2:
716*4882a593Smuzhiyun props->active_speed = IB_SPEED_EDR;
717*4882a593Smuzhiyun break;
718*4882a593Smuzhiyun }
719*4882a593Smuzhiyun }
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun /* If reported active speed is QDR, check if is FDR-10 */
722*4882a593Smuzhiyun if (props->active_speed == IB_SPEED_QDR) {
723*4882a593Smuzhiyun init_query_mad(in_mad);
724*4882a593Smuzhiyun in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
725*4882a593Smuzhiyun in_mad->attr_mod = cpu_to_be32(port);
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
728*4882a593Smuzhiyun NULL, NULL, in_mad, out_mad);
729*4882a593Smuzhiyun if (err)
730*4882a593Smuzhiyun goto out;
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun /* Checking LinkSpeedActive for FDR-10 */
733*4882a593Smuzhiyun if (out_mad->data[15] & 0x1)
734*4882a593Smuzhiyun props->active_speed = IB_SPEED_FDR10;
735*4882a593Smuzhiyun }
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun /* Avoid wrong speed value returned by FW if the IB link is down. */
738*4882a593Smuzhiyun if (props->state == IB_PORT_DOWN)
739*4882a593Smuzhiyun props->active_speed = IB_SPEED_SDR;
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun out:
742*4882a593Smuzhiyun kfree(in_mad);
743*4882a593Smuzhiyun kfree(out_mad);
744*4882a593Smuzhiyun return err;
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun
state_to_phys_state(enum ib_port_state state)747*4882a593Smuzhiyun static u8 state_to_phys_state(enum ib_port_state state)
748*4882a593Smuzhiyun {
749*4882a593Smuzhiyun return state == IB_PORT_ACTIVE ?
750*4882a593Smuzhiyun IB_PORT_PHYS_STATE_LINK_UP : IB_PORT_PHYS_STATE_DISABLED;
751*4882a593Smuzhiyun }
752*4882a593Smuzhiyun
eth_link_query_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props)753*4882a593Smuzhiyun static int eth_link_query_port(struct ib_device *ibdev, u8 port,
754*4882a593Smuzhiyun struct ib_port_attr *props)
755*4882a593Smuzhiyun {
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun struct mlx4_ib_dev *mdev = to_mdev(ibdev);
758*4882a593Smuzhiyun struct mlx4_ib_iboe *iboe = &mdev->iboe;
759*4882a593Smuzhiyun struct net_device *ndev;
760*4882a593Smuzhiyun enum ib_mtu tmp;
761*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
762*4882a593Smuzhiyun int err = 0;
763*4882a593Smuzhiyun int is_bonded = mlx4_is_bonded(mdev->dev);
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
766*4882a593Smuzhiyun if (IS_ERR(mailbox))
767*4882a593Smuzhiyun return PTR_ERR(mailbox);
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
770*4882a593Smuzhiyun MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
771*4882a593Smuzhiyun MLX4_CMD_WRAPPED);
772*4882a593Smuzhiyun if (err)
773*4882a593Smuzhiyun goto out;
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ||
776*4882a593Smuzhiyun (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
777*4882a593Smuzhiyun IB_WIDTH_4X : IB_WIDTH_1X;
778*4882a593Smuzhiyun props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
779*4882a593Smuzhiyun IB_SPEED_FDR : IB_SPEED_QDR;
780*4882a593Smuzhiyun props->port_cap_flags = IB_PORT_CM_SUP;
781*4882a593Smuzhiyun props->ip_gids = true;
782*4882a593Smuzhiyun props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
783*4882a593Smuzhiyun props->max_msg_sz = mdev->dev->caps.max_msg_sz;
784*4882a593Smuzhiyun if (mdev->dev->caps.pkey_table_len[port])
785*4882a593Smuzhiyun props->pkey_tbl_len = 1;
786*4882a593Smuzhiyun props->max_mtu = IB_MTU_4096;
787*4882a593Smuzhiyun props->max_vl_num = 2;
788*4882a593Smuzhiyun props->state = IB_PORT_DOWN;
789*4882a593Smuzhiyun props->phys_state = state_to_phys_state(props->state);
790*4882a593Smuzhiyun props->active_mtu = IB_MTU_256;
791*4882a593Smuzhiyun spin_lock_bh(&iboe->lock);
792*4882a593Smuzhiyun ndev = iboe->netdevs[port - 1];
793*4882a593Smuzhiyun if (ndev && is_bonded) {
794*4882a593Smuzhiyun rcu_read_lock(); /* required to get upper dev */
795*4882a593Smuzhiyun ndev = netdev_master_upper_dev_get_rcu(ndev);
796*4882a593Smuzhiyun rcu_read_unlock();
797*4882a593Smuzhiyun }
798*4882a593Smuzhiyun if (!ndev)
799*4882a593Smuzhiyun goto out_unlock;
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun tmp = iboe_get_mtu(ndev->mtu);
802*4882a593Smuzhiyun props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
805*4882a593Smuzhiyun IB_PORT_ACTIVE : IB_PORT_DOWN;
806*4882a593Smuzhiyun props->phys_state = state_to_phys_state(props->state);
807*4882a593Smuzhiyun out_unlock:
808*4882a593Smuzhiyun spin_unlock_bh(&iboe->lock);
809*4882a593Smuzhiyun out:
810*4882a593Smuzhiyun mlx4_free_cmd_mailbox(mdev->dev, mailbox);
811*4882a593Smuzhiyun return err;
812*4882a593Smuzhiyun }
813*4882a593Smuzhiyun
__mlx4_ib_query_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props,int netw_view)814*4882a593Smuzhiyun int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
815*4882a593Smuzhiyun struct ib_port_attr *props, int netw_view)
816*4882a593Smuzhiyun {
817*4882a593Smuzhiyun int err;
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun /* props being zeroed by the caller, avoid zeroing it here */
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
822*4882a593Smuzhiyun ib_link_query_port(ibdev, port, props, netw_view) :
823*4882a593Smuzhiyun eth_link_query_port(ibdev, port, props);
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun return err;
826*4882a593Smuzhiyun }
827*4882a593Smuzhiyun
mlx4_ib_query_port(struct ib_device * ibdev,u8 port,struct ib_port_attr * props)828*4882a593Smuzhiyun static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
829*4882a593Smuzhiyun struct ib_port_attr *props)
830*4882a593Smuzhiyun {
831*4882a593Smuzhiyun /* returns host view */
832*4882a593Smuzhiyun return __mlx4_ib_query_port(ibdev, port, props, 0);
833*4882a593Smuzhiyun }
834*4882a593Smuzhiyun
__mlx4_ib_query_gid(struct ib_device * ibdev,u8 port,int index,union ib_gid * gid,int netw_view)835*4882a593Smuzhiyun int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
836*4882a593Smuzhiyun union ib_gid *gid, int netw_view)
837*4882a593Smuzhiyun {
838*4882a593Smuzhiyun struct ib_smp *in_mad = NULL;
839*4882a593Smuzhiyun struct ib_smp *out_mad = NULL;
840*4882a593Smuzhiyun int err = -ENOMEM;
841*4882a593Smuzhiyun struct mlx4_ib_dev *dev = to_mdev(ibdev);
842*4882a593Smuzhiyun int clear = 0;
843*4882a593Smuzhiyun int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
846*4882a593Smuzhiyun out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
847*4882a593Smuzhiyun if (!in_mad || !out_mad)
848*4882a593Smuzhiyun goto out;
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun init_query_mad(in_mad);
851*4882a593Smuzhiyun in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
852*4882a593Smuzhiyun in_mad->attr_mod = cpu_to_be32(port);
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun if (mlx4_is_mfunc(dev->dev) && netw_view)
855*4882a593Smuzhiyun mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
858*4882a593Smuzhiyun if (err)
859*4882a593Smuzhiyun goto out;
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun memcpy(gid->raw, out_mad->data + 8, 8);
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun if (mlx4_is_mfunc(dev->dev) && !netw_view) {
864*4882a593Smuzhiyun if (index) {
865*4882a593Smuzhiyun /* For any index > 0, return the null guid */
866*4882a593Smuzhiyun err = 0;
867*4882a593Smuzhiyun clear = 1;
868*4882a593Smuzhiyun goto out;
869*4882a593Smuzhiyun }
870*4882a593Smuzhiyun }
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun init_query_mad(in_mad);
873*4882a593Smuzhiyun in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
874*4882a593Smuzhiyun in_mad->attr_mod = cpu_to_be32(index / 8);
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
877*4882a593Smuzhiyun NULL, NULL, in_mad, out_mad);
878*4882a593Smuzhiyun if (err)
879*4882a593Smuzhiyun goto out;
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun out:
884*4882a593Smuzhiyun if (clear)
885*4882a593Smuzhiyun memset(gid->raw + 8, 0, 8);
886*4882a593Smuzhiyun kfree(in_mad);
887*4882a593Smuzhiyun kfree(out_mad);
888*4882a593Smuzhiyun return err;
889*4882a593Smuzhiyun }
890*4882a593Smuzhiyun
mlx4_ib_query_gid(struct ib_device * ibdev,u8 port,int index,union ib_gid * gid)891*4882a593Smuzhiyun static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
892*4882a593Smuzhiyun union ib_gid *gid)
893*4882a593Smuzhiyun {
894*4882a593Smuzhiyun if (rdma_protocol_ib(ibdev, port))
895*4882a593Smuzhiyun return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
896*4882a593Smuzhiyun return 0;
897*4882a593Smuzhiyun }
898*4882a593Smuzhiyun
mlx4_ib_query_sl2vl(struct ib_device * ibdev,u8 port,u64 * sl2vl_tbl)899*4882a593Smuzhiyun static int mlx4_ib_query_sl2vl(struct ib_device *ibdev, u8 port, u64 *sl2vl_tbl)
900*4882a593Smuzhiyun {
901*4882a593Smuzhiyun union sl2vl_tbl_to_u64 sl2vl64;
902*4882a593Smuzhiyun struct ib_smp *in_mad = NULL;
903*4882a593Smuzhiyun struct ib_smp *out_mad = NULL;
904*4882a593Smuzhiyun int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
905*4882a593Smuzhiyun int err = -ENOMEM;
906*4882a593Smuzhiyun int jj;
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun if (mlx4_is_slave(to_mdev(ibdev)->dev)) {
909*4882a593Smuzhiyun *sl2vl_tbl = 0;
910*4882a593Smuzhiyun return 0;
911*4882a593Smuzhiyun }
912*4882a593Smuzhiyun
913*4882a593Smuzhiyun in_mad = kzalloc(sizeof(*in_mad), GFP_KERNEL);
914*4882a593Smuzhiyun out_mad = kmalloc(sizeof(*out_mad), GFP_KERNEL);
915*4882a593Smuzhiyun if (!in_mad || !out_mad)
916*4882a593Smuzhiyun goto out;
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun init_query_mad(in_mad);
919*4882a593Smuzhiyun in_mad->attr_id = IB_SMP_ATTR_SL_TO_VL_TABLE;
920*4882a593Smuzhiyun in_mad->attr_mod = 0;
921*4882a593Smuzhiyun
922*4882a593Smuzhiyun if (mlx4_is_mfunc(to_mdev(ibdev)->dev))
923*4882a593Smuzhiyun mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
926*4882a593Smuzhiyun in_mad, out_mad);
927*4882a593Smuzhiyun if (err)
928*4882a593Smuzhiyun goto out;
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun for (jj = 0; jj < 8; jj++)
931*4882a593Smuzhiyun sl2vl64.sl8[jj] = ((struct ib_smp *)out_mad)->data[jj];
932*4882a593Smuzhiyun *sl2vl_tbl = sl2vl64.sl64;
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun out:
935*4882a593Smuzhiyun kfree(in_mad);
936*4882a593Smuzhiyun kfree(out_mad);
937*4882a593Smuzhiyun return err;
938*4882a593Smuzhiyun }
939*4882a593Smuzhiyun
mlx4_init_sl2vl_tbl(struct mlx4_ib_dev * mdev)940*4882a593Smuzhiyun static void mlx4_init_sl2vl_tbl(struct mlx4_ib_dev *mdev)
941*4882a593Smuzhiyun {
942*4882a593Smuzhiyun u64 sl2vl;
943*4882a593Smuzhiyun int i;
944*4882a593Smuzhiyun int err;
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun for (i = 1; i <= mdev->dev->caps.num_ports; i++) {
947*4882a593Smuzhiyun if (mdev->dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
948*4882a593Smuzhiyun continue;
949*4882a593Smuzhiyun err = mlx4_ib_query_sl2vl(&mdev->ib_dev, i, &sl2vl);
950*4882a593Smuzhiyun if (err) {
951*4882a593Smuzhiyun pr_err("Unable to get default sl to vl mapping for port %d. Using all zeroes (%d)\n",
952*4882a593Smuzhiyun i, err);
953*4882a593Smuzhiyun sl2vl = 0;
954*4882a593Smuzhiyun }
955*4882a593Smuzhiyun atomic64_set(&mdev->sl2vl[i - 1], sl2vl);
956*4882a593Smuzhiyun }
957*4882a593Smuzhiyun }
958*4882a593Smuzhiyun
__mlx4_ib_query_pkey(struct ib_device * ibdev,u8 port,u16 index,u16 * pkey,int netw_view)959*4882a593Smuzhiyun int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
960*4882a593Smuzhiyun u16 *pkey, int netw_view)
961*4882a593Smuzhiyun {
962*4882a593Smuzhiyun struct ib_smp *in_mad = NULL;
963*4882a593Smuzhiyun struct ib_smp *out_mad = NULL;
964*4882a593Smuzhiyun int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
965*4882a593Smuzhiyun int err = -ENOMEM;
966*4882a593Smuzhiyun
967*4882a593Smuzhiyun in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
968*4882a593Smuzhiyun out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
969*4882a593Smuzhiyun if (!in_mad || !out_mad)
970*4882a593Smuzhiyun goto out;
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun init_query_mad(in_mad);
973*4882a593Smuzhiyun in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
974*4882a593Smuzhiyun in_mad->attr_mod = cpu_to_be32(index / 32);
975*4882a593Smuzhiyun
976*4882a593Smuzhiyun if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
977*4882a593Smuzhiyun mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
980*4882a593Smuzhiyun in_mad, out_mad);
981*4882a593Smuzhiyun if (err)
982*4882a593Smuzhiyun goto out;
983*4882a593Smuzhiyun
984*4882a593Smuzhiyun *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
985*4882a593Smuzhiyun
986*4882a593Smuzhiyun out:
987*4882a593Smuzhiyun kfree(in_mad);
988*4882a593Smuzhiyun kfree(out_mad);
989*4882a593Smuzhiyun return err;
990*4882a593Smuzhiyun }
991*4882a593Smuzhiyun
mlx4_ib_query_pkey(struct ib_device * ibdev,u8 port,u16 index,u16 * pkey)992*4882a593Smuzhiyun static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
993*4882a593Smuzhiyun {
994*4882a593Smuzhiyun return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
995*4882a593Smuzhiyun }
996*4882a593Smuzhiyun
mlx4_ib_modify_device(struct ib_device * ibdev,int mask,struct ib_device_modify * props)997*4882a593Smuzhiyun static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
998*4882a593Smuzhiyun struct ib_device_modify *props)
999*4882a593Smuzhiyun {
1000*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
1001*4882a593Smuzhiyun unsigned long flags;
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1004*4882a593Smuzhiyun return -EOPNOTSUPP;
1005*4882a593Smuzhiyun
1006*4882a593Smuzhiyun if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1007*4882a593Smuzhiyun return 0;
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun if (mlx4_is_slave(to_mdev(ibdev)->dev))
1010*4882a593Smuzhiyun return -EOPNOTSUPP;
1011*4882a593Smuzhiyun
1012*4882a593Smuzhiyun spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
1013*4882a593Smuzhiyun memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1014*4882a593Smuzhiyun spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun /*
1017*4882a593Smuzhiyun * If possible, pass node desc to FW, so it can generate
1018*4882a593Smuzhiyun * a 144 trap. If cmd fails, just ignore.
1019*4882a593Smuzhiyun */
1020*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
1021*4882a593Smuzhiyun if (IS_ERR(mailbox))
1022*4882a593Smuzhiyun return 0;
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun memcpy(mailbox->buf, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1025*4882a593Smuzhiyun mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
1026*4882a593Smuzhiyun MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
1027*4882a593Smuzhiyun
1028*4882a593Smuzhiyun mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun return 0;
1031*4882a593Smuzhiyun }
1032*4882a593Smuzhiyun
mlx4_ib_SET_PORT(struct mlx4_ib_dev * dev,u8 port,int reset_qkey_viols,u32 cap_mask)1033*4882a593Smuzhiyun static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
1034*4882a593Smuzhiyun u32 cap_mask)
1035*4882a593Smuzhiyun {
1036*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
1037*4882a593Smuzhiyun int err;
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
1040*4882a593Smuzhiyun if (IS_ERR(mailbox))
1041*4882a593Smuzhiyun return PTR_ERR(mailbox);
1042*4882a593Smuzhiyun
1043*4882a593Smuzhiyun if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
1044*4882a593Smuzhiyun *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
1045*4882a593Smuzhiyun ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
1046*4882a593Smuzhiyun } else {
1047*4882a593Smuzhiyun ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
1048*4882a593Smuzhiyun ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
1049*4882a593Smuzhiyun }
1050*4882a593Smuzhiyun
1051*4882a593Smuzhiyun err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
1052*4882a593Smuzhiyun MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
1053*4882a593Smuzhiyun MLX4_CMD_WRAPPED);
1054*4882a593Smuzhiyun
1055*4882a593Smuzhiyun mlx4_free_cmd_mailbox(dev->dev, mailbox);
1056*4882a593Smuzhiyun return err;
1057*4882a593Smuzhiyun }
1058*4882a593Smuzhiyun
mlx4_ib_modify_port(struct ib_device * ibdev,u8 port,int mask,struct ib_port_modify * props)1059*4882a593Smuzhiyun static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1060*4882a593Smuzhiyun struct ib_port_modify *props)
1061*4882a593Smuzhiyun {
1062*4882a593Smuzhiyun struct mlx4_ib_dev *mdev = to_mdev(ibdev);
1063*4882a593Smuzhiyun u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
1064*4882a593Smuzhiyun struct ib_port_attr attr;
1065*4882a593Smuzhiyun u32 cap_mask;
1066*4882a593Smuzhiyun int err;
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun /* return OK if this is RoCE. CM calls ib_modify_port() regardless
1069*4882a593Smuzhiyun * of whether port link layer is ETH or IB. For ETH ports, qkey
1070*4882a593Smuzhiyun * violations and port capabilities are not meaningful.
1071*4882a593Smuzhiyun */
1072*4882a593Smuzhiyun if (is_eth)
1073*4882a593Smuzhiyun return 0;
1074*4882a593Smuzhiyun
1075*4882a593Smuzhiyun mutex_lock(&mdev->cap_mask_mutex);
1076*4882a593Smuzhiyun
1077*4882a593Smuzhiyun err = ib_query_port(ibdev, port, &attr);
1078*4882a593Smuzhiyun if (err)
1079*4882a593Smuzhiyun goto out;
1080*4882a593Smuzhiyun
1081*4882a593Smuzhiyun cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
1082*4882a593Smuzhiyun ~props->clr_port_cap_mask;
1083*4882a593Smuzhiyun
1084*4882a593Smuzhiyun err = mlx4_ib_SET_PORT(mdev, port,
1085*4882a593Smuzhiyun !!(mask & IB_PORT_RESET_QKEY_CNTR),
1086*4882a593Smuzhiyun cap_mask);
1087*4882a593Smuzhiyun
1088*4882a593Smuzhiyun out:
1089*4882a593Smuzhiyun mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
1090*4882a593Smuzhiyun return err;
1091*4882a593Smuzhiyun }
1092*4882a593Smuzhiyun
mlx4_ib_alloc_ucontext(struct ib_ucontext * uctx,struct ib_udata * udata)1093*4882a593Smuzhiyun static int mlx4_ib_alloc_ucontext(struct ib_ucontext *uctx,
1094*4882a593Smuzhiyun struct ib_udata *udata)
1095*4882a593Smuzhiyun {
1096*4882a593Smuzhiyun struct ib_device *ibdev = uctx->device;
1097*4882a593Smuzhiyun struct mlx4_ib_dev *dev = to_mdev(ibdev);
1098*4882a593Smuzhiyun struct mlx4_ib_ucontext *context = to_mucontext(uctx);
1099*4882a593Smuzhiyun struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
1100*4882a593Smuzhiyun struct mlx4_ib_alloc_ucontext_resp resp;
1101*4882a593Smuzhiyun int err;
1102*4882a593Smuzhiyun
1103*4882a593Smuzhiyun if (!dev->ib_active)
1104*4882a593Smuzhiyun return -EAGAIN;
1105*4882a593Smuzhiyun
1106*4882a593Smuzhiyun if (ibdev->ops.uverbs_abi_ver ==
1107*4882a593Smuzhiyun MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
1108*4882a593Smuzhiyun resp_v3.qp_tab_size = dev->dev->caps.num_qps;
1109*4882a593Smuzhiyun resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
1110*4882a593Smuzhiyun resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1111*4882a593Smuzhiyun } else {
1112*4882a593Smuzhiyun resp.dev_caps = dev->dev->caps.userspace_caps;
1113*4882a593Smuzhiyun resp.qp_tab_size = dev->dev->caps.num_qps;
1114*4882a593Smuzhiyun resp.bf_reg_size = dev->dev->caps.bf_reg_size;
1115*4882a593Smuzhiyun resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
1116*4882a593Smuzhiyun resp.cqe_size = dev->dev->caps.cqe_size;
1117*4882a593Smuzhiyun }
1118*4882a593Smuzhiyun
1119*4882a593Smuzhiyun err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
1120*4882a593Smuzhiyun if (err)
1121*4882a593Smuzhiyun return err;
1122*4882a593Smuzhiyun
1123*4882a593Smuzhiyun INIT_LIST_HEAD(&context->db_page_list);
1124*4882a593Smuzhiyun mutex_init(&context->db_page_mutex);
1125*4882a593Smuzhiyun
1126*4882a593Smuzhiyun INIT_LIST_HEAD(&context->wqn_ranges_list);
1127*4882a593Smuzhiyun mutex_init(&context->wqn_ranges_mutex);
1128*4882a593Smuzhiyun
1129*4882a593Smuzhiyun if (ibdev->ops.uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
1130*4882a593Smuzhiyun err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
1131*4882a593Smuzhiyun else
1132*4882a593Smuzhiyun err = ib_copy_to_udata(udata, &resp, sizeof(resp));
1133*4882a593Smuzhiyun
1134*4882a593Smuzhiyun if (err) {
1135*4882a593Smuzhiyun mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
1136*4882a593Smuzhiyun return -EFAULT;
1137*4882a593Smuzhiyun }
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun return err;
1140*4882a593Smuzhiyun }
1141*4882a593Smuzhiyun
mlx4_ib_dealloc_ucontext(struct ib_ucontext * ibcontext)1142*4882a593Smuzhiyun static void mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1143*4882a593Smuzhiyun {
1144*4882a593Smuzhiyun struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
1147*4882a593Smuzhiyun }
1148*4882a593Smuzhiyun
mlx4_ib_disassociate_ucontext(struct ib_ucontext * ibcontext)1149*4882a593Smuzhiyun static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1150*4882a593Smuzhiyun {
1151*4882a593Smuzhiyun }
1152*4882a593Smuzhiyun
mlx4_ib_mmap(struct ib_ucontext * context,struct vm_area_struct * vma)1153*4882a593Smuzhiyun static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
1154*4882a593Smuzhiyun {
1155*4882a593Smuzhiyun struct mlx4_ib_dev *dev = to_mdev(context->device);
1156*4882a593Smuzhiyun
1157*4882a593Smuzhiyun switch (vma->vm_pgoff) {
1158*4882a593Smuzhiyun case 0:
1159*4882a593Smuzhiyun return rdma_user_mmap_io(context, vma,
1160*4882a593Smuzhiyun to_mucontext(context)->uar.pfn,
1161*4882a593Smuzhiyun PAGE_SIZE,
1162*4882a593Smuzhiyun pgprot_noncached(vma->vm_page_prot),
1163*4882a593Smuzhiyun NULL);
1164*4882a593Smuzhiyun
1165*4882a593Smuzhiyun case 1:
1166*4882a593Smuzhiyun if (dev->dev->caps.bf_reg_size == 0)
1167*4882a593Smuzhiyun return -EINVAL;
1168*4882a593Smuzhiyun return rdma_user_mmap_io(
1169*4882a593Smuzhiyun context, vma,
1170*4882a593Smuzhiyun to_mucontext(context)->uar.pfn +
1171*4882a593Smuzhiyun dev->dev->caps.num_uars,
1172*4882a593Smuzhiyun PAGE_SIZE, pgprot_writecombine(vma->vm_page_prot),
1173*4882a593Smuzhiyun NULL);
1174*4882a593Smuzhiyun
1175*4882a593Smuzhiyun case 3: {
1176*4882a593Smuzhiyun struct mlx4_clock_params params;
1177*4882a593Smuzhiyun int ret;
1178*4882a593Smuzhiyun
1179*4882a593Smuzhiyun ret = mlx4_get_internal_clock_params(dev->dev, ¶ms);
1180*4882a593Smuzhiyun if (ret)
1181*4882a593Smuzhiyun return ret;
1182*4882a593Smuzhiyun
1183*4882a593Smuzhiyun return rdma_user_mmap_io(
1184*4882a593Smuzhiyun context, vma,
1185*4882a593Smuzhiyun (pci_resource_start(dev->dev->persist->pdev,
1186*4882a593Smuzhiyun params.bar) +
1187*4882a593Smuzhiyun params.offset) >>
1188*4882a593Smuzhiyun PAGE_SHIFT,
1189*4882a593Smuzhiyun PAGE_SIZE, pgprot_noncached(vma->vm_page_prot),
1190*4882a593Smuzhiyun NULL);
1191*4882a593Smuzhiyun }
1192*4882a593Smuzhiyun
1193*4882a593Smuzhiyun default:
1194*4882a593Smuzhiyun return -EINVAL;
1195*4882a593Smuzhiyun }
1196*4882a593Smuzhiyun }
1197*4882a593Smuzhiyun
mlx4_ib_alloc_pd(struct ib_pd * ibpd,struct ib_udata * udata)1198*4882a593Smuzhiyun static int mlx4_ib_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata)
1199*4882a593Smuzhiyun {
1200*4882a593Smuzhiyun struct mlx4_ib_pd *pd = to_mpd(ibpd);
1201*4882a593Smuzhiyun struct ib_device *ibdev = ibpd->device;
1202*4882a593Smuzhiyun int err;
1203*4882a593Smuzhiyun
1204*4882a593Smuzhiyun err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
1205*4882a593Smuzhiyun if (err)
1206*4882a593Smuzhiyun return err;
1207*4882a593Smuzhiyun
1208*4882a593Smuzhiyun if (udata && ib_copy_to_udata(udata, &pd->pdn, sizeof(__u32))) {
1209*4882a593Smuzhiyun mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
1210*4882a593Smuzhiyun return -EFAULT;
1211*4882a593Smuzhiyun }
1212*4882a593Smuzhiyun return 0;
1213*4882a593Smuzhiyun }
1214*4882a593Smuzhiyun
mlx4_ib_dealloc_pd(struct ib_pd * pd,struct ib_udata * udata)1215*4882a593Smuzhiyun static int mlx4_ib_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata)
1216*4882a593Smuzhiyun {
1217*4882a593Smuzhiyun mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
1218*4882a593Smuzhiyun return 0;
1219*4882a593Smuzhiyun }
1220*4882a593Smuzhiyun
mlx4_ib_alloc_xrcd(struct ib_xrcd * ibxrcd,struct ib_udata * udata)1221*4882a593Smuzhiyun static int mlx4_ib_alloc_xrcd(struct ib_xrcd *ibxrcd, struct ib_udata *udata)
1222*4882a593Smuzhiyun {
1223*4882a593Smuzhiyun struct mlx4_ib_dev *dev = to_mdev(ibxrcd->device);
1224*4882a593Smuzhiyun struct mlx4_ib_xrcd *xrcd = to_mxrcd(ibxrcd);
1225*4882a593Smuzhiyun struct ib_cq_init_attr cq_attr = {};
1226*4882a593Smuzhiyun int err;
1227*4882a593Smuzhiyun
1228*4882a593Smuzhiyun if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1229*4882a593Smuzhiyun return -EOPNOTSUPP;
1230*4882a593Smuzhiyun
1231*4882a593Smuzhiyun err = mlx4_xrcd_alloc(dev->dev, &xrcd->xrcdn);
1232*4882a593Smuzhiyun if (err)
1233*4882a593Smuzhiyun return err;
1234*4882a593Smuzhiyun
1235*4882a593Smuzhiyun xrcd->pd = ib_alloc_pd(ibxrcd->device, 0);
1236*4882a593Smuzhiyun if (IS_ERR(xrcd->pd)) {
1237*4882a593Smuzhiyun err = PTR_ERR(xrcd->pd);
1238*4882a593Smuzhiyun goto err2;
1239*4882a593Smuzhiyun }
1240*4882a593Smuzhiyun
1241*4882a593Smuzhiyun cq_attr.cqe = 1;
1242*4882a593Smuzhiyun xrcd->cq = ib_create_cq(ibxrcd->device, NULL, NULL, xrcd, &cq_attr);
1243*4882a593Smuzhiyun if (IS_ERR(xrcd->cq)) {
1244*4882a593Smuzhiyun err = PTR_ERR(xrcd->cq);
1245*4882a593Smuzhiyun goto err3;
1246*4882a593Smuzhiyun }
1247*4882a593Smuzhiyun
1248*4882a593Smuzhiyun return 0;
1249*4882a593Smuzhiyun
1250*4882a593Smuzhiyun err3:
1251*4882a593Smuzhiyun ib_dealloc_pd(xrcd->pd);
1252*4882a593Smuzhiyun err2:
1253*4882a593Smuzhiyun mlx4_xrcd_free(dev->dev, xrcd->xrcdn);
1254*4882a593Smuzhiyun return err;
1255*4882a593Smuzhiyun }
1256*4882a593Smuzhiyun
mlx4_ib_dealloc_xrcd(struct ib_xrcd * xrcd,struct ib_udata * udata)1257*4882a593Smuzhiyun static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata)
1258*4882a593Smuzhiyun {
1259*4882a593Smuzhiyun ib_destroy_cq(to_mxrcd(xrcd)->cq);
1260*4882a593Smuzhiyun ib_dealloc_pd(to_mxrcd(xrcd)->pd);
1261*4882a593Smuzhiyun mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
1262*4882a593Smuzhiyun return 0;
1263*4882a593Smuzhiyun }
1264*4882a593Smuzhiyun
add_gid_entry(struct ib_qp * ibqp,union ib_gid * gid)1265*4882a593Smuzhiyun static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
1266*4882a593Smuzhiyun {
1267*4882a593Smuzhiyun struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1268*4882a593Smuzhiyun struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1269*4882a593Smuzhiyun struct mlx4_ib_gid_entry *ge;
1270*4882a593Smuzhiyun
1271*4882a593Smuzhiyun ge = kzalloc(sizeof *ge, GFP_KERNEL);
1272*4882a593Smuzhiyun if (!ge)
1273*4882a593Smuzhiyun return -ENOMEM;
1274*4882a593Smuzhiyun
1275*4882a593Smuzhiyun ge->gid = *gid;
1276*4882a593Smuzhiyun if (mlx4_ib_add_mc(mdev, mqp, gid)) {
1277*4882a593Smuzhiyun ge->port = mqp->port;
1278*4882a593Smuzhiyun ge->added = 1;
1279*4882a593Smuzhiyun }
1280*4882a593Smuzhiyun
1281*4882a593Smuzhiyun mutex_lock(&mqp->mutex);
1282*4882a593Smuzhiyun list_add_tail(&ge->list, &mqp->gid_list);
1283*4882a593Smuzhiyun mutex_unlock(&mqp->mutex);
1284*4882a593Smuzhiyun
1285*4882a593Smuzhiyun return 0;
1286*4882a593Smuzhiyun }
1287*4882a593Smuzhiyun
mlx4_ib_delete_counters_table(struct mlx4_ib_dev * ibdev,struct mlx4_ib_counters * ctr_table)1288*4882a593Smuzhiyun static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
1289*4882a593Smuzhiyun struct mlx4_ib_counters *ctr_table)
1290*4882a593Smuzhiyun {
1291*4882a593Smuzhiyun struct counter_index *counter, *tmp_count;
1292*4882a593Smuzhiyun
1293*4882a593Smuzhiyun mutex_lock(&ctr_table->mutex);
1294*4882a593Smuzhiyun list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
1295*4882a593Smuzhiyun list) {
1296*4882a593Smuzhiyun if (counter->allocated)
1297*4882a593Smuzhiyun mlx4_counter_free(ibdev->dev, counter->index);
1298*4882a593Smuzhiyun list_del(&counter->list);
1299*4882a593Smuzhiyun kfree(counter);
1300*4882a593Smuzhiyun }
1301*4882a593Smuzhiyun mutex_unlock(&ctr_table->mutex);
1302*4882a593Smuzhiyun }
1303*4882a593Smuzhiyun
mlx4_ib_add_mc(struct mlx4_ib_dev * mdev,struct mlx4_ib_qp * mqp,union ib_gid * gid)1304*4882a593Smuzhiyun int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
1305*4882a593Smuzhiyun union ib_gid *gid)
1306*4882a593Smuzhiyun {
1307*4882a593Smuzhiyun struct net_device *ndev;
1308*4882a593Smuzhiyun int ret = 0;
1309*4882a593Smuzhiyun
1310*4882a593Smuzhiyun if (!mqp->port)
1311*4882a593Smuzhiyun return 0;
1312*4882a593Smuzhiyun
1313*4882a593Smuzhiyun spin_lock_bh(&mdev->iboe.lock);
1314*4882a593Smuzhiyun ndev = mdev->iboe.netdevs[mqp->port - 1];
1315*4882a593Smuzhiyun if (ndev)
1316*4882a593Smuzhiyun dev_hold(ndev);
1317*4882a593Smuzhiyun spin_unlock_bh(&mdev->iboe.lock);
1318*4882a593Smuzhiyun
1319*4882a593Smuzhiyun if (ndev) {
1320*4882a593Smuzhiyun ret = 1;
1321*4882a593Smuzhiyun dev_put(ndev);
1322*4882a593Smuzhiyun }
1323*4882a593Smuzhiyun
1324*4882a593Smuzhiyun return ret;
1325*4882a593Smuzhiyun }
1326*4882a593Smuzhiyun
1327*4882a593Smuzhiyun struct mlx4_ib_steering {
1328*4882a593Smuzhiyun struct list_head list;
1329*4882a593Smuzhiyun struct mlx4_flow_reg_id reg_id;
1330*4882a593Smuzhiyun union ib_gid gid;
1331*4882a593Smuzhiyun };
1332*4882a593Smuzhiyun
1333*4882a593Smuzhiyun #define LAST_ETH_FIELD vlan_tag
1334*4882a593Smuzhiyun #define LAST_IB_FIELD sl
1335*4882a593Smuzhiyun #define LAST_IPV4_FIELD dst_ip
1336*4882a593Smuzhiyun #define LAST_TCP_UDP_FIELD src_port
1337*4882a593Smuzhiyun
1338*4882a593Smuzhiyun /* Field is the last supported field */
1339*4882a593Smuzhiyun #define FIELDS_NOT_SUPPORTED(filter, field)\
1340*4882a593Smuzhiyun memchr_inv((void *)&filter.field +\
1341*4882a593Smuzhiyun sizeof(filter.field), 0,\
1342*4882a593Smuzhiyun sizeof(filter) -\
1343*4882a593Smuzhiyun offsetof(typeof(filter), field) -\
1344*4882a593Smuzhiyun sizeof(filter.field))
1345*4882a593Smuzhiyun
parse_flow_attr(struct mlx4_dev * dev,u32 qp_num,union ib_flow_spec * ib_spec,struct _rule_hw * mlx4_spec)1346*4882a593Smuzhiyun static int parse_flow_attr(struct mlx4_dev *dev,
1347*4882a593Smuzhiyun u32 qp_num,
1348*4882a593Smuzhiyun union ib_flow_spec *ib_spec,
1349*4882a593Smuzhiyun struct _rule_hw *mlx4_spec)
1350*4882a593Smuzhiyun {
1351*4882a593Smuzhiyun enum mlx4_net_trans_rule_id type;
1352*4882a593Smuzhiyun
1353*4882a593Smuzhiyun switch (ib_spec->type) {
1354*4882a593Smuzhiyun case IB_FLOW_SPEC_ETH:
1355*4882a593Smuzhiyun if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1356*4882a593Smuzhiyun return -ENOTSUPP;
1357*4882a593Smuzhiyun
1358*4882a593Smuzhiyun type = MLX4_NET_TRANS_RULE_ID_ETH;
1359*4882a593Smuzhiyun memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
1360*4882a593Smuzhiyun ETH_ALEN);
1361*4882a593Smuzhiyun memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
1362*4882a593Smuzhiyun ETH_ALEN);
1363*4882a593Smuzhiyun mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
1364*4882a593Smuzhiyun mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
1365*4882a593Smuzhiyun break;
1366*4882a593Smuzhiyun case IB_FLOW_SPEC_IB:
1367*4882a593Smuzhiyun if (FIELDS_NOT_SUPPORTED(ib_spec->ib.mask, LAST_IB_FIELD))
1368*4882a593Smuzhiyun return -ENOTSUPP;
1369*4882a593Smuzhiyun
1370*4882a593Smuzhiyun type = MLX4_NET_TRANS_RULE_ID_IB;
1371*4882a593Smuzhiyun mlx4_spec->ib.l3_qpn =
1372*4882a593Smuzhiyun cpu_to_be32(qp_num);
1373*4882a593Smuzhiyun mlx4_spec->ib.qpn_mask =
1374*4882a593Smuzhiyun cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
1375*4882a593Smuzhiyun break;
1376*4882a593Smuzhiyun
1377*4882a593Smuzhiyun
1378*4882a593Smuzhiyun case IB_FLOW_SPEC_IPV4:
1379*4882a593Smuzhiyun if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1380*4882a593Smuzhiyun return -ENOTSUPP;
1381*4882a593Smuzhiyun
1382*4882a593Smuzhiyun type = MLX4_NET_TRANS_RULE_ID_IPV4;
1383*4882a593Smuzhiyun mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
1384*4882a593Smuzhiyun mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
1385*4882a593Smuzhiyun mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
1386*4882a593Smuzhiyun mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
1387*4882a593Smuzhiyun break;
1388*4882a593Smuzhiyun
1389*4882a593Smuzhiyun case IB_FLOW_SPEC_TCP:
1390*4882a593Smuzhiyun case IB_FLOW_SPEC_UDP:
1391*4882a593Smuzhiyun if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, LAST_TCP_UDP_FIELD))
1392*4882a593Smuzhiyun return -ENOTSUPP;
1393*4882a593Smuzhiyun
1394*4882a593Smuzhiyun type = ib_spec->type == IB_FLOW_SPEC_TCP ?
1395*4882a593Smuzhiyun MLX4_NET_TRANS_RULE_ID_TCP :
1396*4882a593Smuzhiyun MLX4_NET_TRANS_RULE_ID_UDP;
1397*4882a593Smuzhiyun mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
1398*4882a593Smuzhiyun mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
1399*4882a593Smuzhiyun mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
1400*4882a593Smuzhiyun mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
1401*4882a593Smuzhiyun break;
1402*4882a593Smuzhiyun
1403*4882a593Smuzhiyun default:
1404*4882a593Smuzhiyun return -EINVAL;
1405*4882a593Smuzhiyun }
1406*4882a593Smuzhiyun if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
1407*4882a593Smuzhiyun mlx4_hw_rule_sz(dev, type) < 0)
1408*4882a593Smuzhiyun return -EINVAL;
1409*4882a593Smuzhiyun mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
1410*4882a593Smuzhiyun mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
1411*4882a593Smuzhiyun return mlx4_hw_rule_sz(dev, type);
1412*4882a593Smuzhiyun }
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun struct default_rules {
1415*4882a593Smuzhiyun __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1416*4882a593Smuzhiyun __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
1417*4882a593Smuzhiyun __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
1418*4882a593Smuzhiyun __u8 link_layer;
1419*4882a593Smuzhiyun };
1420*4882a593Smuzhiyun static const struct default_rules default_table[] = {
1421*4882a593Smuzhiyun {
1422*4882a593Smuzhiyun .mandatory_fields = {IB_FLOW_SPEC_IPV4},
1423*4882a593Smuzhiyun .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
1424*4882a593Smuzhiyun .rules_create_list = {IB_FLOW_SPEC_IB},
1425*4882a593Smuzhiyun .link_layer = IB_LINK_LAYER_INFINIBAND
1426*4882a593Smuzhiyun }
1427*4882a593Smuzhiyun };
1428*4882a593Smuzhiyun
__mlx4_ib_default_rules_match(struct ib_qp * qp,struct ib_flow_attr * flow_attr)1429*4882a593Smuzhiyun static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
1430*4882a593Smuzhiyun struct ib_flow_attr *flow_attr)
1431*4882a593Smuzhiyun {
1432*4882a593Smuzhiyun int i, j, k;
1433*4882a593Smuzhiyun void *ib_flow;
1434*4882a593Smuzhiyun const struct default_rules *pdefault_rules = default_table;
1435*4882a593Smuzhiyun u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
1436*4882a593Smuzhiyun
1437*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
1438*4882a593Smuzhiyun __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
1439*4882a593Smuzhiyun memset(&field_types, 0, sizeof(field_types));
1440*4882a593Smuzhiyun
1441*4882a593Smuzhiyun if (link_layer != pdefault_rules->link_layer)
1442*4882a593Smuzhiyun continue;
1443*4882a593Smuzhiyun
1444*4882a593Smuzhiyun ib_flow = flow_attr + 1;
1445*4882a593Smuzhiyun /* we assume the specs are sorted */
1446*4882a593Smuzhiyun for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
1447*4882a593Smuzhiyun j < flow_attr->num_of_specs; k++) {
1448*4882a593Smuzhiyun union ib_flow_spec *current_flow =
1449*4882a593Smuzhiyun (union ib_flow_spec *)ib_flow;
1450*4882a593Smuzhiyun
1451*4882a593Smuzhiyun /* same layer but different type */
1452*4882a593Smuzhiyun if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
1453*4882a593Smuzhiyun (pdefault_rules->mandatory_fields[k] &
1454*4882a593Smuzhiyun IB_FLOW_SPEC_LAYER_MASK)) &&
1455*4882a593Smuzhiyun (current_flow->type !=
1456*4882a593Smuzhiyun pdefault_rules->mandatory_fields[k]))
1457*4882a593Smuzhiyun goto out;
1458*4882a593Smuzhiyun
1459*4882a593Smuzhiyun /* same layer, try match next one */
1460*4882a593Smuzhiyun if (current_flow->type ==
1461*4882a593Smuzhiyun pdefault_rules->mandatory_fields[k]) {
1462*4882a593Smuzhiyun j++;
1463*4882a593Smuzhiyun ib_flow +=
1464*4882a593Smuzhiyun ((union ib_flow_spec *)ib_flow)->size;
1465*4882a593Smuzhiyun }
1466*4882a593Smuzhiyun }
1467*4882a593Smuzhiyun
1468*4882a593Smuzhiyun ib_flow = flow_attr + 1;
1469*4882a593Smuzhiyun for (j = 0; j < flow_attr->num_of_specs;
1470*4882a593Smuzhiyun j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
1471*4882a593Smuzhiyun for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
1472*4882a593Smuzhiyun /* same layer and same type */
1473*4882a593Smuzhiyun if (((union ib_flow_spec *)ib_flow)->type ==
1474*4882a593Smuzhiyun pdefault_rules->mandatory_not_fields[k])
1475*4882a593Smuzhiyun goto out;
1476*4882a593Smuzhiyun
1477*4882a593Smuzhiyun return i;
1478*4882a593Smuzhiyun }
1479*4882a593Smuzhiyun out:
1480*4882a593Smuzhiyun return -1;
1481*4882a593Smuzhiyun }
1482*4882a593Smuzhiyun
__mlx4_ib_create_default_rules(struct mlx4_ib_dev * mdev,struct ib_qp * qp,const struct default_rules * pdefault_rules,struct _rule_hw * mlx4_spec)1483*4882a593Smuzhiyun static int __mlx4_ib_create_default_rules(
1484*4882a593Smuzhiyun struct mlx4_ib_dev *mdev,
1485*4882a593Smuzhiyun struct ib_qp *qp,
1486*4882a593Smuzhiyun const struct default_rules *pdefault_rules,
1487*4882a593Smuzhiyun struct _rule_hw *mlx4_spec) {
1488*4882a593Smuzhiyun int size = 0;
1489*4882a593Smuzhiyun int i;
1490*4882a593Smuzhiyun
1491*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
1492*4882a593Smuzhiyun union ib_flow_spec ib_spec = {};
1493*4882a593Smuzhiyun int ret;
1494*4882a593Smuzhiyun
1495*4882a593Smuzhiyun switch (pdefault_rules->rules_create_list[i]) {
1496*4882a593Smuzhiyun case 0:
1497*4882a593Smuzhiyun /* no rule */
1498*4882a593Smuzhiyun continue;
1499*4882a593Smuzhiyun case IB_FLOW_SPEC_IB:
1500*4882a593Smuzhiyun ib_spec.type = IB_FLOW_SPEC_IB;
1501*4882a593Smuzhiyun ib_spec.size = sizeof(struct ib_flow_spec_ib);
1502*4882a593Smuzhiyun
1503*4882a593Smuzhiyun break;
1504*4882a593Smuzhiyun default:
1505*4882a593Smuzhiyun /* invalid rule */
1506*4882a593Smuzhiyun return -EINVAL;
1507*4882a593Smuzhiyun }
1508*4882a593Smuzhiyun /* We must put empty rule, qpn is being ignored */
1509*4882a593Smuzhiyun ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
1510*4882a593Smuzhiyun mlx4_spec);
1511*4882a593Smuzhiyun if (ret < 0) {
1512*4882a593Smuzhiyun pr_info("invalid parsing\n");
1513*4882a593Smuzhiyun return -EINVAL;
1514*4882a593Smuzhiyun }
1515*4882a593Smuzhiyun
1516*4882a593Smuzhiyun mlx4_spec = (void *)mlx4_spec + ret;
1517*4882a593Smuzhiyun size += ret;
1518*4882a593Smuzhiyun }
1519*4882a593Smuzhiyun return size;
1520*4882a593Smuzhiyun }
1521*4882a593Smuzhiyun
__mlx4_ib_create_flow(struct ib_qp * qp,struct ib_flow_attr * flow_attr,int domain,enum mlx4_net_trans_promisc_mode flow_type,u64 * reg_id)1522*4882a593Smuzhiyun static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1523*4882a593Smuzhiyun int domain,
1524*4882a593Smuzhiyun enum mlx4_net_trans_promisc_mode flow_type,
1525*4882a593Smuzhiyun u64 *reg_id)
1526*4882a593Smuzhiyun {
1527*4882a593Smuzhiyun int ret, i;
1528*4882a593Smuzhiyun int size = 0;
1529*4882a593Smuzhiyun void *ib_flow;
1530*4882a593Smuzhiyun struct mlx4_ib_dev *mdev = to_mdev(qp->device);
1531*4882a593Smuzhiyun struct mlx4_cmd_mailbox *mailbox;
1532*4882a593Smuzhiyun struct mlx4_net_trans_rule_hw_ctrl *ctrl;
1533*4882a593Smuzhiyun int default_flow;
1534*4882a593Smuzhiyun
1535*4882a593Smuzhiyun if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
1536*4882a593Smuzhiyun pr_err("Invalid priority value %d\n", flow_attr->priority);
1537*4882a593Smuzhiyun return -EINVAL;
1538*4882a593Smuzhiyun }
1539*4882a593Smuzhiyun
1540*4882a593Smuzhiyun if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
1541*4882a593Smuzhiyun return -EINVAL;
1542*4882a593Smuzhiyun
1543*4882a593Smuzhiyun mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
1544*4882a593Smuzhiyun if (IS_ERR(mailbox))
1545*4882a593Smuzhiyun return PTR_ERR(mailbox);
1546*4882a593Smuzhiyun ctrl = mailbox->buf;
1547*4882a593Smuzhiyun
1548*4882a593Smuzhiyun ctrl->prio = cpu_to_be16(domain | flow_attr->priority);
1549*4882a593Smuzhiyun ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
1550*4882a593Smuzhiyun ctrl->port = flow_attr->port;
1551*4882a593Smuzhiyun ctrl->qpn = cpu_to_be32(qp->qp_num);
1552*4882a593Smuzhiyun
1553*4882a593Smuzhiyun ib_flow = flow_attr + 1;
1554*4882a593Smuzhiyun size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
1555*4882a593Smuzhiyun /* Add default flows */
1556*4882a593Smuzhiyun default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
1557*4882a593Smuzhiyun if (default_flow >= 0) {
1558*4882a593Smuzhiyun ret = __mlx4_ib_create_default_rules(
1559*4882a593Smuzhiyun mdev, qp, default_table + default_flow,
1560*4882a593Smuzhiyun mailbox->buf + size);
1561*4882a593Smuzhiyun if (ret < 0) {
1562*4882a593Smuzhiyun mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1563*4882a593Smuzhiyun return -EINVAL;
1564*4882a593Smuzhiyun }
1565*4882a593Smuzhiyun size += ret;
1566*4882a593Smuzhiyun }
1567*4882a593Smuzhiyun for (i = 0; i < flow_attr->num_of_specs; i++) {
1568*4882a593Smuzhiyun ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
1569*4882a593Smuzhiyun mailbox->buf + size);
1570*4882a593Smuzhiyun if (ret < 0) {
1571*4882a593Smuzhiyun mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1572*4882a593Smuzhiyun return -EINVAL;
1573*4882a593Smuzhiyun }
1574*4882a593Smuzhiyun ib_flow += ((union ib_flow_spec *) ib_flow)->size;
1575*4882a593Smuzhiyun size += ret;
1576*4882a593Smuzhiyun }
1577*4882a593Smuzhiyun
1578*4882a593Smuzhiyun if (mlx4_is_master(mdev->dev) && flow_type == MLX4_FS_REGULAR &&
1579*4882a593Smuzhiyun flow_attr->num_of_specs == 1) {
1580*4882a593Smuzhiyun struct _rule_hw *rule_header = (struct _rule_hw *)(ctrl + 1);
1581*4882a593Smuzhiyun enum ib_flow_spec_type header_spec =
1582*4882a593Smuzhiyun ((union ib_flow_spec *)(flow_attr + 1))->type;
1583*4882a593Smuzhiyun
1584*4882a593Smuzhiyun if (header_spec == IB_FLOW_SPEC_ETH)
1585*4882a593Smuzhiyun mlx4_handle_eth_header_mcast_prio(ctrl, rule_header);
1586*4882a593Smuzhiyun }
1587*4882a593Smuzhiyun
1588*4882a593Smuzhiyun ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
1589*4882a593Smuzhiyun MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
1590*4882a593Smuzhiyun MLX4_CMD_NATIVE);
1591*4882a593Smuzhiyun if (ret == -ENOMEM)
1592*4882a593Smuzhiyun pr_err("mcg table is full. Fail to register network rule.\n");
1593*4882a593Smuzhiyun else if (ret == -ENXIO)
1594*4882a593Smuzhiyun pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
1595*4882a593Smuzhiyun else if (ret)
1596*4882a593Smuzhiyun pr_err("Invalid argument. Fail to register network rule.\n");
1597*4882a593Smuzhiyun
1598*4882a593Smuzhiyun mlx4_free_cmd_mailbox(mdev->dev, mailbox);
1599*4882a593Smuzhiyun return ret;
1600*4882a593Smuzhiyun }
1601*4882a593Smuzhiyun
__mlx4_ib_destroy_flow(struct mlx4_dev * dev,u64 reg_id)1602*4882a593Smuzhiyun static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
1603*4882a593Smuzhiyun {
1604*4882a593Smuzhiyun int err;
1605*4882a593Smuzhiyun err = mlx4_cmd(dev, reg_id, 0, 0,
1606*4882a593Smuzhiyun MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
1607*4882a593Smuzhiyun MLX4_CMD_NATIVE);
1608*4882a593Smuzhiyun if (err)
1609*4882a593Smuzhiyun pr_err("Fail to detach network rule. registration id = 0x%llx\n",
1610*4882a593Smuzhiyun reg_id);
1611*4882a593Smuzhiyun return err;
1612*4882a593Smuzhiyun }
1613*4882a593Smuzhiyun
mlx4_ib_tunnel_steer_add(struct ib_qp * qp,struct ib_flow_attr * flow_attr,u64 * reg_id)1614*4882a593Smuzhiyun static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
1615*4882a593Smuzhiyun u64 *reg_id)
1616*4882a593Smuzhiyun {
1617*4882a593Smuzhiyun void *ib_flow;
1618*4882a593Smuzhiyun union ib_flow_spec *ib_spec;
1619*4882a593Smuzhiyun struct mlx4_dev *dev = to_mdev(qp->device)->dev;
1620*4882a593Smuzhiyun int err = 0;
1621*4882a593Smuzhiyun
1622*4882a593Smuzhiyun if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
1623*4882a593Smuzhiyun dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
1624*4882a593Smuzhiyun return 0; /* do nothing */
1625*4882a593Smuzhiyun
1626*4882a593Smuzhiyun ib_flow = flow_attr + 1;
1627*4882a593Smuzhiyun ib_spec = (union ib_flow_spec *)ib_flow;
1628*4882a593Smuzhiyun
1629*4882a593Smuzhiyun if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
1630*4882a593Smuzhiyun return 0; /* do nothing */
1631*4882a593Smuzhiyun
1632*4882a593Smuzhiyun err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
1633*4882a593Smuzhiyun flow_attr->port, qp->qp_num,
1634*4882a593Smuzhiyun MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
1635*4882a593Smuzhiyun reg_id);
1636*4882a593Smuzhiyun return err;
1637*4882a593Smuzhiyun }
1638*4882a593Smuzhiyun
mlx4_ib_add_dont_trap_rule(struct mlx4_dev * dev,struct ib_flow_attr * flow_attr,enum mlx4_net_trans_promisc_mode * type)1639*4882a593Smuzhiyun static int mlx4_ib_add_dont_trap_rule(struct mlx4_dev *dev,
1640*4882a593Smuzhiyun struct ib_flow_attr *flow_attr,
1641*4882a593Smuzhiyun enum mlx4_net_trans_promisc_mode *type)
1642*4882a593Smuzhiyun {
1643*4882a593Smuzhiyun int err = 0;
1644*4882a593Smuzhiyun
1645*4882a593Smuzhiyun if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER) ||
1646*4882a593Smuzhiyun (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC) ||
1647*4882a593Smuzhiyun (flow_attr->num_of_specs > 1) || (flow_attr->priority != 0)) {
1648*4882a593Smuzhiyun return -EOPNOTSUPP;
1649*4882a593Smuzhiyun }
1650*4882a593Smuzhiyun
1651*4882a593Smuzhiyun if (flow_attr->num_of_specs == 0) {
1652*4882a593Smuzhiyun type[0] = MLX4_FS_MC_SNIFFER;
1653*4882a593Smuzhiyun type[1] = MLX4_FS_UC_SNIFFER;
1654*4882a593Smuzhiyun } else {
1655*4882a593Smuzhiyun union ib_flow_spec *ib_spec;
1656*4882a593Smuzhiyun
1657*4882a593Smuzhiyun ib_spec = (union ib_flow_spec *)(flow_attr + 1);
1658*4882a593Smuzhiyun if (ib_spec->type != IB_FLOW_SPEC_ETH)
1659*4882a593Smuzhiyun return -EINVAL;
1660*4882a593Smuzhiyun
1661*4882a593Smuzhiyun /* if all is zero than MC and UC */
1662*4882a593Smuzhiyun if (is_zero_ether_addr(ib_spec->eth.mask.dst_mac)) {
1663*4882a593Smuzhiyun type[0] = MLX4_FS_MC_SNIFFER;
1664*4882a593Smuzhiyun type[1] = MLX4_FS_UC_SNIFFER;
1665*4882a593Smuzhiyun } else {
1666*4882a593Smuzhiyun u8 mac[ETH_ALEN] = {ib_spec->eth.mask.dst_mac[0] ^ 0x01,
1667*4882a593Smuzhiyun ib_spec->eth.mask.dst_mac[1],
1668*4882a593Smuzhiyun ib_spec->eth.mask.dst_mac[2],
1669*4882a593Smuzhiyun ib_spec->eth.mask.dst_mac[3],
1670*4882a593Smuzhiyun ib_spec->eth.mask.dst_mac[4],
1671*4882a593Smuzhiyun ib_spec->eth.mask.dst_mac[5]};
1672*4882a593Smuzhiyun
1673*4882a593Smuzhiyun /* Above xor was only on MC bit, non empty mask is valid
1674*4882a593Smuzhiyun * only if this bit is set and rest are zero.
1675*4882a593Smuzhiyun */
1676*4882a593Smuzhiyun if (!is_zero_ether_addr(&mac[0]))
1677*4882a593Smuzhiyun return -EINVAL;
1678*4882a593Smuzhiyun
1679*4882a593Smuzhiyun if (is_multicast_ether_addr(ib_spec->eth.val.dst_mac))
1680*4882a593Smuzhiyun type[0] = MLX4_FS_MC_SNIFFER;
1681*4882a593Smuzhiyun else
1682*4882a593Smuzhiyun type[0] = MLX4_FS_UC_SNIFFER;
1683*4882a593Smuzhiyun }
1684*4882a593Smuzhiyun }
1685*4882a593Smuzhiyun
1686*4882a593Smuzhiyun return err;
1687*4882a593Smuzhiyun }
1688*4882a593Smuzhiyun
mlx4_ib_create_flow(struct ib_qp * qp,struct ib_flow_attr * flow_attr,struct ib_udata * udata)1689*4882a593Smuzhiyun static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
1690*4882a593Smuzhiyun struct ib_flow_attr *flow_attr,
1691*4882a593Smuzhiyun struct ib_udata *udata)
1692*4882a593Smuzhiyun {
1693*4882a593Smuzhiyun int err = 0, i = 0, j = 0;
1694*4882a593Smuzhiyun struct mlx4_ib_flow *mflow;
1695*4882a593Smuzhiyun enum mlx4_net_trans_promisc_mode type[2];
1696*4882a593Smuzhiyun struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
1697*4882a593Smuzhiyun int is_bonded = mlx4_is_bonded(dev);
1698*4882a593Smuzhiyun
1699*4882a593Smuzhiyun if (flow_attr->port < 1 || flow_attr->port > qp->device->phys_port_cnt)
1700*4882a593Smuzhiyun return ERR_PTR(-EINVAL);
1701*4882a593Smuzhiyun
1702*4882a593Smuzhiyun if (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)
1703*4882a593Smuzhiyun return ERR_PTR(-EOPNOTSUPP);
1704*4882a593Smuzhiyun
1705*4882a593Smuzhiyun if ((flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) &&
1706*4882a593Smuzhiyun (flow_attr->type != IB_FLOW_ATTR_NORMAL))
1707*4882a593Smuzhiyun return ERR_PTR(-EOPNOTSUPP);
1708*4882a593Smuzhiyun
1709*4882a593Smuzhiyun if (udata &&
1710*4882a593Smuzhiyun udata->inlen && !ib_is_udata_cleared(udata, 0, udata->inlen))
1711*4882a593Smuzhiyun return ERR_PTR(-EOPNOTSUPP);
1712*4882a593Smuzhiyun
1713*4882a593Smuzhiyun memset(type, 0, sizeof(type));
1714*4882a593Smuzhiyun
1715*4882a593Smuzhiyun mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
1716*4882a593Smuzhiyun if (!mflow) {
1717*4882a593Smuzhiyun err = -ENOMEM;
1718*4882a593Smuzhiyun goto err_free;
1719*4882a593Smuzhiyun }
1720*4882a593Smuzhiyun
1721*4882a593Smuzhiyun switch (flow_attr->type) {
1722*4882a593Smuzhiyun case IB_FLOW_ATTR_NORMAL:
1723*4882a593Smuzhiyun /* If dont trap flag (continue match) is set, under specific
1724*4882a593Smuzhiyun * condition traffic be replicated to given qp,
1725*4882a593Smuzhiyun * without stealing it
1726*4882a593Smuzhiyun */
1727*4882a593Smuzhiyun if (unlikely(flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP)) {
1728*4882a593Smuzhiyun err = mlx4_ib_add_dont_trap_rule(dev,
1729*4882a593Smuzhiyun flow_attr,
1730*4882a593Smuzhiyun type);
1731*4882a593Smuzhiyun if (err)
1732*4882a593Smuzhiyun goto err_free;
1733*4882a593Smuzhiyun } else {
1734*4882a593Smuzhiyun type[0] = MLX4_FS_REGULAR;
1735*4882a593Smuzhiyun }
1736*4882a593Smuzhiyun break;
1737*4882a593Smuzhiyun
1738*4882a593Smuzhiyun case IB_FLOW_ATTR_ALL_DEFAULT:
1739*4882a593Smuzhiyun type[0] = MLX4_FS_ALL_DEFAULT;
1740*4882a593Smuzhiyun break;
1741*4882a593Smuzhiyun
1742*4882a593Smuzhiyun case IB_FLOW_ATTR_MC_DEFAULT:
1743*4882a593Smuzhiyun type[0] = MLX4_FS_MC_DEFAULT;
1744*4882a593Smuzhiyun break;
1745*4882a593Smuzhiyun
1746*4882a593Smuzhiyun case IB_FLOW_ATTR_SNIFFER:
1747*4882a593Smuzhiyun type[0] = MLX4_FS_MIRROR_RX_PORT;
1748*4882a593Smuzhiyun type[1] = MLX4_FS_MIRROR_SX_PORT;
1749*4882a593Smuzhiyun break;
1750*4882a593Smuzhiyun
1751*4882a593Smuzhiyun default:
1752*4882a593Smuzhiyun err = -EINVAL;
1753*4882a593Smuzhiyun goto err_free;
1754*4882a593Smuzhiyun }
1755*4882a593Smuzhiyun
1756*4882a593Smuzhiyun while (i < ARRAY_SIZE(type) && type[i]) {
1757*4882a593Smuzhiyun err = __mlx4_ib_create_flow(qp, flow_attr, MLX4_DOMAIN_UVERBS,
1758*4882a593Smuzhiyun type[i], &mflow->reg_id[i].id);
1759*4882a593Smuzhiyun if (err)
1760*4882a593Smuzhiyun goto err_create_flow;
1761*4882a593Smuzhiyun if (is_bonded) {
1762*4882a593Smuzhiyun /* Application always sees one port so the mirror rule
1763*4882a593Smuzhiyun * must be on port #2
1764*4882a593Smuzhiyun */
1765*4882a593Smuzhiyun flow_attr->port = 2;
1766*4882a593Smuzhiyun err = __mlx4_ib_create_flow(qp, flow_attr,
1767*4882a593Smuzhiyun MLX4_DOMAIN_UVERBS, type[j],
1768*4882a593Smuzhiyun &mflow->reg_id[j].mirror);
1769*4882a593Smuzhiyun flow_attr->port = 1;
1770*4882a593Smuzhiyun if (err)
1771*4882a593Smuzhiyun goto err_create_flow;
1772*4882a593Smuzhiyun j++;
1773*4882a593Smuzhiyun }
1774*4882a593Smuzhiyun
1775*4882a593Smuzhiyun i++;
1776*4882a593Smuzhiyun }
1777*4882a593Smuzhiyun
1778*4882a593Smuzhiyun if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
1779*4882a593Smuzhiyun err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1780*4882a593Smuzhiyun &mflow->reg_id[i].id);
1781*4882a593Smuzhiyun if (err)
1782*4882a593Smuzhiyun goto err_create_flow;
1783*4882a593Smuzhiyun
1784*4882a593Smuzhiyun if (is_bonded) {
1785*4882a593Smuzhiyun flow_attr->port = 2;
1786*4882a593Smuzhiyun err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
1787*4882a593Smuzhiyun &mflow->reg_id[j].mirror);
1788*4882a593Smuzhiyun flow_attr->port = 1;
1789*4882a593Smuzhiyun if (err)
1790*4882a593Smuzhiyun goto err_create_flow;
1791*4882a593Smuzhiyun j++;
1792*4882a593Smuzhiyun }
1793*4882a593Smuzhiyun /* function to create mirror rule */
1794*4882a593Smuzhiyun i++;
1795*4882a593Smuzhiyun }
1796*4882a593Smuzhiyun
1797*4882a593Smuzhiyun return &mflow->ibflow;
1798*4882a593Smuzhiyun
1799*4882a593Smuzhiyun err_create_flow:
1800*4882a593Smuzhiyun while (i) {
1801*4882a593Smuzhiyun (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1802*4882a593Smuzhiyun mflow->reg_id[i].id);
1803*4882a593Smuzhiyun i--;
1804*4882a593Smuzhiyun }
1805*4882a593Smuzhiyun
1806*4882a593Smuzhiyun while (j) {
1807*4882a593Smuzhiyun (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
1808*4882a593Smuzhiyun mflow->reg_id[j].mirror);
1809*4882a593Smuzhiyun j--;
1810*4882a593Smuzhiyun }
1811*4882a593Smuzhiyun err_free:
1812*4882a593Smuzhiyun kfree(mflow);
1813*4882a593Smuzhiyun return ERR_PTR(err);
1814*4882a593Smuzhiyun }
1815*4882a593Smuzhiyun
mlx4_ib_destroy_flow(struct ib_flow * flow_id)1816*4882a593Smuzhiyun static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
1817*4882a593Smuzhiyun {
1818*4882a593Smuzhiyun int err, ret = 0;
1819*4882a593Smuzhiyun int i = 0;
1820*4882a593Smuzhiyun struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
1821*4882a593Smuzhiyun struct mlx4_ib_flow *mflow = to_mflow(flow_id);
1822*4882a593Smuzhiyun
1823*4882a593Smuzhiyun while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
1824*4882a593Smuzhiyun err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
1825*4882a593Smuzhiyun if (err)
1826*4882a593Smuzhiyun ret = err;
1827*4882a593Smuzhiyun if (mflow->reg_id[i].mirror) {
1828*4882a593Smuzhiyun err = __mlx4_ib_destroy_flow(mdev->dev,
1829*4882a593Smuzhiyun mflow->reg_id[i].mirror);
1830*4882a593Smuzhiyun if (err)
1831*4882a593Smuzhiyun ret = err;
1832*4882a593Smuzhiyun }
1833*4882a593Smuzhiyun i++;
1834*4882a593Smuzhiyun }
1835*4882a593Smuzhiyun
1836*4882a593Smuzhiyun kfree(mflow);
1837*4882a593Smuzhiyun return ret;
1838*4882a593Smuzhiyun }
1839*4882a593Smuzhiyun
mlx4_ib_mcg_attach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)1840*4882a593Smuzhiyun static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1841*4882a593Smuzhiyun {
1842*4882a593Smuzhiyun int err;
1843*4882a593Smuzhiyun struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1844*4882a593Smuzhiyun struct mlx4_dev *dev = mdev->dev;
1845*4882a593Smuzhiyun struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1846*4882a593Smuzhiyun struct mlx4_ib_steering *ib_steering = NULL;
1847*4882a593Smuzhiyun enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
1848*4882a593Smuzhiyun struct mlx4_flow_reg_id reg_id;
1849*4882a593Smuzhiyun
1850*4882a593Smuzhiyun if (mdev->dev->caps.steering_mode ==
1851*4882a593Smuzhiyun MLX4_STEERING_MODE_DEVICE_MANAGED) {
1852*4882a593Smuzhiyun ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
1853*4882a593Smuzhiyun if (!ib_steering)
1854*4882a593Smuzhiyun return -ENOMEM;
1855*4882a593Smuzhiyun }
1856*4882a593Smuzhiyun
1857*4882a593Smuzhiyun err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
1858*4882a593Smuzhiyun !!(mqp->flags &
1859*4882a593Smuzhiyun MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1860*4882a593Smuzhiyun prot, ®_id.id);
1861*4882a593Smuzhiyun if (err) {
1862*4882a593Smuzhiyun pr_err("multicast attach op failed, err %d\n", err);
1863*4882a593Smuzhiyun goto err_malloc;
1864*4882a593Smuzhiyun }
1865*4882a593Smuzhiyun
1866*4882a593Smuzhiyun reg_id.mirror = 0;
1867*4882a593Smuzhiyun if (mlx4_is_bonded(dev)) {
1868*4882a593Smuzhiyun err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
1869*4882a593Smuzhiyun (mqp->port == 1) ? 2 : 1,
1870*4882a593Smuzhiyun !!(mqp->flags &
1871*4882a593Smuzhiyun MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
1872*4882a593Smuzhiyun prot, ®_id.mirror);
1873*4882a593Smuzhiyun if (err)
1874*4882a593Smuzhiyun goto err_add;
1875*4882a593Smuzhiyun }
1876*4882a593Smuzhiyun
1877*4882a593Smuzhiyun err = add_gid_entry(ibqp, gid);
1878*4882a593Smuzhiyun if (err)
1879*4882a593Smuzhiyun goto err_add;
1880*4882a593Smuzhiyun
1881*4882a593Smuzhiyun if (ib_steering) {
1882*4882a593Smuzhiyun memcpy(ib_steering->gid.raw, gid->raw, 16);
1883*4882a593Smuzhiyun ib_steering->reg_id = reg_id;
1884*4882a593Smuzhiyun mutex_lock(&mqp->mutex);
1885*4882a593Smuzhiyun list_add(&ib_steering->list, &mqp->steering_rules);
1886*4882a593Smuzhiyun mutex_unlock(&mqp->mutex);
1887*4882a593Smuzhiyun }
1888*4882a593Smuzhiyun return 0;
1889*4882a593Smuzhiyun
1890*4882a593Smuzhiyun err_add:
1891*4882a593Smuzhiyun mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1892*4882a593Smuzhiyun prot, reg_id.id);
1893*4882a593Smuzhiyun if (reg_id.mirror)
1894*4882a593Smuzhiyun mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1895*4882a593Smuzhiyun prot, reg_id.mirror);
1896*4882a593Smuzhiyun err_malloc:
1897*4882a593Smuzhiyun kfree(ib_steering);
1898*4882a593Smuzhiyun
1899*4882a593Smuzhiyun return err;
1900*4882a593Smuzhiyun }
1901*4882a593Smuzhiyun
find_gid_entry(struct mlx4_ib_qp * qp,u8 * raw)1902*4882a593Smuzhiyun static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
1903*4882a593Smuzhiyun {
1904*4882a593Smuzhiyun struct mlx4_ib_gid_entry *ge;
1905*4882a593Smuzhiyun struct mlx4_ib_gid_entry *tmp;
1906*4882a593Smuzhiyun struct mlx4_ib_gid_entry *ret = NULL;
1907*4882a593Smuzhiyun
1908*4882a593Smuzhiyun list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1909*4882a593Smuzhiyun if (!memcmp(raw, ge->gid.raw, 16)) {
1910*4882a593Smuzhiyun ret = ge;
1911*4882a593Smuzhiyun break;
1912*4882a593Smuzhiyun }
1913*4882a593Smuzhiyun }
1914*4882a593Smuzhiyun
1915*4882a593Smuzhiyun return ret;
1916*4882a593Smuzhiyun }
1917*4882a593Smuzhiyun
mlx4_ib_mcg_detach(struct ib_qp * ibqp,union ib_gid * gid,u16 lid)1918*4882a593Smuzhiyun static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
1919*4882a593Smuzhiyun {
1920*4882a593Smuzhiyun int err;
1921*4882a593Smuzhiyun struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
1922*4882a593Smuzhiyun struct mlx4_dev *dev = mdev->dev;
1923*4882a593Smuzhiyun struct mlx4_ib_qp *mqp = to_mqp(ibqp);
1924*4882a593Smuzhiyun struct net_device *ndev;
1925*4882a593Smuzhiyun struct mlx4_ib_gid_entry *ge;
1926*4882a593Smuzhiyun struct mlx4_flow_reg_id reg_id = {0, 0};
1927*4882a593Smuzhiyun enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
1928*4882a593Smuzhiyun
1929*4882a593Smuzhiyun if (mdev->dev->caps.steering_mode ==
1930*4882a593Smuzhiyun MLX4_STEERING_MODE_DEVICE_MANAGED) {
1931*4882a593Smuzhiyun struct mlx4_ib_steering *ib_steering;
1932*4882a593Smuzhiyun
1933*4882a593Smuzhiyun mutex_lock(&mqp->mutex);
1934*4882a593Smuzhiyun list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
1935*4882a593Smuzhiyun if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
1936*4882a593Smuzhiyun list_del(&ib_steering->list);
1937*4882a593Smuzhiyun break;
1938*4882a593Smuzhiyun }
1939*4882a593Smuzhiyun }
1940*4882a593Smuzhiyun mutex_unlock(&mqp->mutex);
1941*4882a593Smuzhiyun if (&ib_steering->list == &mqp->steering_rules) {
1942*4882a593Smuzhiyun pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
1943*4882a593Smuzhiyun return -EINVAL;
1944*4882a593Smuzhiyun }
1945*4882a593Smuzhiyun reg_id = ib_steering->reg_id;
1946*4882a593Smuzhiyun kfree(ib_steering);
1947*4882a593Smuzhiyun }
1948*4882a593Smuzhiyun
1949*4882a593Smuzhiyun err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1950*4882a593Smuzhiyun prot, reg_id.id);
1951*4882a593Smuzhiyun if (err)
1952*4882a593Smuzhiyun return err;
1953*4882a593Smuzhiyun
1954*4882a593Smuzhiyun if (mlx4_is_bonded(dev)) {
1955*4882a593Smuzhiyun err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
1956*4882a593Smuzhiyun prot, reg_id.mirror);
1957*4882a593Smuzhiyun if (err)
1958*4882a593Smuzhiyun return err;
1959*4882a593Smuzhiyun }
1960*4882a593Smuzhiyun
1961*4882a593Smuzhiyun mutex_lock(&mqp->mutex);
1962*4882a593Smuzhiyun ge = find_gid_entry(mqp, gid->raw);
1963*4882a593Smuzhiyun if (ge) {
1964*4882a593Smuzhiyun spin_lock_bh(&mdev->iboe.lock);
1965*4882a593Smuzhiyun ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
1966*4882a593Smuzhiyun if (ndev)
1967*4882a593Smuzhiyun dev_hold(ndev);
1968*4882a593Smuzhiyun spin_unlock_bh(&mdev->iboe.lock);
1969*4882a593Smuzhiyun if (ndev)
1970*4882a593Smuzhiyun dev_put(ndev);
1971*4882a593Smuzhiyun list_del(&ge->list);
1972*4882a593Smuzhiyun kfree(ge);
1973*4882a593Smuzhiyun } else
1974*4882a593Smuzhiyun pr_warn("could not find mgid entry\n");
1975*4882a593Smuzhiyun
1976*4882a593Smuzhiyun mutex_unlock(&mqp->mutex);
1977*4882a593Smuzhiyun
1978*4882a593Smuzhiyun return 0;
1979*4882a593Smuzhiyun }
1980*4882a593Smuzhiyun
init_node_data(struct mlx4_ib_dev * dev)1981*4882a593Smuzhiyun static int init_node_data(struct mlx4_ib_dev *dev)
1982*4882a593Smuzhiyun {
1983*4882a593Smuzhiyun struct ib_smp *in_mad = NULL;
1984*4882a593Smuzhiyun struct ib_smp *out_mad = NULL;
1985*4882a593Smuzhiyun int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
1986*4882a593Smuzhiyun int err = -ENOMEM;
1987*4882a593Smuzhiyun
1988*4882a593Smuzhiyun in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
1989*4882a593Smuzhiyun out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
1990*4882a593Smuzhiyun if (!in_mad || !out_mad)
1991*4882a593Smuzhiyun goto out;
1992*4882a593Smuzhiyun
1993*4882a593Smuzhiyun init_query_mad(in_mad);
1994*4882a593Smuzhiyun in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
1995*4882a593Smuzhiyun if (mlx4_is_master(dev->dev))
1996*4882a593Smuzhiyun mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
1997*4882a593Smuzhiyun
1998*4882a593Smuzhiyun err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
1999*4882a593Smuzhiyun if (err)
2000*4882a593Smuzhiyun goto out;
2001*4882a593Smuzhiyun
2002*4882a593Smuzhiyun memcpy(dev->ib_dev.node_desc, out_mad->data, IB_DEVICE_NODE_DESC_MAX);
2003*4882a593Smuzhiyun
2004*4882a593Smuzhiyun in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
2005*4882a593Smuzhiyun
2006*4882a593Smuzhiyun err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
2007*4882a593Smuzhiyun if (err)
2008*4882a593Smuzhiyun goto out;
2009*4882a593Smuzhiyun
2010*4882a593Smuzhiyun dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
2011*4882a593Smuzhiyun memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
2012*4882a593Smuzhiyun
2013*4882a593Smuzhiyun out:
2014*4882a593Smuzhiyun kfree(in_mad);
2015*4882a593Smuzhiyun kfree(out_mad);
2016*4882a593Smuzhiyun return err;
2017*4882a593Smuzhiyun }
2018*4882a593Smuzhiyun
hca_type_show(struct device * device,struct device_attribute * attr,char * buf)2019*4882a593Smuzhiyun static ssize_t hca_type_show(struct device *device,
2020*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
2021*4882a593Smuzhiyun {
2022*4882a593Smuzhiyun struct mlx4_ib_dev *dev =
2023*4882a593Smuzhiyun rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev);
2024*4882a593Smuzhiyun return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
2025*4882a593Smuzhiyun }
2026*4882a593Smuzhiyun static DEVICE_ATTR_RO(hca_type);
2027*4882a593Smuzhiyun
hw_rev_show(struct device * device,struct device_attribute * attr,char * buf)2028*4882a593Smuzhiyun static ssize_t hw_rev_show(struct device *device,
2029*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
2030*4882a593Smuzhiyun {
2031*4882a593Smuzhiyun struct mlx4_ib_dev *dev =
2032*4882a593Smuzhiyun rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev);
2033*4882a593Smuzhiyun return sprintf(buf, "%x\n", dev->dev->rev_id);
2034*4882a593Smuzhiyun }
2035*4882a593Smuzhiyun static DEVICE_ATTR_RO(hw_rev);
2036*4882a593Smuzhiyun
board_id_show(struct device * device,struct device_attribute * attr,char * buf)2037*4882a593Smuzhiyun static ssize_t board_id_show(struct device *device,
2038*4882a593Smuzhiyun struct device_attribute *attr, char *buf)
2039*4882a593Smuzhiyun {
2040*4882a593Smuzhiyun struct mlx4_ib_dev *dev =
2041*4882a593Smuzhiyun rdma_device_to_drv_device(device, struct mlx4_ib_dev, ib_dev);
2042*4882a593Smuzhiyun
2043*4882a593Smuzhiyun return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
2044*4882a593Smuzhiyun dev->dev->board_id);
2045*4882a593Smuzhiyun }
2046*4882a593Smuzhiyun static DEVICE_ATTR_RO(board_id);
2047*4882a593Smuzhiyun
2048*4882a593Smuzhiyun static struct attribute *mlx4_class_attributes[] = {
2049*4882a593Smuzhiyun &dev_attr_hw_rev.attr,
2050*4882a593Smuzhiyun &dev_attr_hca_type.attr,
2051*4882a593Smuzhiyun &dev_attr_board_id.attr,
2052*4882a593Smuzhiyun NULL
2053*4882a593Smuzhiyun };
2054*4882a593Smuzhiyun
2055*4882a593Smuzhiyun static const struct attribute_group mlx4_attr_group = {
2056*4882a593Smuzhiyun .attrs = mlx4_class_attributes,
2057*4882a593Smuzhiyun };
2058*4882a593Smuzhiyun
2059*4882a593Smuzhiyun struct diag_counter {
2060*4882a593Smuzhiyun const char *name;
2061*4882a593Smuzhiyun u32 offset;
2062*4882a593Smuzhiyun };
2063*4882a593Smuzhiyun
2064*4882a593Smuzhiyun #define DIAG_COUNTER(_name, _offset) \
2065*4882a593Smuzhiyun { .name = #_name, .offset = _offset }
2066*4882a593Smuzhiyun
2067*4882a593Smuzhiyun static const struct diag_counter diag_basic[] = {
2068*4882a593Smuzhiyun DIAG_COUNTER(rq_num_lle, 0x00),
2069*4882a593Smuzhiyun DIAG_COUNTER(sq_num_lle, 0x04),
2070*4882a593Smuzhiyun DIAG_COUNTER(rq_num_lqpoe, 0x08),
2071*4882a593Smuzhiyun DIAG_COUNTER(sq_num_lqpoe, 0x0C),
2072*4882a593Smuzhiyun DIAG_COUNTER(rq_num_lpe, 0x18),
2073*4882a593Smuzhiyun DIAG_COUNTER(sq_num_lpe, 0x1C),
2074*4882a593Smuzhiyun DIAG_COUNTER(rq_num_wrfe, 0x20),
2075*4882a593Smuzhiyun DIAG_COUNTER(sq_num_wrfe, 0x24),
2076*4882a593Smuzhiyun DIAG_COUNTER(sq_num_mwbe, 0x2C),
2077*4882a593Smuzhiyun DIAG_COUNTER(sq_num_bre, 0x34),
2078*4882a593Smuzhiyun DIAG_COUNTER(sq_num_rire, 0x44),
2079*4882a593Smuzhiyun DIAG_COUNTER(rq_num_rire, 0x48),
2080*4882a593Smuzhiyun DIAG_COUNTER(sq_num_rae, 0x4C),
2081*4882a593Smuzhiyun DIAG_COUNTER(rq_num_rae, 0x50),
2082*4882a593Smuzhiyun DIAG_COUNTER(sq_num_roe, 0x54),
2083*4882a593Smuzhiyun DIAG_COUNTER(sq_num_tree, 0x5C),
2084*4882a593Smuzhiyun DIAG_COUNTER(sq_num_rree, 0x64),
2085*4882a593Smuzhiyun DIAG_COUNTER(rq_num_rnr, 0x68),
2086*4882a593Smuzhiyun DIAG_COUNTER(sq_num_rnr, 0x6C),
2087*4882a593Smuzhiyun DIAG_COUNTER(rq_num_oos, 0x100),
2088*4882a593Smuzhiyun DIAG_COUNTER(sq_num_oos, 0x104),
2089*4882a593Smuzhiyun };
2090*4882a593Smuzhiyun
2091*4882a593Smuzhiyun static const struct diag_counter diag_ext[] = {
2092*4882a593Smuzhiyun DIAG_COUNTER(rq_num_dup, 0x130),
2093*4882a593Smuzhiyun DIAG_COUNTER(sq_num_to, 0x134),
2094*4882a593Smuzhiyun };
2095*4882a593Smuzhiyun
2096*4882a593Smuzhiyun static const struct diag_counter diag_device_only[] = {
2097*4882a593Smuzhiyun DIAG_COUNTER(num_cqovf, 0x1A0),
2098*4882a593Smuzhiyun DIAG_COUNTER(rq_num_udsdprd, 0x118),
2099*4882a593Smuzhiyun };
2100*4882a593Smuzhiyun
mlx4_ib_alloc_hw_stats(struct ib_device * ibdev,u8 port_num)2101*4882a593Smuzhiyun static struct rdma_hw_stats *mlx4_ib_alloc_hw_stats(struct ib_device *ibdev,
2102*4882a593Smuzhiyun u8 port_num)
2103*4882a593Smuzhiyun {
2104*4882a593Smuzhiyun struct mlx4_ib_dev *dev = to_mdev(ibdev);
2105*4882a593Smuzhiyun struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2106*4882a593Smuzhiyun
2107*4882a593Smuzhiyun if (!diag[!!port_num].name)
2108*4882a593Smuzhiyun return NULL;
2109*4882a593Smuzhiyun
2110*4882a593Smuzhiyun return rdma_alloc_hw_stats_struct(diag[!!port_num].name,
2111*4882a593Smuzhiyun diag[!!port_num].num_counters,
2112*4882a593Smuzhiyun RDMA_HW_STATS_DEFAULT_LIFESPAN);
2113*4882a593Smuzhiyun }
2114*4882a593Smuzhiyun
mlx4_ib_get_hw_stats(struct ib_device * ibdev,struct rdma_hw_stats * stats,u8 port,int index)2115*4882a593Smuzhiyun static int mlx4_ib_get_hw_stats(struct ib_device *ibdev,
2116*4882a593Smuzhiyun struct rdma_hw_stats *stats,
2117*4882a593Smuzhiyun u8 port, int index)
2118*4882a593Smuzhiyun {
2119*4882a593Smuzhiyun struct mlx4_ib_dev *dev = to_mdev(ibdev);
2120*4882a593Smuzhiyun struct mlx4_ib_diag_counters *diag = dev->diag_counters;
2121*4882a593Smuzhiyun u32 hw_value[ARRAY_SIZE(diag_device_only) +
2122*4882a593Smuzhiyun ARRAY_SIZE(diag_ext) + ARRAY_SIZE(diag_basic)] = {};
2123*4882a593Smuzhiyun int ret;
2124*4882a593Smuzhiyun int i;
2125*4882a593Smuzhiyun
2126*4882a593Smuzhiyun ret = mlx4_query_diag_counters(dev->dev,
2127*4882a593Smuzhiyun MLX4_OP_MOD_QUERY_TRANSPORT_CI_ERRORS,
2128*4882a593Smuzhiyun diag[!!port].offset, hw_value,
2129*4882a593Smuzhiyun diag[!!port].num_counters, port);
2130*4882a593Smuzhiyun
2131*4882a593Smuzhiyun if (ret)
2132*4882a593Smuzhiyun return ret;
2133*4882a593Smuzhiyun
2134*4882a593Smuzhiyun for (i = 0; i < diag[!!port].num_counters; i++)
2135*4882a593Smuzhiyun stats->value[i] = hw_value[i];
2136*4882a593Smuzhiyun
2137*4882a593Smuzhiyun return diag[!!port].num_counters;
2138*4882a593Smuzhiyun }
2139*4882a593Smuzhiyun
__mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev * ibdev,const char *** name,u32 ** offset,u32 * num,bool port)2140*4882a593Smuzhiyun static int __mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev,
2141*4882a593Smuzhiyun const char ***name,
2142*4882a593Smuzhiyun u32 **offset,
2143*4882a593Smuzhiyun u32 *num,
2144*4882a593Smuzhiyun bool port)
2145*4882a593Smuzhiyun {
2146*4882a593Smuzhiyun u32 num_counters;
2147*4882a593Smuzhiyun
2148*4882a593Smuzhiyun num_counters = ARRAY_SIZE(diag_basic);
2149*4882a593Smuzhiyun
2150*4882a593Smuzhiyun if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT)
2151*4882a593Smuzhiyun num_counters += ARRAY_SIZE(diag_ext);
2152*4882a593Smuzhiyun
2153*4882a593Smuzhiyun if (!port)
2154*4882a593Smuzhiyun num_counters += ARRAY_SIZE(diag_device_only);
2155*4882a593Smuzhiyun
2156*4882a593Smuzhiyun *name = kcalloc(num_counters, sizeof(**name), GFP_KERNEL);
2157*4882a593Smuzhiyun if (!*name)
2158*4882a593Smuzhiyun return -ENOMEM;
2159*4882a593Smuzhiyun
2160*4882a593Smuzhiyun *offset = kcalloc(num_counters, sizeof(**offset), GFP_KERNEL);
2161*4882a593Smuzhiyun if (!*offset)
2162*4882a593Smuzhiyun goto err_name;
2163*4882a593Smuzhiyun
2164*4882a593Smuzhiyun *num = num_counters;
2165*4882a593Smuzhiyun
2166*4882a593Smuzhiyun return 0;
2167*4882a593Smuzhiyun
2168*4882a593Smuzhiyun err_name:
2169*4882a593Smuzhiyun kfree(*name);
2170*4882a593Smuzhiyun return -ENOMEM;
2171*4882a593Smuzhiyun }
2172*4882a593Smuzhiyun
mlx4_ib_fill_diag_counters(struct mlx4_ib_dev * ibdev,const char ** name,u32 * offset,bool port)2173*4882a593Smuzhiyun static void mlx4_ib_fill_diag_counters(struct mlx4_ib_dev *ibdev,
2174*4882a593Smuzhiyun const char **name,
2175*4882a593Smuzhiyun u32 *offset,
2176*4882a593Smuzhiyun bool port)
2177*4882a593Smuzhiyun {
2178*4882a593Smuzhiyun int i;
2179*4882a593Smuzhiyun int j;
2180*4882a593Smuzhiyun
2181*4882a593Smuzhiyun for (i = 0, j = 0; i < ARRAY_SIZE(diag_basic); i++, j++) {
2182*4882a593Smuzhiyun name[i] = diag_basic[i].name;
2183*4882a593Smuzhiyun offset[i] = diag_basic[i].offset;
2184*4882a593Smuzhiyun }
2185*4882a593Smuzhiyun
2186*4882a593Smuzhiyun if (ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT) {
2187*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(diag_ext); i++, j++) {
2188*4882a593Smuzhiyun name[j] = diag_ext[i].name;
2189*4882a593Smuzhiyun offset[j] = diag_ext[i].offset;
2190*4882a593Smuzhiyun }
2191*4882a593Smuzhiyun }
2192*4882a593Smuzhiyun
2193*4882a593Smuzhiyun if (!port) {
2194*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(diag_device_only); i++, j++) {
2195*4882a593Smuzhiyun name[j] = diag_device_only[i].name;
2196*4882a593Smuzhiyun offset[j] = diag_device_only[i].offset;
2197*4882a593Smuzhiyun }
2198*4882a593Smuzhiyun }
2199*4882a593Smuzhiyun }
2200*4882a593Smuzhiyun
2201*4882a593Smuzhiyun static const struct ib_device_ops mlx4_ib_hw_stats_ops = {
2202*4882a593Smuzhiyun .alloc_hw_stats = mlx4_ib_alloc_hw_stats,
2203*4882a593Smuzhiyun .get_hw_stats = mlx4_ib_get_hw_stats,
2204*4882a593Smuzhiyun };
2205*4882a593Smuzhiyun
mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev * ibdev)2206*4882a593Smuzhiyun static int mlx4_ib_alloc_diag_counters(struct mlx4_ib_dev *ibdev)
2207*4882a593Smuzhiyun {
2208*4882a593Smuzhiyun struct mlx4_ib_diag_counters *diag = ibdev->diag_counters;
2209*4882a593Smuzhiyun int i;
2210*4882a593Smuzhiyun int ret;
2211*4882a593Smuzhiyun bool per_port = !!(ibdev->dev->caps.flags2 &
2212*4882a593Smuzhiyun MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT);
2213*4882a593Smuzhiyun
2214*4882a593Smuzhiyun if (mlx4_is_slave(ibdev->dev))
2215*4882a593Smuzhiyun return 0;
2216*4882a593Smuzhiyun
2217*4882a593Smuzhiyun for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2218*4882a593Smuzhiyun /* i == 1 means we are building port counters */
2219*4882a593Smuzhiyun if (i && !per_port)
2220*4882a593Smuzhiyun continue;
2221*4882a593Smuzhiyun
2222*4882a593Smuzhiyun ret = __mlx4_ib_alloc_diag_counters(ibdev, &diag[i].name,
2223*4882a593Smuzhiyun &diag[i].offset,
2224*4882a593Smuzhiyun &diag[i].num_counters, i);
2225*4882a593Smuzhiyun if (ret)
2226*4882a593Smuzhiyun goto err_alloc;
2227*4882a593Smuzhiyun
2228*4882a593Smuzhiyun mlx4_ib_fill_diag_counters(ibdev, diag[i].name,
2229*4882a593Smuzhiyun diag[i].offset, i);
2230*4882a593Smuzhiyun }
2231*4882a593Smuzhiyun
2232*4882a593Smuzhiyun ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_hw_stats_ops);
2233*4882a593Smuzhiyun
2234*4882a593Smuzhiyun return 0;
2235*4882a593Smuzhiyun
2236*4882a593Smuzhiyun err_alloc:
2237*4882a593Smuzhiyun if (i) {
2238*4882a593Smuzhiyun kfree(diag[i - 1].name);
2239*4882a593Smuzhiyun kfree(diag[i - 1].offset);
2240*4882a593Smuzhiyun }
2241*4882a593Smuzhiyun
2242*4882a593Smuzhiyun return ret;
2243*4882a593Smuzhiyun }
2244*4882a593Smuzhiyun
mlx4_ib_diag_cleanup(struct mlx4_ib_dev * ibdev)2245*4882a593Smuzhiyun static void mlx4_ib_diag_cleanup(struct mlx4_ib_dev *ibdev)
2246*4882a593Smuzhiyun {
2247*4882a593Smuzhiyun int i;
2248*4882a593Smuzhiyun
2249*4882a593Smuzhiyun for (i = 0; i < MLX4_DIAG_COUNTERS_TYPES; i++) {
2250*4882a593Smuzhiyun kfree(ibdev->diag_counters[i].offset);
2251*4882a593Smuzhiyun kfree(ibdev->diag_counters[i].name);
2252*4882a593Smuzhiyun }
2253*4882a593Smuzhiyun }
2254*4882a593Smuzhiyun
2255*4882a593Smuzhiyun #define MLX4_IB_INVALID_MAC ((u64)-1)
mlx4_ib_update_qps(struct mlx4_ib_dev * ibdev,struct net_device * dev,int port)2256*4882a593Smuzhiyun static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
2257*4882a593Smuzhiyun struct net_device *dev,
2258*4882a593Smuzhiyun int port)
2259*4882a593Smuzhiyun {
2260*4882a593Smuzhiyun u64 new_smac = 0;
2261*4882a593Smuzhiyun u64 release_mac = MLX4_IB_INVALID_MAC;
2262*4882a593Smuzhiyun struct mlx4_ib_qp *qp;
2263*4882a593Smuzhiyun
2264*4882a593Smuzhiyun read_lock(&dev_base_lock);
2265*4882a593Smuzhiyun new_smac = mlx4_mac_to_u64(dev->dev_addr);
2266*4882a593Smuzhiyun read_unlock(&dev_base_lock);
2267*4882a593Smuzhiyun
2268*4882a593Smuzhiyun atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
2269*4882a593Smuzhiyun
2270*4882a593Smuzhiyun /* no need for update QP1 and mac registration in non-SRIOV */
2271*4882a593Smuzhiyun if (!mlx4_is_mfunc(ibdev->dev))
2272*4882a593Smuzhiyun return;
2273*4882a593Smuzhiyun
2274*4882a593Smuzhiyun mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
2275*4882a593Smuzhiyun qp = ibdev->qp1_proxy[port - 1];
2276*4882a593Smuzhiyun if (qp) {
2277*4882a593Smuzhiyun int new_smac_index;
2278*4882a593Smuzhiyun u64 old_smac;
2279*4882a593Smuzhiyun struct mlx4_update_qp_params update_params;
2280*4882a593Smuzhiyun
2281*4882a593Smuzhiyun mutex_lock(&qp->mutex);
2282*4882a593Smuzhiyun old_smac = qp->pri.smac;
2283*4882a593Smuzhiyun if (new_smac == old_smac)
2284*4882a593Smuzhiyun goto unlock;
2285*4882a593Smuzhiyun
2286*4882a593Smuzhiyun new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
2287*4882a593Smuzhiyun
2288*4882a593Smuzhiyun if (new_smac_index < 0)
2289*4882a593Smuzhiyun goto unlock;
2290*4882a593Smuzhiyun
2291*4882a593Smuzhiyun update_params.smac_index = new_smac_index;
2292*4882a593Smuzhiyun if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
2293*4882a593Smuzhiyun &update_params)) {
2294*4882a593Smuzhiyun release_mac = new_smac;
2295*4882a593Smuzhiyun goto unlock;
2296*4882a593Smuzhiyun }
2297*4882a593Smuzhiyun /* if old port was zero, no mac was yet registered for this QP */
2298*4882a593Smuzhiyun if (qp->pri.smac_port)
2299*4882a593Smuzhiyun release_mac = old_smac;
2300*4882a593Smuzhiyun qp->pri.smac = new_smac;
2301*4882a593Smuzhiyun qp->pri.smac_port = port;
2302*4882a593Smuzhiyun qp->pri.smac_index = new_smac_index;
2303*4882a593Smuzhiyun }
2304*4882a593Smuzhiyun
2305*4882a593Smuzhiyun unlock:
2306*4882a593Smuzhiyun if (release_mac != MLX4_IB_INVALID_MAC)
2307*4882a593Smuzhiyun mlx4_unregister_mac(ibdev->dev, port, release_mac);
2308*4882a593Smuzhiyun if (qp)
2309*4882a593Smuzhiyun mutex_unlock(&qp->mutex);
2310*4882a593Smuzhiyun mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
2311*4882a593Smuzhiyun }
2312*4882a593Smuzhiyun
mlx4_ib_scan_netdevs(struct mlx4_ib_dev * ibdev,struct net_device * dev,unsigned long event)2313*4882a593Smuzhiyun static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
2314*4882a593Smuzhiyun struct net_device *dev,
2315*4882a593Smuzhiyun unsigned long event)
2316*4882a593Smuzhiyun
2317*4882a593Smuzhiyun {
2318*4882a593Smuzhiyun struct mlx4_ib_iboe *iboe;
2319*4882a593Smuzhiyun int update_qps_port = -1;
2320*4882a593Smuzhiyun int port;
2321*4882a593Smuzhiyun
2322*4882a593Smuzhiyun ASSERT_RTNL();
2323*4882a593Smuzhiyun
2324*4882a593Smuzhiyun iboe = &ibdev->iboe;
2325*4882a593Smuzhiyun
2326*4882a593Smuzhiyun spin_lock_bh(&iboe->lock);
2327*4882a593Smuzhiyun mlx4_foreach_ib_transport_port(port, ibdev->dev) {
2328*4882a593Smuzhiyun
2329*4882a593Smuzhiyun iboe->netdevs[port - 1] =
2330*4882a593Smuzhiyun mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
2331*4882a593Smuzhiyun
2332*4882a593Smuzhiyun if (dev == iboe->netdevs[port - 1] &&
2333*4882a593Smuzhiyun (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
2334*4882a593Smuzhiyun event == NETDEV_UP || event == NETDEV_CHANGE))
2335*4882a593Smuzhiyun update_qps_port = port;
2336*4882a593Smuzhiyun
2337*4882a593Smuzhiyun if (dev == iboe->netdevs[port - 1] &&
2338*4882a593Smuzhiyun (event == NETDEV_UP || event == NETDEV_DOWN)) {
2339*4882a593Smuzhiyun enum ib_port_state port_state;
2340*4882a593Smuzhiyun struct ib_event ibev = { };
2341*4882a593Smuzhiyun
2342*4882a593Smuzhiyun if (ib_get_cached_port_state(&ibdev->ib_dev, port,
2343*4882a593Smuzhiyun &port_state))
2344*4882a593Smuzhiyun continue;
2345*4882a593Smuzhiyun
2346*4882a593Smuzhiyun if (event == NETDEV_UP &&
2347*4882a593Smuzhiyun (port_state != IB_PORT_ACTIVE ||
2348*4882a593Smuzhiyun iboe->last_port_state[port - 1] != IB_PORT_DOWN))
2349*4882a593Smuzhiyun continue;
2350*4882a593Smuzhiyun if (event == NETDEV_DOWN &&
2351*4882a593Smuzhiyun (port_state != IB_PORT_DOWN ||
2352*4882a593Smuzhiyun iboe->last_port_state[port - 1] != IB_PORT_ACTIVE))
2353*4882a593Smuzhiyun continue;
2354*4882a593Smuzhiyun iboe->last_port_state[port - 1] = port_state;
2355*4882a593Smuzhiyun
2356*4882a593Smuzhiyun ibev.device = &ibdev->ib_dev;
2357*4882a593Smuzhiyun ibev.element.port_num = port;
2358*4882a593Smuzhiyun ibev.event = event == NETDEV_UP ? IB_EVENT_PORT_ACTIVE :
2359*4882a593Smuzhiyun IB_EVENT_PORT_ERR;
2360*4882a593Smuzhiyun ib_dispatch_event(&ibev);
2361*4882a593Smuzhiyun }
2362*4882a593Smuzhiyun
2363*4882a593Smuzhiyun }
2364*4882a593Smuzhiyun spin_unlock_bh(&iboe->lock);
2365*4882a593Smuzhiyun
2366*4882a593Smuzhiyun if (update_qps_port > 0)
2367*4882a593Smuzhiyun mlx4_ib_update_qps(ibdev, dev, update_qps_port);
2368*4882a593Smuzhiyun }
2369*4882a593Smuzhiyun
mlx4_ib_netdev_event(struct notifier_block * this,unsigned long event,void * ptr)2370*4882a593Smuzhiyun static int mlx4_ib_netdev_event(struct notifier_block *this,
2371*4882a593Smuzhiyun unsigned long event, void *ptr)
2372*4882a593Smuzhiyun {
2373*4882a593Smuzhiyun struct net_device *dev = netdev_notifier_info_to_dev(ptr);
2374*4882a593Smuzhiyun struct mlx4_ib_dev *ibdev;
2375*4882a593Smuzhiyun
2376*4882a593Smuzhiyun if (!net_eq(dev_net(dev), &init_net))
2377*4882a593Smuzhiyun return NOTIFY_DONE;
2378*4882a593Smuzhiyun
2379*4882a593Smuzhiyun ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
2380*4882a593Smuzhiyun mlx4_ib_scan_netdevs(ibdev, dev, event);
2381*4882a593Smuzhiyun
2382*4882a593Smuzhiyun return NOTIFY_DONE;
2383*4882a593Smuzhiyun }
2384*4882a593Smuzhiyun
init_pkeys(struct mlx4_ib_dev * ibdev)2385*4882a593Smuzhiyun static void init_pkeys(struct mlx4_ib_dev *ibdev)
2386*4882a593Smuzhiyun {
2387*4882a593Smuzhiyun int port;
2388*4882a593Smuzhiyun int slave;
2389*4882a593Smuzhiyun int i;
2390*4882a593Smuzhiyun
2391*4882a593Smuzhiyun if (mlx4_is_master(ibdev->dev)) {
2392*4882a593Smuzhiyun for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
2393*4882a593Smuzhiyun ++slave) {
2394*4882a593Smuzhiyun for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2395*4882a593Smuzhiyun for (i = 0;
2396*4882a593Smuzhiyun i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2397*4882a593Smuzhiyun ++i) {
2398*4882a593Smuzhiyun ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
2399*4882a593Smuzhiyun /* master has the identity virt2phys pkey mapping */
2400*4882a593Smuzhiyun (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
2401*4882a593Smuzhiyun ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
2402*4882a593Smuzhiyun mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
2403*4882a593Smuzhiyun ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
2404*4882a593Smuzhiyun }
2405*4882a593Smuzhiyun }
2406*4882a593Smuzhiyun }
2407*4882a593Smuzhiyun /* initialize pkey cache */
2408*4882a593Smuzhiyun for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
2409*4882a593Smuzhiyun for (i = 0;
2410*4882a593Smuzhiyun i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
2411*4882a593Smuzhiyun ++i)
2412*4882a593Smuzhiyun ibdev->pkeys.phys_pkey_cache[port-1][i] =
2413*4882a593Smuzhiyun (i) ? 0 : 0xFFFF;
2414*4882a593Smuzhiyun }
2415*4882a593Smuzhiyun }
2416*4882a593Smuzhiyun }
2417*4882a593Smuzhiyun
mlx4_ib_alloc_eqs(struct mlx4_dev * dev,struct mlx4_ib_dev * ibdev)2418*4882a593Smuzhiyun static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2419*4882a593Smuzhiyun {
2420*4882a593Smuzhiyun int i, j, eq = 0, total_eqs = 0;
2421*4882a593Smuzhiyun
2422*4882a593Smuzhiyun ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
2423*4882a593Smuzhiyun sizeof(ibdev->eq_table[0]), GFP_KERNEL);
2424*4882a593Smuzhiyun if (!ibdev->eq_table)
2425*4882a593Smuzhiyun return;
2426*4882a593Smuzhiyun
2427*4882a593Smuzhiyun for (i = 1; i <= dev->caps.num_ports; i++) {
2428*4882a593Smuzhiyun for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
2429*4882a593Smuzhiyun j++, total_eqs++) {
2430*4882a593Smuzhiyun if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
2431*4882a593Smuzhiyun continue;
2432*4882a593Smuzhiyun ibdev->eq_table[eq] = total_eqs;
2433*4882a593Smuzhiyun if (!mlx4_assign_eq(dev, i,
2434*4882a593Smuzhiyun &ibdev->eq_table[eq]))
2435*4882a593Smuzhiyun eq++;
2436*4882a593Smuzhiyun else
2437*4882a593Smuzhiyun ibdev->eq_table[eq] = -1;
2438*4882a593Smuzhiyun }
2439*4882a593Smuzhiyun }
2440*4882a593Smuzhiyun
2441*4882a593Smuzhiyun for (i = eq; i < dev->caps.num_comp_vectors;
2442*4882a593Smuzhiyun ibdev->eq_table[i++] = -1)
2443*4882a593Smuzhiyun ;
2444*4882a593Smuzhiyun
2445*4882a593Smuzhiyun /* Advertise the new number of EQs to clients */
2446*4882a593Smuzhiyun ibdev->ib_dev.num_comp_vectors = eq;
2447*4882a593Smuzhiyun }
2448*4882a593Smuzhiyun
mlx4_ib_free_eqs(struct mlx4_dev * dev,struct mlx4_ib_dev * ibdev)2449*4882a593Smuzhiyun static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
2450*4882a593Smuzhiyun {
2451*4882a593Smuzhiyun int i;
2452*4882a593Smuzhiyun int total_eqs = ibdev->ib_dev.num_comp_vectors;
2453*4882a593Smuzhiyun
2454*4882a593Smuzhiyun /* no eqs were allocated */
2455*4882a593Smuzhiyun if (!ibdev->eq_table)
2456*4882a593Smuzhiyun return;
2457*4882a593Smuzhiyun
2458*4882a593Smuzhiyun /* Reset the advertised EQ number */
2459*4882a593Smuzhiyun ibdev->ib_dev.num_comp_vectors = 0;
2460*4882a593Smuzhiyun
2461*4882a593Smuzhiyun for (i = 0; i < total_eqs; i++)
2462*4882a593Smuzhiyun mlx4_release_eq(dev, ibdev->eq_table[i]);
2463*4882a593Smuzhiyun
2464*4882a593Smuzhiyun kfree(ibdev->eq_table);
2465*4882a593Smuzhiyun ibdev->eq_table = NULL;
2466*4882a593Smuzhiyun }
2467*4882a593Smuzhiyun
mlx4_port_immutable(struct ib_device * ibdev,u8 port_num,struct ib_port_immutable * immutable)2468*4882a593Smuzhiyun static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
2469*4882a593Smuzhiyun struct ib_port_immutable *immutable)
2470*4882a593Smuzhiyun {
2471*4882a593Smuzhiyun struct ib_port_attr attr;
2472*4882a593Smuzhiyun struct mlx4_ib_dev *mdev = to_mdev(ibdev);
2473*4882a593Smuzhiyun int err;
2474*4882a593Smuzhiyun
2475*4882a593Smuzhiyun if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND) {
2476*4882a593Smuzhiyun immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
2477*4882a593Smuzhiyun immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2478*4882a593Smuzhiyun } else {
2479*4882a593Smuzhiyun if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)
2480*4882a593Smuzhiyun immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
2481*4882a593Smuzhiyun if (mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2)
2482*4882a593Smuzhiyun immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE |
2483*4882a593Smuzhiyun RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
2484*4882a593Smuzhiyun immutable->core_cap_flags |= RDMA_CORE_PORT_RAW_PACKET;
2485*4882a593Smuzhiyun if (immutable->core_cap_flags & (RDMA_CORE_PORT_IBA_ROCE |
2486*4882a593Smuzhiyun RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP))
2487*4882a593Smuzhiyun immutable->max_mad_size = IB_MGMT_MAD_SIZE;
2488*4882a593Smuzhiyun }
2489*4882a593Smuzhiyun
2490*4882a593Smuzhiyun err = ib_query_port(ibdev, port_num, &attr);
2491*4882a593Smuzhiyun if (err)
2492*4882a593Smuzhiyun return err;
2493*4882a593Smuzhiyun
2494*4882a593Smuzhiyun immutable->pkey_tbl_len = attr.pkey_tbl_len;
2495*4882a593Smuzhiyun immutable->gid_tbl_len = attr.gid_tbl_len;
2496*4882a593Smuzhiyun
2497*4882a593Smuzhiyun return 0;
2498*4882a593Smuzhiyun }
2499*4882a593Smuzhiyun
get_fw_ver_str(struct ib_device * device,char * str)2500*4882a593Smuzhiyun static void get_fw_ver_str(struct ib_device *device, char *str)
2501*4882a593Smuzhiyun {
2502*4882a593Smuzhiyun struct mlx4_ib_dev *dev =
2503*4882a593Smuzhiyun container_of(device, struct mlx4_ib_dev, ib_dev);
2504*4882a593Smuzhiyun snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d",
2505*4882a593Smuzhiyun (int) (dev->dev->caps.fw_ver >> 32),
2506*4882a593Smuzhiyun (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
2507*4882a593Smuzhiyun (int) dev->dev->caps.fw_ver & 0xffff);
2508*4882a593Smuzhiyun }
2509*4882a593Smuzhiyun
2510*4882a593Smuzhiyun static const struct ib_device_ops mlx4_ib_dev_ops = {
2511*4882a593Smuzhiyun .owner = THIS_MODULE,
2512*4882a593Smuzhiyun .driver_id = RDMA_DRIVER_MLX4,
2513*4882a593Smuzhiyun .uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION,
2514*4882a593Smuzhiyun
2515*4882a593Smuzhiyun .add_gid = mlx4_ib_add_gid,
2516*4882a593Smuzhiyun .alloc_mr = mlx4_ib_alloc_mr,
2517*4882a593Smuzhiyun .alloc_pd = mlx4_ib_alloc_pd,
2518*4882a593Smuzhiyun .alloc_ucontext = mlx4_ib_alloc_ucontext,
2519*4882a593Smuzhiyun .attach_mcast = mlx4_ib_mcg_attach,
2520*4882a593Smuzhiyun .create_ah = mlx4_ib_create_ah,
2521*4882a593Smuzhiyun .create_cq = mlx4_ib_create_cq,
2522*4882a593Smuzhiyun .create_qp = mlx4_ib_create_qp,
2523*4882a593Smuzhiyun .create_srq = mlx4_ib_create_srq,
2524*4882a593Smuzhiyun .dealloc_pd = mlx4_ib_dealloc_pd,
2525*4882a593Smuzhiyun .dealloc_ucontext = mlx4_ib_dealloc_ucontext,
2526*4882a593Smuzhiyun .del_gid = mlx4_ib_del_gid,
2527*4882a593Smuzhiyun .dereg_mr = mlx4_ib_dereg_mr,
2528*4882a593Smuzhiyun .destroy_ah = mlx4_ib_destroy_ah,
2529*4882a593Smuzhiyun .destroy_cq = mlx4_ib_destroy_cq,
2530*4882a593Smuzhiyun .destroy_qp = mlx4_ib_destroy_qp,
2531*4882a593Smuzhiyun .destroy_srq = mlx4_ib_destroy_srq,
2532*4882a593Smuzhiyun .detach_mcast = mlx4_ib_mcg_detach,
2533*4882a593Smuzhiyun .disassociate_ucontext = mlx4_ib_disassociate_ucontext,
2534*4882a593Smuzhiyun .drain_rq = mlx4_ib_drain_rq,
2535*4882a593Smuzhiyun .drain_sq = mlx4_ib_drain_sq,
2536*4882a593Smuzhiyun .get_dev_fw_str = get_fw_ver_str,
2537*4882a593Smuzhiyun .get_dma_mr = mlx4_ib_get_dma_mr,
2538*4882a593Smuzhiyun .get_link_layer = mlx4_ib_port_link_layer,
2539*4882a593Smuzhiyun .get_netdev = mlx4_ib_get_netdev,
2540*4882a593Smuzhiyun .get_port_immutable = mlx4_port_immutable,
2541*4882a593Smuzhiyun .map_mr_sg = mlx4_ib_map_mr_sg,
2542*4882a593Smuzhiyun .mmap = mlx4_ib_mmap,
2543*4882a593Smuzhiyun .modify_cq = mlx4_ib_modify_cq,
2544*4882a593Smuzhiyun .modify_device = mlx4_ib_modify_device,
2545*4882a593Smuzhiyun .modify_port = mlx4_ib_modify_port,
2546*4882a593Smuzhiyun .modify_qp = mlx4_ib_modify_qp,
2547*4882a593Smuzhiyun .modify_srq = mlx4_ib_modify_srq,
2548*4882a593Smuzhiyun .poll_cq = mlx4_ib_poll_cq,
2549*4882a593Smuzhiyun .post_recv = mlx4_ib_post_recv,
2550*4882a593Smuzhiyun .post_send = mlx4_ib_post_send,
2551*4882a593Smuzhiyun .post_srq_recv = mlx4_ib_post_srq_recv,
2552*4882a593Smuzhiyun .process_mad = mlx4_ib_process_mad,
2553*4882a593Smuzhiyun .query_ah = mlx4_ib_query_ah,
2554*4882a593Smuzhiyun .query_device = mlx4_ib_query_device,
2555*4882a593Smuzhiyun .query_gid = mlx4_ib_query_gid,
2556*4882a593Smuzhiyun .query_pkey = mlx4_ib_query_pkey,
2557*4882a593Smuzhiyun .query_port = mlx4_ib_query_port,
2558*4882a593Smuzhiyun .query_qp = mlx4_ib_query_qp,
2559*4882a593Smuzhiyun .query_srq = mlx4_ib_query_srq,
2560*4882a593Smuzhiyun .reg_user_mr = mlx4_ib_reg_user_mr,
2561*4882a593Smuzhiyun .req_notify_cq = mlx4_ib_arm_cq,
2562*4882a593Smuzhiyun .rereg_user_mr = mlx4_ib_rereg_user_mr,
2563*4882a593Smuzhiyun .resize_cq = mlx4_ib_resize_cq,
2564*4882a593Smuzhiyun
2565*4882a593Smuzhiyun INIT_RDMA_OBJ_SIZE(ib_ah, mlx4_ib_ah, ibah),
2566*4882a593Smuzhiyun INIT_RDMA_OBJ_SIZE(ib_cq, mlx4_ib_cq, ibcq),
2567*4882a593Smuzhiyun INIT_RDMA_OBJ_SIZE(ib_pd, mlx4_ib_pd, ibpd),
2568*4882a593Smuzhiyun INIT_RDMA_OBJ_SIZE(ib_srq, mlx4_ib_srq, ibsrq),
2569*4882a593Smuzhiyun INIT_RDMA_OBJ_SIZE(ib_ucontext, mlx4_ib_ucontext, ibucontext),
2570*4882a593Smuzhiyun };
2571*4882a593Smuzhiyun
2572*4882a593Smuzhiyun static const struct ib_device_ops mlx4_ib_dev_wq_ops = {
2573*4882a593Smuzhiyun .create_rwq_ind_table = mlx4_ib_create_rwq_ind_table,
2574*4882a593Smuzhiyun .create_wq = mlx4_ib_create_wq,
2575*4882a593Smuzhiyun .destroy_rwq_ind_table = mlx4_ib_destroy_rwq_ind_table,
2576*4882a593Smuzhiyun .destroy_wq = mlx4_ib_destroy_wq,
2577*4882a593Smuzhiyun .modify_wq = mlx4_ib_modify_wq,
2578*4882a593Smuzhiyun
2579*4882a593Smuzhiyun INIT_RDMA_OBJ_SIZE(ib_rwq_ind_table, mlx4_ib_rwq_ind_table,
2580*4882a593Smuzhiyun ib_rwq_ind_tbl),
2581*4882a593Smuzhiyun };
2582*4882a593Smuzhiyun
2583*4882a593Smuzhiyun static const struct ib_device_ops mlx4_ib_dev_mw_ops = {
2584*4882a593Smuzhiyun .alloc_mw = mlx4_ib_alloc_mw,
2585*4882a593Smuzhiyun .dealloc_mw = mlx4_ib_dealloc_mw,
2586*4882a593Smuzhiyun
2587*4882a593Smuzhiyun INIT_RDMA_OBJ_SIZE(ib_mw, mlx4_ib_mw, ibmw),
2588*4882a593Smuzhiyun };
2589*4882a593Smuzhiyun
2590*4882a593Smuzhiyun static const struct ib_device_ops mlx4_ib_dev_xrc_ops = {
2591*4882a593Smuzhiyun .alloc_xrcd = mlx4_ib_alloc_xrcd,
2592*4882a593Smuzhiyun .dealloc_xrcd = mlx4_ib_dealloc_xrcd,
2593*4882a593Smuzhiyun
2594*4882a593Smuzhiyun INIT_RDMA_OBJ_SIZE(ib_xrcd, mlx4_ib_xrcd, ibxrcd),
2595*4882a593Smuzhiyun };
2596*4882a593Smuzhiyun
2597*4882a593Smuzhiyun static const struct ib_device_ops mlx4_ib_dev_fs_ops = {
2598*4882a593Smuzhiyun .create_flow = mlx4_ib_create_flow,
2599*4882a593Smuzhiyun .destroy_flow = mlx4_ib_destroy_flow,
2600*4882a593Smuzhiyun };
2601*4882a593Smuzhiyun
mlx4_ib_add(struct mlx4_dev * dev)2602*4882a593Smuzhiyun static void *mlx4_ib_add(struct mlx4_dev *dev)
2603*4882a593Smuzhiyun {
2604*4882a593Smuzhiyun struct mlx4_ib_dev *ibdev;
2605*4882a593Smuzhiyun int num_ports = 0;
2606*4882a593Smuzhiyun int i, j;
2607*4882a593Smuzhiyun int err;
2608*4882a593Smuzhiyun struct mlx4_ib_iboe *iboe;
2609*4882a593Smuzhiyun int ib_num_ports = 0;
2610*4882a593Smuzhiyun int num_req_counters;
2611*4882a593Smuzhiyun int allocated;
2612*4882a593Smuzhiyun u32 counter_index;
2613*4882a593Smuzhiyun struct counter_index *new_counter_index = NULL;
2614*4882a593Smuzhiyun
2615*4882a593Smuzhiyun pr_info_once("%s", mlx4_ib_version);
2616*4882a593Smuzhiyun
2617*4882a593Smuzhiyun num_ports = 0;
2618*4882a593Smuzhiyun mlx4_foreach_ib_transport_port(i, dev)
2619*4882a593Smuzhiyun num_ports++;
2620*4882a593Smuzhiyun
2621*4882a593Smuzhiyun /* No point in registering a device with no ports... */
2622*4882a593Smuzhiyun if (num_ports == 0)
2623*4882a593Smuzhiyun return NULL;
2624*4882a593Smuzhiyun
2625*4882a593Smuzhiyun ibdev = ib_alloc_device(mlx4_ib_dev, ib_dev);
2626*4882a593Smuzhiyun if (!ibdev) {
2627*4882a593Smuzhiyun dev_err(&dev->persist->pdev->dev,
2628*4882a593Smuzhiyun "Device struct alloc failed\n");
2629*4882a593Smuzhiyun return NULL;
2630*4882a593Smuzhiyun }
2631*4882a593Smuzhiyun
2632*4882a593Smuzhiyun iboe = &ibdev->iboe;
2633*4882a593Smuzhiyun
2634*4882a593Smuzhiyun if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
2635*4882a593Smuzhiyun goto err_dealloc;
2636*4882a593Smuzhiyun
2637*4882a593Smuzhiyun if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
2638*4882a593Smuzhiyun goto err_pd;
2639*4882a593Smuzhiyun
2640*4882a593Smuzhiyun ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
2641*4882a593Smuzhiyun PAGE_SIZE);
2642*4882a593Smuzhiyun if (!ibdev->uar_map)
2643*4882a593Smuzhiyun goto err_uar;
2644*4882a593Smuzhiyun MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
2645*4882a593Smuzhiyun
2646*4882a593Smuzhiyun ibdev->dev = dev;
2647*4882a593Smuzhiyun ibdev->bond_next_port = 0;
2648*4882a593Smuzhiyun
2649*4882a593Smuzhiyun ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
2650*4882a593Smuzhiyun ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
2651*4882a593Smuzhiyun ibdev->num_ports = num_ports;
2652*4882a593Smuzhiyun ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
2653*4882a593Smuzhiyun 1 : ibdev->num_ports;
2654*4882a593Smuzhiyun ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
2655*4882a593Smuzhiyun ibdev->ib_dev.dev.parent = &dev->persist->pdev->dev;
2656*4882a593Smuzhiyun
2657*4882a593Smuzhiyun ibdev->ib_dev.uverbs_cmd_mask =
2658*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
2659*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
2660*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
2661*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
2662*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
2663*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_REG_MR) |
2664*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_REREG_MR) |
2665*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
2666*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
2667*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
2668*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
2669*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
2670*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
2671*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
2672*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
2673*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
2674*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
2675*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
2676*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
2677*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
2678*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
2679*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
2680*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
2681*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_OPEN_QP);
2682*4882a593Smuzhiyun
2683*4882a593Smuzhiyun ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_ops);
2684*4882a593Smuzhiyun ibdev->ib_dev.uverbs_ex_cmd_mask |=
2685*4882a593Smuzhiyun (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ) |
2686*4882a593Smuzhiyun (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
2687*4882a593Smuzhiyun (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
2688*4882a593Smuzhiyun (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
2689*4882a593Smuzhiyun
2690*4882a593Smuzhiyun if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS) &&
2691*4882a593Smuzhiyun ((mlx4_ib_port_link_layer(&ibdev->ib_dev, 1) ==
2692*4882a593Smuzhiyun IB_LINK_LAYER_ETHERNET) ||
2693*4882a593Smuzhiyun (mlx4_ib_port_link_layer(&ibdev->ib_dev, 2) ==
2694*4882a593Smuzhiyun IB_LINK_LAYER_ETHERNET))) {
2695*4882a593Smuzhiyun ibdev->ib_dev.uverbs_ex_cmd_mask |=
2696*4882a593Smuzhiyun (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
2697*4882a593Smuzhiyun (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
2698*4882a593Smuzhiyun (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
2699*4882a593Smuzhiyun (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
2700*4882a593Smuzhiyun (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
2701*4882a593Smuzhiyun ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_wq_ops);
2702*4882a593Smuzhiyun }
2703*4882a593Smuzhiyun
2704*4882a593Smuzhiyun if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2705*4882a593Smuzhiyun dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
2706*4882a593Smuzhiyun ibdev->ib_dev.uverbs_cmd_mask |=
2707*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
2708*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
2709*4882a593Smuzhiyun ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_mw_ops);
2710*4882a593Smuzhiyun }
2711*4882a593Smuzhiyun
2712*4882a593Smuzhiyun if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
2713*4882a593Smuzhiyun ibdev->ib_dev.uverbs_cmd_mask |=
2714*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
2715*4882a593Smuzhiyun (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
2716*4882a593Smuzhiyun ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_xrc_ops);
2717*4882a593Smuzhiyun }
2718*4882a593Smuzhiyun
2719*4882a593Smuzhiyun if (check_flow_steering_support(dev)) {
2720*4882a593Smuzhiyun ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
2721*4882a593Smuzhiyun ibdev->ib_dev.uverbs_ex_cmd_mask |=
2722*4882a593Smuzhiyun (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
2723*4882a593Smuzhiyun (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
2724*4882a593Smuzhiyun ib_set_device_ops(&ibdev->ib_dev, &mlx4_ib_dev_fs_ops);
2725*4882a593Smuzhiyun }
2726*4882a593Smuzhiyun
2727*4882a593Smuzhiyun if (!dev->caps.userspace_caps)
2728*4882a593Smuzhiyun ibdev->ib_dev.ops.uverbs_abi_ver =
2729*4882a593Smuzhiyun MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
2730*4882a593Smuzhiyun
2731*4882a593Smuzhiyun mlx4_ib_alloc_eqs(dev, ibdev);
2732*4882a593Smuzhiyun
2733*4882a593Smuzhiyun spin_lock_init(&iboe->lock);
2734*4882a593Smuzhiyun
2735*4882a593Smuzhiyun if (init_node_data(ibdev))
2736*4882a593Smuzhiyun goto err_map;
2737*4882a593Smuzhiyun mlx4_init_sl2vl_tbl(ibdev);
2738*4882a593Smuzhiyun
2739*4882a593Smuzhiyun for (i = 0; i < ibdev->num_ports; ++i) {
2740*4882a593Smuzhiyun mutex_init(&ibdev->counters_table[i].mutex);
2741*4882a593Smuzhiyun INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
2742*4882a593Smuzhiyun iboe->last_port_state[i] = IB_PORT_DOWN;
2743*4882a593Smuzhiyun }
2744*4882a593Smuzhiyun
2745*4882a593Smuzhiyun num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
2746*4882a593Smuzhiyun for (i = 0; i < num_req_counters; ++i) {
2747*4882a593Smuzhiyun mutex_init(&ibdev->qp1_proxy_lock[i]);
2748*4882a593Smuzhiyun allocated = 0;
2749*4882a593Smuzhiyun if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
2750*4882a593Smuzhiyun IB_LINK_LAYER_ETHERNET) {
2751*4882a593Smuzhiyun err = mlx4_counter_alloc(ibdev->dev, &counter_index,
2752*4882a593Smuzhiyun MLX4_RES_USAGE_DRIVER);
2753*4882a593Smuzhiyun /* if failed to allocate a new counter, use default */
2754*4882a593Smuzhiyun if (err)
2755*4882a593Smuzhiyun counter_index =
2756*4882a593Smuzhiyun mlx4_get_default_counter_index(dev,
2757*4882a593Smuzhiyun i + 1);
2758*4882a593Smuzhiyun else
2759*4882a593Smuzhiyun allocated = 1;
2760*4882a593Smuzhiyun } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
2761*4882a593Smuzhiyun counter_index = mlx4_get_default_counter_index(dev,
2762*4882a593Smuzhiyun i + 1);
2763*4882a593Smuzhiyun }
2764*4882a593Smuzhiyun new_counter_index = kmalloc(sizeof(*new_counter_index),
2765*4882a593Smuzhiyun GFP_KERNEL);
2766*4882a593Smuzhiyun if (!new_counter_index) {
2767*4882a593Smuzhiyun if (allocated)
2768*4882a593Smuzhiyun mlx4_counter_free(ibdev->dev, counter_index);
2769*4882a593Smuzhiyun goto err_counter;
2770*4882a593Smuzhiyun }
2771*4882a593Smuzhiyun new_counter_index->index = counter_index;
2772*4882a593Smuzhiyun new_counter_index->allocated = allocated;
2773*4882a593Smuzhiyun list_add_tail(&new_counter_index->list,
2774*4882a593Smuzhiyun &ibdev->counters_table[i].counters_list);
2775*4882a593Smuzhiyun ibdev->counters_table[i].default_counter = counter_index;
2776*4882a593Smuzhiyun pr_info("counter index %d for port %d allocated %d\n",
2777*4882a593Smuzhiyun counter_index, i + 1, allocated);
2778*4882a593Smuzhiyun }
2779*4882a593Smuzhiyun if (mlx4_is_bonded(dev))
2780*4882a593Smuzhiyun for (i = 1; i < ibdev->num_ports ; ++i) {
2781*4882a593Smuzhiyun new_counter_index =
2782*4882a593Smuzhiyun kmalloc(sizeof(struct counter_index),
2783*4882a593Smuzhiyun GFP_KERNEL);
2784*4882a593Smuzhiyun if (!new_counter_index)
2785*4882a593Smuzhiyun goto err_counter;
2786*4882a593Smuzhiyun new_counter_index->index = counter_index;
2787*4882a593Smuzhiyun new_counter_index->allocated = 0;
2788*4882a593Smuzhiyun list_add_tail(&new_counter_index->list,
2789*4882a593Smuzhiyun &ibdev->counters_table[i].counters_list);
2790*4882a593Smuzhiyun ibdev->counters_table[i].default_counter =
2791*4882a593Smuzhiyun counter_index;
2792*4882a593Smuzhiyun }
2793*4882a593Smuzhiyun
2794*4882a593Smuzhiyun mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2795*4882a593Smuzhiyun ib_num_ports++;
2796*4882a593Smuzhiyun
2797*4882a593Smuzhiyun spin_lock_init(&ibdev->sm_lock);
2798*4882a593Smuzhiyun mutex_init(&ibdev->cap_mask_mutex);
2799*4882a593Smuzhiyun INIT_LIST_HEAD(&ibdev->qp_list);
2800*4882a593Smuzhiyun spin_lock_init(&ibdev->reset_flow_resource_lock);
2801*4882a593Smuzhiyun
2802*4882a593Smuzhiyun if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2803*4882a593Smuzhiyun ib_num_ports) {
2804*4882a593Smuzhiyun ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
2805*4882a593Smuzhiyun err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
2806*4882a593Smuzhiyun MLX4_IB_UC_STEER_QPN_ALIGN,
2807*4882a593Smuzhiyun &ibdev->steer_qpn_base, 0,
2808*4882a593Smuzhiyun MLX4_RES_USAGE_DRIVER);
2809*4882a593Smuzhiyun if (err)
2810*4882a593Smuzhiyun goto err_counter;
2811*4882a593Smuzhiyun
2812*4882a593Smuzhiyun ibdev->ib_uc_qpns_bitmap =
2813*4882a593Smuzhiyun kmalloc_array(BITS_TO_LONGS(ibdev->steer_qpn_count),
2814*4882a593Smuzhiyun sizeof(long),
2815*4882a593Smuzhiyun GFP_KERNEL);
2816*4882a593Smuzhiyun if (!ibdev->ib_uc_qpns_bitmap)
2817*4882a593Smuzhiyun goto err_steer_qp_release;
2818*4882a593Smuzhiyun
2819*4882a593Smuzhiyun if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) {
2820*4882a593Smuzhiyun bitmap_zero(ibdev->ib_uc_qpns_bitmap,
2821*4882a593Smuzhiyun ibdev->steer_qpn_count);
2822*4882a593Smuzhiyun err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
2823*4882a593Smuzhiyun dev, ibdev->steer_qpn_base,
2824*4882a593Smuzhiyun ibdev->steer_qpn_base +
2825*4882a593Smuzhiyun ibdev->steer_qpn_count - 1);
2826*4882a593Smuzhiyun if (err)
2827*4882a593Smuzhiyun goto err_steer_free_bitmap;
2828*4882a593Smuzhiyun } else {
2829*4882a593Smuzhiyun bitmap_fill(ibdev->ib_uc_qpns_bitmap,
2830*4882a593Smuzhiyun ibdev->steer_qpn_count);
2831*4882a593Smuzhiyun }
2832*4882a593Smuzhiyun }
2833*4882a593Smuzhiyun
2834*4882a593Smuzhiyun for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
2835*4882a593Smuzhiyun atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
2836*4882a593Smuzhiyun
2837*4882a593Smuzhiyun if (mlx4_ib_alloc_diag_counters(ibdev))
2838*4882a593Smuzhiyun goto err_steer_free_bitmap;
2839*4882a593Smuzhiyun
2840*4882a593Smuzhiyun rdma_set_device_sysfs_group(&ibdev->ib_dev, &mlx4_attr_group);
2841*4882a593Smuzhiyun if (ib_register_device(&ibdev->ib_dev, "mlx4_%d",
2842*4882a593Smuzhiyun &dev->persist->pdev->dev))
2843*4882a593Smuzhiyun goto err_diag_counters;
2844*4882a593Smuzhiyun
2845*4882a593Smuzhiyun if (mlx4_ib_mad_init(ibdev))
2846*4882a593Smuzhiyun goto err_reg;
2847*4882a593Smuzhiyun
2848*4882a593Smuzhiyun if (mlx4_ib_init_sriov(ibdev))
2849*4882a593Smuzhiyun goto err_mad;
2850*4882a593Smuzhiyun
2851*4882a593Smuzhiyun if (!iboe->nb.notifier_call) {
2852*4882a593Smuzhiyun iboe->nb.notifier_call = mlx4_ib_netdev_event;
2853*4882a593Smuzhiyun err = register_netdevice_notifier(&iboe->nb);
2854*4882a593Smuzhiyun if (err) {
2855*4882a593Smuzhiyun iboe->nb.notifier_call = NULL;
2856*4882a593Smuzhiyun goto err_notif;
2857*4882a593Smuzhiyun }
2858*4882a593Smuzhiyun }
2859*4882a593Smuzhiyun if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
2860*4882a593Smuzhiyun err = mlx4_config_roce_v2_port(dev, ROCE_V2_UDP_DPORT);
2861*4882a593Smuzhiyun if (err)
2862*4882a593Smuzhiyun goto err_notif;
2863*4882a593Smuzhiyun }
2864*4882a593Smuzhiyun
2865*4882a593Smuzhiyun ibdev->ib_active = true;
2866*4882a593Smuzhiyun mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
2867*4882a593Smuzhiyun devlink_port_type_ib_set(mlx4_get_devlink_port(dev, i),
2868*4882a593Smuzhiyun &ibdev->ib_dev);
2869*4882a593Smuzhiyun
2870*4882a593Smuzhiyun if (mlx4_is_mfunc(ibdev->dev))
2871*4882a593Smuzhiyun init_pkeys(ibdev);
2872*4882a593Smuzhiyun
2873*4882a593Smuzhiyun /* create paravirt contexts for any VFs which are active */
2874*4882a593Smuzhiyun if (mlx4_is_master(ibdev->dev)) {
2875*4882a593Smuzhiyun for (j = 0; j < MLX4_MFUNC_MAX; j++) {
2876*4882a593Smuzhiyun if (j == mlx4_master_func_num(ibdev->dev))
2877*4882a593Smuzhiyun continue;
2878*4882a593Smuzhiyun if (mlx4_is_slave_active(ibdev->dev, j))
2879*4882a593Smuzhiyun do_slave_init(ibdev, j, 1);
2880*4882a593Smuzhiyun }
2881*4882a593Smuzhiyun }
2882*4882a593Smuzhiyun return ibdev;
2883*4882a593Smuzhiyun
2884*4882a593Smuzhiyun err_notif:
2885*4882a593Smuzhiyun if (ibdev->iboe.nb.notifier_call) {
2886*4882a593Smuzhiyun if (unregister_netdevice_notifier(&ibdev->iboe.nb))
2887*4882a593Smuzhiyun pr_warn("failure unregistering notifier\n");
2888*4882a593Smuzhiyun ibdev->iboe.nb.notifier_call = NULL;
2889*4882a593Smuzhiyun }
2890*4882a593Smuzhiyun flush_workqueue(wq);
2891*4882a593Smuzhiyun
2892*4882a593Smuzhiyun mlx4_ib_close_sriov(ibdev);
2893*4882a593Smuzhiyun
2894*4882a593Smuzhiyun err_mad:
2895*4882a593Smuzhiyun mlx4_ib_mad_cleanup(ibdev);
2896*4882a593Smuzhiyun
2897*4882a593Smuzhiyun err_reg:
2898*4882a593Smuzhiyun ib_unregister_device(&ibdev->ib_dev);
2899*4882a593Smuzhiyun
2900*4882a593Smuzhiyun err_diag_counters:
2901*4882a593Smuzhiyun mlx4_ib_diag_cleanup(ibdev);
2902*4882a593Smuzhiyun
2903*4882a593Smuzhiyun err_steer_free_bitmap:
2904*4882a593Smuzhiyun kfree(ibdev->ib_uc_qpns_bitmap);
2905*4882a593Smuzhiyun
2906*4882a593Smuzhiyun err_steer_qp_release:
2907*4882a593Smuzhiyun mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
2908*4882a593Smuzhiyun ibdev->steer_qpn_count);
2909*4882a593Smuzhiyun err_counter:
2910*4882a593Smuzhiyun for (i = 0; i < ibdev->num_ports; ++i)
2911*4882a593Smuzhiyun mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
2912*4882a593Smuzhiyun
2913*4882a593Smuzhiyun err_map:
2914*4882a593Smuzhiyun mlx4_ib_free_eqs(dev, ibdev);
2915*4882a593Smuzhiyun iounmap(ibdev->uar_map);
2916*4882a593Smuzhiyun
2917*4882a593Smuzhiyun err_uar:
2918*4882a593Smuzhiyun mlx4_uar_free(dev, &ibdev->priv_uar);
2919*4882a593Smuzhiyun
2920*4882a593Smuzhiyun err_pd:
2921*4882a593Smuzhiyun mlx4_pd_free(dev, ibdev->priv_pdn);
2922*4882a593Smuzhiyun
2923*4882a593Smuzhiyun err_dealloc:
2924*4882a593Smuzhiyun ib_dealloc_device(&ibdev->ib_dev);
2925*4882a593Smuzhiyun
2926*4882a593Smuzhiyun return NULL;
2927*4882a593Smuzhiyun }
2928*4882a593Smuzhiyun
mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev * dev,int count,int * qpn)2929*4882a593Smuzhiyun int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
2930*4882a593Smuzhiyun {
2931*4882a593Smuzhiyun int offset;
2932*4882a593Smuzhiyun
2933*4882a593Smuzhiyun WARN_ON(!dev->ib_uc_qpns_bitmap);
2934*4882a593Smuzhiyun
2935*4882a593Smuzhiyun offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
2936*4882a593Smuzhiyun dev->steer_qpn_count,
2937*4882a593Smuzhiyun get_count_order(count));
2938*4882a593Smuzhiyun if (offset < 0)
2939*4882a593Smuzhiyun return offset;
2940*4882a593Smuzhiyun
2941*4882a593Smuzhiyun *qpn = dev->steer_qpn_base + offset;
2942*4882a593Smuzhiyun return 0;
2943*4882a593Smuzhiyun }
2944*4882a593Smuzhiyun
mlx4_ib_steer_qp_free(struct mlx4_ib_dev * dev,u32 qpn,int count)2945*4882a593Smuzhiyun void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
2946*4882a593Smuzhiyun {
2947*4882a593Smuzhiyun if (!qpn ||
2948*4882a593Smuzhiyun dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
2949*4882a593Smuzhiyun return;
2950*4882a593Smuzhiyun
2951*4882a593Smuzhiyun if (WARN(qpn < dev->steer_qpn_base, "qpn = %u, steer_qpn_base = %u\n",
2952*4882a593Smuzhiyun qpn, dev->steer_qpn_base))
2953*4882a593Smuzhiyun /* not supposed to be here */
2954*4882a593Smuzhiyun return;
2955*4882a593Smuzhiyun
2956*4882a593Smuzhiyun bitmap_release_region(dev->ib_uc_qpns_bitmap,
2957*4882a593Smuzhiyun qpn - dev->steer_qpn_base,
2958*4882a593Smuzhiyun get_count_order(count));
2959*4882a593Smuzhiyun }
2960*4882a593Smuzhiyun
mlx4_ib_steer_qp_reg(struct mlx4_ib_dev * mdev,struct mlx4_ib_qp * mqp,int is_attach)2961*4882a593Smuzhiyun int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
2962*4882a593Smuzhiyun int is_attach)
2963*4882a593Smuzhiyun {
2964*4882a593Smuzhiyun int err;
2965*4882a593Smuzhiyun size_t flow_size;
2966*4882a593Smuzhiyun struct ib_flow_attr *flow = NULL;
2967*4882a593Smuzhiyun struct ib_flow_spec_ib *ib_spec;
2968*4882a593Smuzhiyun
2969*4882a593Smuzhiyun if (is_attach) {
2970*4882a593Smuzhiyun flow_size = sizeof(struct ib_flow_attr) +
2971*4882a593Smuzhiyun sizeof(struct ib_flow_spec_ib);
2972*4882a593Smuzhiyun flow = kzalloc(flow_size, GFP_KERNEL);
2973*4882a593Smuzhiyun if (!flow)
2974*4882a593Smuzhiyun return -ENOMEM;
2975*4882a593Smuzhiyun flow->port = mqp->port;
2976*4882a593Smuzhiyun flow->num_of_specs = 1;
2977*4882a593Smuzhiyun flow->size = flow_size;
2978*4882a593Smuzhiyun ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
2979*4882a593Smuzhiyun ib_spec->type = IB_FLOW_SPEC_IB;
2980*4882a593Smuzhiyun ib_spec->size = sizeof(struct ib_flow_spec_ib);
2981*4882a593Smuzhiyun /* Add an empty rule for IB L2 */
2982*4882a593Smuzhiyun memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
2983*4882a593Smuzhiyun
2984*4882a593Smuzhiyun err = __mlx4_ib_create_flow(&mqp->ibqp, flow, MLX4_DOMAIN_NIC,
2985*4882a593Smuzhiyun MLX4_FS_REGULAR, &mqp->reg_id);
2986*4882a593Smuzhiyun } else {
2987*4882a593Smuzhiyun err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
2988*4882a593Smuzhiyun }
2989*4882a593Smuzhiyun kfree(flow);
2990*4882a593Smuzhiyun return err;
2991*4882a593Smuzhiyun }
2992*4882a593Smuzhiyun
mlx4_ib_remove(struct mlx4_dev * dev,void * ibdev_ptr)2993*4882a593Smuzhiyun static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
2994*4882a593Smuzhiyun {
2995*4882a593Smuzhiyun struct mlx4_ib_dev *ibdev = ibdev_ptr;
2996*4882a593Smuzhiyun int p;
2997*4882a593Smuzhiyun int i;
2998*4882a593Smuzhiyun
2999*4882a593Smuzhiyun mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
3000*4882a593Smuzhiyun devlink_port_type_clear(mlx4_get_devlink_port(dev, i));
3001*4882a593Smuzhiyun ibdev->ib_active = false;
3002*4882a593Smuzhiyun flush_workqueue(wq);
3003*4882a593Smuzhiyun
3004*4882a593Smuzhiyun if (ibdev->iboe.nb.notifier_call) {
3005*4882a593Smuzhiyun if (unregister_netdevice_notifier(&ibdev->iboe.nb))
3006*4882a593Smuzhiyun pr_warn("failure unregistering notifier\n");
3007*4882a593Smuzhiyun ibdev->iboe.nb.notifier_call = NULL;
3008*4882a593Smuzhiyun }
3009*4882a593Smuzhiyun
3010*4882a593Smuzhiyun mlx4_ib_close_sriov(ibdev);
3011*4882a593Smuzhiyun mlx4_ib_mad_cleanup(ibdev);
3012*4882a593Smuzhiyun ib_unregister_device(&ibdev->ib_dev);
3013*4882a593Smuzhiyun mlx4_ib_diag_cleanup(ibdev);
3014*4882a593Smuzhiyun
3015*4882a593Smuzhiyun mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
3016*4882a593Smuzhiyun ibdev->steer_qpn_count);
3017*4882a593Smuzhiyun kfree(ibdev->ib_uc_qpns_bitmap);
3018*4882a593Smuzhiyun
3019*4882a593Smuzhiyun iounmap(ibdev->uar_map);
3020*4882a593Smuzhiyun for (p = 0; p < ibdev->num_ports; ++p)
3021*4882a593Smuzhiyun mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
3022*4882a593Smuzhiyun
3023*4882a593Smuzhiyun mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
3024*4882a593Smuzhiyun mlx4_CLOSE_PORT(dev, p);
3025*4882a593Smuzhiyun
3026*4882a593Smuzhiyun mlx4_ib_free_eqs(dev, ibdev);
3027*4882a593Smuzhiyun
3028*4882a593Smuzhiyun mlx4_uar_free(dev, &ibdev->priv_uar);
3029*4882a593Smuzhiyun mlx4_pd_free(dev, ibdev->priv_pdn);
3030*4882a593Smuzhiyun ib_dealloc_device(&ibdev->ib_dev);
3031*4882a593Smuzhiyun }
3032*4882a593Smuzhiyun
do_slave_init(struct mlx4_ib_dev * ibdev,int slave,int do_init)3033*4882a593Smuzhiyun static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
3034*4882a593Smuzhiyun {
3035*4882a593Smuzhiyun struct mlx4_ib_demux_work **dm = NULL;
3036*4882a593Smuzhiyun struct mlx4_dev *dev = ibdev->dev;
3037*4882a593Smuzhiyun int i;
3038*4882a593Smuzhiyun unsigned long flags;
3039*4882a593Smuzhiyun struct mlx4_active_ports actv_ports;
3040*4882a593Smuzhiyun unsigned int ports;
3041*4882a593Smuzhiyun unsigned int first_port;
3042*4882a593Smuzhiyun
3043*4882a593Smuzhiyun if (!mlx4_is_master(dev))
3044*4882a593Smuzhiyun return;
3045*4882a593Smuzhiyun
3046*4882a593Smuzhiyun actv_ports = mlx4_get_active_ports(dev, slave);
3047*4882a593Smuzhiyun ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
3048*4882a593Smuzhiyun first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
3049*4882a593Smuzhiyun
3050*4882a593Smuzhiyun dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
3051*4882a593Smuzhiyun if (!dm)
3052*4882a593Smuzhiyun return;
3053*4882a593Smuzhiyun
3054*4882a593Smuzhiyun for (i = 0; i < ports; i++) {
3055*4882a593Smuzhiyun dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
3056*4882a593Smuzhiyun if (!dm[i]) {
3057*4882a593Smuzhiyun while (--i >= 0)
3058*4882a593Smuzhiyun kfree(dm[i]);
3059*4882a593Smuzhiyun goto out;
3060*4882a593Smuzhiyun }
3061*4882a593Smuzhiyun INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
3062*4882a593Smuzhiyun dm[i]->port = first_port + i + 1;
3063*4882a593Smuzhiyun dm[i]->slave = slave;
3064*4882a593Smuzhiyun dm[i]->do_init = do_init;
3065*4882a593Smuzhiyun dm[i]->dev = ibdev;
3066*4882a593Smuzhiyun }
3067*4882a593Smuzhiyun /* initialize or tear down tunnel QPs for the slave */
3068*4882a593Smuzhiyun spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
3069*4882a593Smuzhiyun if (!ibdev->sriov.is_going_down) {
3070*4882a593Smuzhiyun for (i = 0; i < ports; i++)
3071*4882a593Smuzhiyun queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
3072*4882a593Smuzhiyun spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3073*4882a593Smuzhiyun } else {
3074*4882a593Smuzhiyun spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
3075*4882a593Smuzhiyun for (i = 0; i < ports; i++)
3076*4882a593Smuzhiyun kfree(dm[i]);
3077*4882a593Smuzhiyun }
3078*4882a593Smuzhiyun out:
3079*4882a593Smuzhiyun kfree(dm);
3080*4882a593Smuzhiyun return;
3081*4882a593Smuzhiyun }
3082*4882a593Smuzhiyun
mlx4_ib_handle_catas_error(struct mlx4_ib_dev * ibdev)3083*4882a593Smuzhiyun static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
3084*4882a593Smuzhiyun {
3085*4882a593Smuzhiyun struct mlx4_ib_qp *mqp;
3086*4882a593Smuzhiyun unsigned long flags_qp;
3087*4882a593Smuzhiyun unsigned long flags_cq;
3088*4882a593Smuzhiyun struct mlx4_ib_cq *send_mcq, *recv_mcq;
3089*4882a593Smuzhiyun struct list_head cq_notify_list;
3090*4882a593Smuzhiyun struct mlx4_cq *mcq;
3091*4882a593Smuzhiyun unsigned long flags;
3092*4882a593Smuzhiyun
3093*4882a593Smuzhiyun pr_warn("mlx4_ib_handle_catas_error was started\n");
3094*4882a593Smuzhiyun INIT_LIST_HEAD(&cq_notify_list);
3095*4882a593Smuzhiyun
3096*4882a593Smuzhiyun /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3097*4882a593Smuzhiyun spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
3098*4882a593Smuzhiyun
3099*4882a593Smuzhiyun list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
3100*4882a593Smuzhiyun spin_lock_irqsave(&mqp->sq.lock, flags_qp);
3101*4882a593Smuzhiyun if (mqp->sq.tail != mqp->sq.head) {
3102*4882a593Smuzhiyun send_mcq = to_mcq(mqp->ibqp.send_cq);
3103*4882a593Smuzhiyun spin_lock_irqsave(&send_mcq->lock, flags_cq);
3104*4882a593Smuzhiyun if (send_mcq->mcq.comp &&
3105*4882a593Smuzhiyun mqp->ibqp.send_cq->comp_handler) {
3106*4882a593Smuzhiyun if (!send_mcq->mcq.reset_notify_added) {
3107*4882a593Smuzhiyun send_mcq->mcq.reset_notify_added = 1;
3108*4882a593Smuzhiyun list_add_tail(&send_mcq->mcq.reset_notify,
3109*4882a593Smuzhiyun &cq_notify_list);
3110*4882a593Smuzhiyun }
3111*4882a593Smuzhiyun }
3112*4882a593Smuzhiyun spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
3113*4882a593Smuzhiyun }
3114*4882a593Smuzhiyun spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
3115*4882a593Smuzhiyun /* Now, handle the QP's receive queue */
3116*4882a593Smuzhiyun spin_lock_irqsave(&mqp->rq.lock, flags_qp);
3117*4882a593Smuzhiyun /* no handling is needed for SRQ */
3118*4882a593Smuzhiyun if (!mqp->ibqp.srq) {
3119*4882a593Smuzhiyun if (mqp->rq.tail != mqp->rq.head) {
3120*4882a593Smuzhiyun recv_mcq = to_mcq(mqp->ibqp.recv_cq);
3121*4882a593Smuzhiyun spin_lock_irqsave(&recv_mcq->lock, flags_cq);
3122*4882a593Smuzhiyun if (recv_mcq->mcq.comp &&
3123*4882a593Smuzhiyun mqp->ibqp.recv_cq->comp_handler) {
3124*4882a593Smuzhiyun if (!recv_mcq->mcq.reset_notify_added) {
3125*4882a593Smuzhiyun recv_mcq->mcq.reset_notify_added = 1;
3126*4882a593Smuzhiyun list_add_tail(&recv_mcq->mcq.reset_notify,
3127*4882a593Smuzhiyun &cq_notify_list);
3128*4882a593Smuzhiyun }
3129*4882a593Smuzhiyun }
3130*4882a593Smuzhiyun spin_unlock_irqrestore(&recv_mcq->lock,
3131*4882a593Smuzhiyun flags_cq);
3132*4882a593Smuzhiyun }
3133*4882a593Smuzhiyun }
3134*4882a593Smuzhiyun spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
3135*4882a593Smuzhiyun }
3136*4882a593Smuzhiyun
3137*4882a593Smuzhiyun list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
3138*4882a593Smuzhiyun mcq->comp(mcq);
3139*4882a593Smuzhiyun }
3140*4882a593Smuzhiyun spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
3141*4882a593Smuzhiyun pr_warn("mlx4_ib_handle_catas_error ended\n");
3142*4882a593Smuzhiyun }
3143*4882a593Smuzhiyun
handle_bonded_port_state_event(struct work_struct * work)3144*4882a593Smuzhiyun static void handle_bonded_port_state_event(struct work_struct *work)
3145*4882a593Smuzhiyun {
3146*4882a593Smuzhiyun struct ib_event_work *ew =
3147*4882a593Smuzhiyun container_of(work, struct ib_event_work, work);
3148*4882a593Smuzhiyun struct mlx4_ib_dev *ibdev = ew->ib_dev;
3149*4882a593Smuzhiyun enum ib_port_state bonded_port_state = IB_PORT_NOP;
3150*4882a593Smuzhiyun int i;
3151*4882a593Smuzhiyun struct ib_event ibev;
3152*4882a593Smuzhiyun
3153*4882a593Smuzhiyun kfree(ew);
3154*4882a593Smuzhiyun spin_lock_bh(&ibdev->iboe.lock);
3155*4882a593Smuzhiyun for (i = 0; i < MLX4_MAX_PORTS; ++i) {
3156*4882a593Smuzhiyun struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
3157*4882a593Smuzhiyun enum ib_port_state curr_port_state;
3158*4882a593Smuzhiyun
3159*4882a593Smuzhiyun if (!curr_netdev)
3160*4882a593Smuzhiyun continue;
3161*4882a593Smuzhiyun
3162*4882a593Smuzhiyun curr_port_state =
3163*4882a593Smuzhiyun (netif_running(curr_netdev) &&
3164*4882a593Smuzhiyun netif_carrier_ok(curr_netdev)) ?
3165*4882a593Smuzhiyun IB_PORT_ACTIVE : IB_PORT_DOWN;
3166*4882a593Smuzhiyun
3167*4882a593Smuzhiyun bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
3168*4882a593Smuzhiyun curr_port_state : IB_PORT_ACTIVE;
3169*4882a593Smuzhiyun }
3170*4882a593Smuzhiyun spin_unlock_bh(&ibdev->iboe.lock);
3171*4882a593Smuzhiyun
3172*4882a593Smuzhiyun ibev.device = &ibdev->ib_dev;
3173*4882a593Smuzhiyun ibev.element.port_num = 1;
3174*4882a593Smuzhiyun ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
3175*4882a593Smuzhiyun IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
3176*4882a593Smuzhiyun
3177*4882a593Smuzhiyun ib_dispatch_event(&ibev);
3178*4882a593Smuzhiyun }
3179*4882a593Smuzhiyun
mlx4_ib_sl2vl_update(struct mlx4_ib_dev * mdev,int port)3180*4882a593Smuzhiyun void mlx4_ib_sl2vl_update(struct mlx4_ib_dev *mdev, int port)
3181*4882a593Smuzhiyun {
3182*4882a593Smuzhiyun u64 sl2vl;
3183*4882a593Smuzhiyun int err;
3184*4882a593Smuzhiyun
3185*4882a593Smuzhiyun err = mlx4_ib_query_sl2vl(&mdev->ib_dev, port, &sl2vl);
3186*4882a593Smuzhiyun if (err) {
3187*4882a593Smuzhiyun pr_err("Unable to get current sl to vl mapping for port %d. Using all zeroes (%d)\n",
3188*4882a593Smuzhiyun port, err);
3189*4882a593Smuzhiyun sl2vl = 0;
3190*4882a593Smuzhiyun }
3191*4882a593Smuzhiyun atomic64_set(&mdev->sl2vl[port - 1], sl2vl);
3192*4882a593Smuzhiyun }
3193*4882a593Smuzhiyun
ib_sl2vl_update_work(struct work_struct * work)3194*4882a593Smuzhiyun static void ib_sl2vl_update_work(struct work_struct *work)
3195*4882a593Smuzhiyun {
3196*4882a593Smuzhiyun struct ib_event_work *ew = container_of(work, struct ib_event_work, work);
3197*4882a593Smuzhiyun struct mlx4_ib_dev *mdev = ew->ib_dev;
3198*4882a593Smuzhiyun int port = ew->port;
3199*4882a593Smuzhiyun
3200*4882a593Smuzhiyun mlx4_ib_sl2vl_update(mdev, port);
3201*4882a593Smuzhiyun
3202*4882a593Smuzhiyun kfree(ew);
3203*4882a593Smuzhiyun }
3204*4882a593Smuzhiyun
mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev * ibdev,int port)3205*4882a593Smuzhiyun void mlx4_sched_ib_sl2vl_update_work(struct mlx4_ib_dev *ibdev,
3206*4882a593Smuzhiyun int port)
3207*4882a593Smuzhiyun {
3208*4882a593Smuzhiyun struct ib_event_work *ew;
3209*4882a593Smuzhiyun
3210*4882a593Smuzhiyun ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3211*4882a593Smuzhiyun if (ew) {
3212*4882a593Smuzhiyun INIT_WORK(&ew->work, ib_sl2vl_update_work);
3213*4882a593Smuzhiyun ew->port = port;
3214*4882a593Smuzhiyun ew->ib_dev = ibdev;
3215*4882a593Smuzhiyun queue_work(wq, &ew->work);
3216*4882a593Smuzhiyun }
3217*4882a593Smuzhiyun }
3218*4882a593Smuzhiyun
mlx4_ib_event(struct mlx4_dev * dev,void * ibdev_ptr,enum mlx4_dev_event event,unsigned long param)3219*4882a593Smuzhiyun static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
3220*4882a593Smuzhiyun enum mlx4_dev_event event, unsigned long param)
3221*4882a593Smuzhiyun {
3222*4882a593Smuzhiyun struct ib_event ibev;
3223*4882a593Smuzhiyun struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
3224*4882a593Smuzhiyun struct mlx4_eqe *eqe = NULL;
3225*4882a593Smuzhiyun struct ib_event_work *ew;
3226*4882a593Smuzhiyun int p = 0;
3227*4882a593Smuzhiyun
3228*4882a593Smuzhiyun if (mlx4_is_bonded(dev) &&
3229*4882a593Smuzhiyun ((event == MLX4_DEV_EVENT_PORT_UP) ||
3230*4882a593Smuzhiyun (event == MLX4_DEV_EVENT_PORT_DOWN))) {
3231*4882a593Smuzhiyun ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
3232*4882a593Smuzhiyun if (!ew)
3233*4882a593Smuzhiyun return;
3234*4882a593Smuzhiyun INIT_WORK(&ew->work, handle_bonded_port_state_event);
3235*4882a593Smuzhiyun ew->ib_dev = ibdev;
3236*4882a593Smuzhiyun queue_work(wq, &ew->work);
3237*4882a593Smuzhiyun return;
3238*4882a593Smuzhiyun }
3239*4882a593Smuzhiyun
3240*4882a593Smuzhiyun if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
3241*4882a593Smuzhiyun eqe = (struct mlx4_eqe *)param;
3242*4882a593Smuzhiyun else
3243*4882a593Smuzhiyun p = (int) param;
3244*4882a593Smuzhiyun
3245*4882a593Smuzhiyun switch (event) {
3246*4882a593Smuzhiyun case MLX4_DEV_EVENT_PORT_UP:
3247*4882a593Smuzhiyun if (p > ibdev->num_ports)
3248*4882a593Smuzhiyun return;
3249*4882a593Smuzhiyun if (!mlx4_is_slave(dev) &&
3250*4882a593Smuzhiyun rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
3251*4882a593Smuzhiyun IB_LINK_LAYER_INFINIBAND) {
3252*4882a593Smuzhiyun if (mlx4_is_master(dev))
3253*4882a593Smuzhiyun mlx4_ib_invalidate_all_guid_record(ibdev, p);
3254*4882a593Smuzhiyun if (ibdev->dev->flags & MLX4_FLAG_SECURE_HOST &&
3255*4882a593Smuzhiyun !(ibdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SL_TO_VL_CHANGE_EVENT))
3256*4882a593Smuzhiyun mlx4_sched_ib_sl2vl_update_work(ibdev, p);
3257*4882a593Smuzhiyun }
3258*4882a593Smuzhiyun ibev.event = IB_EVENT_PORT_ACTIVE;
3259*4882a593Smuzhiyun break;
3260*4882a593Smuzhiyun
3261*4882a593Smuzhiyun case MLX4_DEV_EVENT_PORT_DOWN:
3262*4882a593Smuzhiyun if (p > ibdev->num_ports)
3263*4882a593Smuzhiyun return;
3264*4882a593Smuzhiyun ibev.event = IB_EVENT_PORT_ERR;
3265*4882a593Smuzhiyun break;
3266*4882a593Smuzhiyun
3267*4882a593Smuzhiyun case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
3268*4882a593Smuzhiyun ibdev->ib_active = false;
3269*4882a593Smuzhiyun ibev.event = IB_EVENT_DEVICE_FATAL;
3270*4882a593Smuzhiyun mlx4_ib_handle_catas_error(ibdev);
3271*4882a593Smuzhiyun break;
3272*4882a593Smuzhiyun
3273*4882a593Smuzhiyun case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
3274*4882a593Smuzhiyun ew = kmalloc(sizeof *ew, GFP_ATOMIC);
3275*4882a593Smuzhiyun if (!ew)
3276*4882a593Smuzhiyun return;
3277*4882a593Smuzhiyun
3278*4882a593Smuzhiyun INIT_WORK(&ew->work, handle_port_mgmt_change_event);
3279*4882a593Smuzhiyun memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
3280*4882a593Smuzhiyun ew->ib_dev = ibdev;
3281*4882a593Smuzhiyun /* need to queue only for port owner, which uses GEN_EQE */
3282*4882a593Smuzhiyun if (mlx4_is_master(dev))
3283*4882a593Smuzhiyun queue_work(wq, &ew->work);
3284*4882a593Smuzhiyun else
3285*4882a593Smuzhiyun handle_port_mgmt_change_event(&ew->work);
3286*4882a593Smuzhiyun return;
3287*4882a593Smuzhiyun
3288*4882a593Smuzhiyun case MLX4_DEV_EVENT_SLAVE_INIT:
3289*4882a593Smuzhiyun /* here, p is the slave id */
3290*4882a593Smuzhiyun do_slave_init(ibdev, p, 1);
3291*4882a593Smuzhiyun if (mlx4_is_master(dev)) {
3292*4882a593Smuzhiyun int i;
3293*4882a593Smuzhiyun
3294*4882a593Smuzhiyun for (i = 1; i <= ibdev->num_ports; i++) {
3295*4882a593Smuzhiyun if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3296*4882a593Smuzhiyun == IB_LINK_LAYER_INFINIBAND)
3297*4882a593Smuzhiyun mlx4_ib_slave_alias_guid_event(ibdev,
3298*4882a593Smuzhiyun p, i,
3299*4882a593Smuzhiyun 1);
3300*4882a593Smuzhiyun }
3301*4882a593Smuzhiyun }
3302*4882a593Smuzhiyun return;
3303*4882a593Smuzhiyun
3304*4882a593Smuzhiyun case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
3305*4882a593Smuzhiyun if (mlx4_is_master(dev)) {
3306*4882a593Smuzhiyun int i;
3307*4882a593Smuzhiyun
3308*4882a593Smuzhiyun for (i = 1; i <= ibdev->num_ports; i++) {
3309*4882a593Smuzhiyun if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
3310*4882a593Smuzhiyun == IB_LINK_LAYER_INFINIBAND)
3311*4882a593Smuzhiyun mlx4_ib_slave_alias_guid_event(ibdev,
3312*4882a593Smuzhiyun p, i,
3313*4882a593Smuzhiyun 0);
3314*4882a593Smuzhiyun }
3315*4882a593Smuzhiyun }
3316*4882a593Smuzhiyun /* here, p is the slave id */
3317*4882a593Smuzhiyun do_slave_init(ibdev, p, 0);
3318*4882a593Smuzhiyun return;
3319*4882a593Smuzhiyun
3320*4882a593Smuzhiyun default:
3321*4882a593Smuzhiyun return;
3322*4882a593Smuzhiyun }
3323*4882a593Smuzhiyun
3324*4882a593Smuzhiyun ibev.device = ibdev_ptr;
3325*4882a593Smuzhiyun ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
3326*4882a593Smuzhiyun
3327*4882a593Smuzhiyun ib_dispatch_event(&ibev);
3328*4882a593Smuzhiyun }
3329*4882a593Smuzhiyun
3330*4882a593Smuzhiyun static struct mlx4_interface mlx4_ib_interface = {
3331*4882a593Smuzhiyun .add = mlx4_ib_add,
3332*4882a593Smuzhiyun .remove = mlx4_ib_remove,
3333*4882a593Smuzhiyun .event = mlx4_ib_event,
3334*4882a593Smuzhiyun .protocol = MLX4_PROT_IB_IPV6,
3335*4882a593Smuzhiyun .flags = MLX4_INTFF_BONDING
3336*4882a593Smuzhiyun };
3337*4882a593Smuzhiyun
mlx4_ib_init(void)3338*4882a593Smuzhiyun static int __init mlx4_ib_init(void)
3339*4882a593Smuzhiyun {
3340*4882a593Smuzhiyun int err;
3341*4882a593Smuzhiyun
3342*4882a593Smuzhiyun wq = alloc_ordered_workqueue("mlx4_ib", WQ_MEM_RECLAIM);
3343*4882a593Smuzhiyun if (!wq)
3344*4882a593Smuzhiyun return -ENOMEM;
3345*4882a593Smuzhiyun
3346*4882a593Smuzhiyun err = mlx4_ib_mcg_init();
3347*4882a593Smuzhiyun if (err)
3348*4882a593Smuzhiyun goto clean_wq;
3349*4882a593Smuzhiyun
3350*4882a593Smuzhiyun err = mlx4_register_interface(&mlx4_ib_interface);
3351*4882a593Smuzhiyun if (err)
3352*4882a593Smuzhiyun goto clean_mcg;
3353*4882a593Smuzhiyun
3354*4882a593Smuzhiyun return 0;
3355*4882a593Smuzhiyun
3356*4882a593Smuzhiyun clean_mcg:
3357*4882a593Smuzhiyun mlx4_ib_mcg_destroy();
3358*4882a593Smuzhiyun
3359*4882a593Smuzhiyun clean_wq:
3360*4882a593Smuzhiyun destroy_workqueue(wq);
3361*4882a593Smuzhiyun return err;
3362*4882a593Smuzhiyun }
3363*4882a593Smuzhiyun
mlx4_ib_cleanup(void)3364*4882a593Smuzhiyun static void __exit mlx4_ib_cleanup(void)
3365*4882a593Smuzhiyun {
3366*4882a593Smuzhiyun mlx4_unregister_interface(&mlx4_ib_interface);
3367*4882a593Smuzhiyun mlx4_ib_mcg_destroy();
3368*4882a593Smuzhiyun destroy_workqueue(wq);
3369*4882a593Smuzhiyun }
3370*4882a593Smuzhiyun
3371*4882a593Smuzhiyun module_init(mlx4_ib_init);
3372*4882a593Smuzhiyun module_exit(mlx4_ib_cleanup);
3373