1*4882a593Smuzhiyun /******************************************************************************* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (c) 2015-2016 Intel Corporation. All rights reserved. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This software is available to you under a choice of one of two 6*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU 7*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file 8*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the 9*4882a593Smuzhiyun * OpenFabrics.org BSD license below: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or 12*4882a593Smuzhiyun * without modification, are permitted provided that the following 13*4882a593Smuzhiyun * conditions are met: 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * - Redistributions of source code must retain the above 16*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 17*4882a593Smuzhiyun * disclaimer. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above 20*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 21*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials 22*4882a593Smuzhiyun * provided with the distribution. 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31*4882a593Smuzhiyun * SOFTWARE. 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun *******************************************************************************/ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifndef I40IW_VERBS_H 36*4882a593Smuzhiyun #define I40IW_VERBS_H 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun struct i40iw_ucontext { 39*4882a593Smuzhiyun struct ib_ucontext ibucontext; 40*4882a593Smuzhiyun struct i40iw_device *iwdev; 41*4882a593Smuzhiyun struct list_head cq_reg_mem_list; 42*4882a593Smuzhiyun spinlock_t cq_reg_mem_list_lock; /* memory list for cq's */ 43*4882a593Smuzhiyun struct list_head qp_reg_mem_list; 44*4882a593Smuzhiyun spinlock_t qp_reg_mem_list_lock; /* memory list for qp's */ 45*4882a593Smuzhiyun int abi_ver; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct i40iw_pd { 49*4882a593Smuzhiyun struct ib_pd ibpd; 50*4882a593Smuzhiyun struct i40iw_sc_pd sc_pd; 51*4882a593Smuzhiyun atomic_t usecount; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun struct i40iw_hmc_pble { 55*4882a593Smuzhiyun union { 56*4882a593Smuzhiyun u32 idx; 57*4882a593Smuzhiyun dma_addr_t addr; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun struct i40iw_cq_mr { 62*4882a593Smuzhiyun struct i40iw_hmc_pble cq_pbl; 63*4882a593Smuzhiyun dma_addr_t shadow; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun struct i40iw_qp_mr { 67*4882a593Smuzhiyun struct i40iw_hmc_pble sq_pbl; 68*4882a593Smuzhiyun struct i40iw_hmc_pble rq_pbl; 69*4882a593Smuzhiyun dma_addr_t shadow; 70*4882a593Smuzhiyun struct page *sq_page; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun struct i40iw_pbl { 74*4882a593Smuzhiyun struct list_head list; 75*4882a593Smuzhiyun union { 76*4882a593Smuzhiyun struct i40iw_qp_mr qp_mr; 77*4882a593Smuzhiyun struct i40iw_cq_mr cq_mr; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun bool pbl_allocated; 81*4882a593Smuzhiyun bool on_list; 82*4882a593Smuzhiyun u64 user_base; 83*4882a593Smuzhiyun struct i40iw_pble_alloc pble_alloc; 84*4882a593Smuzhiyun struct i40iw_mr *iwmr; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define MAX_SAVE_PAGE_ADDRS 4 88*4882a593Smuzhiyun struct i40iw_mr { 89*4882a593Smuzhiyun union { 90*4882a593Smuzhiyun struct ib_mr ibmr; 91*4882a593Smuzhiyun struct ib_mw ibmw; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun struct ib_umem *region; 94*4882a593Smuzhiyun u16 type; 95*4882a593Smuzhiyun u32 page_cnt; 96*4882a593Smuzhiyun u64 page_size; 97*4882a593Smuzhiyun u32 npages; 98*4882a593Smuzhiyun u32 stag; 99*4882a593Smuzhiyun u64 length; 100*4882a593Smuzhiyun u64 pgaddrmem[MAX_SAVE_PAGE_ADDRS]; 101*4882a593Smuzhiyun struct i40iw_pbl iwpbl; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun struct i40iw_cq { 105*4882a593Smuzhiyun struct ib_cq ibcq; 106*4882a593Smuzhiyun struct i40iw_sc_cq sc_cq; 107*4882a593Smuzhiyun u16 cq_head; 108*4882a593Smuzhiyun u16 cq_size; 109*4882a593Smuzhiyun u16 cq_number; 110*4882a593Smuzhiyun bool user_mode; 111*4882a593Smuzhiyun u32 polled_completions; 112*4882a593Smuzhiyun u32 cq_mem_size; 113*4882a593Smuzhiyun struct i40iw_dma_mem kmem; 114*4882a593Smuzhiyun spinlock_t lock; /* for poll cq */ 115*4882a593Smuzhiyun struct i40iw_pbl *iwpbl; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun struct disconn_work { 119*4882a593Smuzhiyun struct work_struct work; 120*4882a593Smuzhiyun struct i40iw_qp *iwqp; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun struct iw_cm_id; 124*4882a593Smuzhiyun struct ietf_mpa_frame; 125*4882a593Smuzhiyun struct i40iw_ud_file; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun struct i40iw_qp_kmode { 128*4882a593Smuzhiyun struct i40iw_dma_mem dma_mem; 129*4882a593Smuzhiyun u64 *wrid_mem; 130*4882a593Smuzhiyun }; 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun struct i40iw_qp { 133*4882a593Smuzhiyun struct ib_qp ibqp; 134*4882a593Smuzhiyun struct i40iw_sc_qp sc_qp; 135*4882a593Smuzhiyun struct i40iw_device *iwdev; 136*4882a593Smuzhiyun struct i40iw_cq *iwscq; 137*4882a593Smuzhiyun struct i40iw_cq *iwrcq; 138*4882a593Smuzhiyun struct i40iw_pd *iwpd; 139*4882a593Smuzhiyun struct i40iw_qp_host_ctx_info ctx_info; 140*4882a593Smuzhiyun struct i40iwarp_offload_info iwarp_info; 141*4882a593Smuzhiyun void *allocated_buffer; 142*4882a593Smuzhiyun refcount_t refcount; 143*4882a593Smuzhiyun struct iw_cm_id *cm_id; 144*4882a593Smuzhiyun void *cm_node; 145*4882a593Smuzhiyun struct ib_mr *lsmm_mr; 146*4882a593Smuzhiyun struct work_struct work; 147*4882a593Smuzhiyun enum ib_qp_state ibqp_state; 148*4882a593Smuzhiyun u32 iwarp_state; 149*4882a593Smuzhiyun u32 qp_mem_size; 150*4882a593Smuzhiyun u32 last_aeq; 151*4882a593Smuzhiyun atomic_t close_timer_started; 152*4882a593Smuzhiyun spinlock_t lock; /* for post work requests */ 153*4882a593Smuzhiyun struct i40iw_qp_context *iwqp_context; 154*4882a593Smuzhiyun void *pbl_vbase; 155*4882a593Smuzhiyun dma_addr_t pbl_pbase; 156*4882a593Smuzhiyun struct page *page; 157*4882a593Smuzhiyun u8 active_conn:1; 158*4882a593Smuzhiyun u8 user_mode:1; 159*4882a593Smuzhiyun u8 hte_added:1; 160*4882a593Smuzhiyun u8 flush_issued:1; 161*4882a593Smuzhiyun u8 destroyed:1; 162*4882a593Smuzhiyun u8 sig_all:1; 163*4882a593Smuzhiyun u8 pau_mode:1; 164*4882a593Smuzhiyun u8 rsvd:1; 165*4882a593Smuzhiyun u16 term_sq_flush_code; 166*4882a593Smuzhiyun u16 term_rq_flush_code; 167*4882a593Smuzhiyun u8 hw_iwarp_state; 168*4882a593Smuzhiyun u8 hw_tcp_state; 169*4882a593Smuzhiyun struct i40iw_qp_kmode kqp; 170*4882a593Smuzhiyun struct i40iw_dma_mem host_ctx; 171*4882a593Smuzhiyun struct timer_list terminate_timer; 172*4882a593Smuzhiyun struct i40iw_pbl iwpbl; 173*4882a593Smuzhiyun struct i40iw_dma_mem q2_ctx_mem; 174*4882a593Smuzhiyun struct i40iw_dma_mem ietf_mem; 175*4882a593Smuzhiyun struct completion sq_drained; 176*4882a593Smuzhiyun struct completion rq_drained; 177*4882a593Smuzhiyun struct completion free_qp; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun #endif 180