1*4882a593Smuzhiyun /******************************************************************************* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (c) 2015-2016 Intel Corporation. All rights reserved. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This software is available to you under a choice of one of two 6*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU 7*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file 8*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the 9*4882a593Smuzhiyun * OpenFabrics.org BSD license below: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or 12*4882a593Smuzhiyun * without modification, are permitted provided that the following 13*4882a593Smuzhiyun * conditions are met: 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * - Redistributions of source code must retain the above 16*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 17*4882a593Smuzhiyun * disclaimer. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above 20*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 21*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials 22*4882a593Smuzhiyun * provided with the distribution. 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31*4882a593Smuzhiyun * SOFTWARE. 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun *******************************************************************************/ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifndef I40IW_PUDA_H 36*4882a593Smuzhiyun #define I40IW_PUDA_H 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define I40IW_IEQ_MPA_FRAMING 6 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun struct i40iw_sc_dev; 41*4882a593Smuzhiyun struct i40iw_sc_qp; 42*4882a593Smuzhiyun struct i40iw_sc_cq; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun enum puda_resource_type { 45*4882a593Smuzhiyun I40IW_PUDA_RSRC_TYPE_ILQ = 1, 46*4882a593Smuzhiyun I40IW_PUDA_RSRC_TYPE_IEQ 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun enum puda_rsrc_complete { 50*4882a593Smuzhiyun PUDA_CQ_CREATED = 1, 51*4882a593Smuzhiyun PUDA_QP_CREATED, 52*4882a593Smuzhiyun PUDA_TX_COMPLETE, 53*4882a593Smuzhiyun PUDA_RX_COMPLETE, 54*4882a593Smuzhiyun PUDA_HASH_CRC_COMPLETE 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct i40iw_puda_completion_info { 58*4882a593Smuzhiyun struct i40iw_qp_uk *qp; 59*4882a593Smuzhiyun u8 q_type; 60*4882a593Smuzhiyun u8 vlan_valid; 61*4882a593Smuzhiyun u8 l3proto; 62*4882a593Smuzhiyun u8 l4proto; 63*4882a593Smuzhiyun u16 payload_len; 64*4882a593Smuzhiyun u32 compl_error; /* No_err=0, else major and minor err code */ 65*4882a593Smuzhiyun u32 qp_id; 66*4882a593Smuzhiyun u32 wqe_idx; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun struct i40iw_puda_send_info { 70*4882a593Smuzhiyun u64 paddr; /* Physical address */ 71*4882a593Smuzhiyun u32 len; 72*4882a593Smuzhiyun u8 tcplen; 73*4882a593Smuzhiyun u8 maclen; 74*4882a593Smuzhiyun bool ipv4; 75*4882a593Smuzhiyun bool doloopback; 76*4882a593Smuzhiyun void *scratch; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun struct i40iw_puda_buf { 80*4882a593Smuzhiyun struct list_head list; /* MUST be first entry */ 81*4882a593Smuzhiyun struct i40iw_dma_mem mem; /* DMA memory for the buffer */ 82*4882a593Smuzhiyun struct i40iw_puda_buf *next; /* for alloclist in rsrc struct */ 83*4882a593Smuzhiyun struct i40iw_virt_mem buf_mem; /* Buffer memory for this buffer */ 84*4882a593Smuzhiyun void *scratch; 85*4882a593Smuzhiyun u8 *iph; 86*4882a593Smuzhiyun u8 *tcph; 87*4882a593Smuzhiyun u8 *data; 88*4882a593Smuzhiyun u16 datalen; 89*4882a593Smuzhiyun u16 vlan_id; 90*4882a593Smuzhiyun u8 tcphlen; /* tcp length in bytes */ 91*4882a593Smuzhiyun u8 maclen; /* mac length in bytes */ 92*4882a593Smuzhiyun u32 totallen; /* machlen+iphlen+tcphlen+datalen */ 93*4882a593Smuzhiyun atomic_t refcount; 94*4882a593Smuzhiyun u8 hdrlen; 95*4882a593Smuzhiyun bool ipv4; 96*4882a593Smuzhiyun u32 seqnum; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct i40iw_puda_rsrc_info { 100*4882a593Smuzhiyun enum puda_resource_type type; /* ILQ or IEQ */ 101*4882a593Smuzhiyun u32 count; 102*4882a593Smuzhiyun u16 pd_id; 103*4882a593Smuzhiyun u32 cq_id; 104*4882a593Smuzhiyun u32 qp_id; 105*4882a593Smuzhiyun u32 sq_size; 106*4882a593Smuzhiyun u32 rq_size; 107*4882a593Smuzhiyun u16 buf_size; 108*4882a593Smuzhiyun u16 mss; 109*4882a593Smuzhiyun u32 tx_buf_cnt; /* total bufs allocated will be rq_size + tx_buf_cnt */ 110*4882a593Smuzhiyun void (*receive)(struct i40iw_sc_vsi *, struct i40iw_puda_buf *); 111*4882a593Smuzhiyun void (*xmit_complete)(struct i40iw_sc_vsi *, void *); 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun struct i40iw_puda_rsrc { 115*4882a593Smuzhiyun struct i40iw_sc_cq cq; 116*4882a593Smuzhiyun struct i40iw_sc_qp qp; 117*4882a593Smuzhiyun struct i40iw_sc_pd sc_pd; 118*4882a593Smuzhiyun struct i40iw_sc_dev *dev; 119*4882a593Smuzhiyun struct i40iw_sc_vsi *vsi; 120*4882a593Smuzhiyun struct i40iw_dma_mem cqmem; 121*4882a593Smuzhiyun struct i40iw_dma_mem qpmem; 122*4882a593Smuzhiyun struct i40iw_virt_mem ilq_mem; 123*4882a593Smuzhiyun enum puda_rsrc_complete completion; 124*4882a593Smuzhiyun enum puda_resource_type type; 125*4882a593Smuzhiyun u16 buf_size; /*buffer must be max datalen + tcpip hdr + mac */ 126*4882a593Smuzhiyun u16 mss; 127*4882a593Smuzhiyun u32 cq_id; 128*4882a593Smuzhiyun u32 qp_id; 129*4882a593Smuzhiyun u32 sq_size; 130*4882a593Smuzhiyun u32 rq_size; 131*4882a593Smuzhiyun u32 cq_size; 132*4882a593Smuzhiyun struct i40iw_sq_uk_wr_trk_info *sq_wrtrk_array; 133*4882a593Smuzhiyun u64 *rq_wrid_array; 134*4882a593Smuzhiyun u32 compl_rxwqe_idx; 135*4882a593Smuzhiyun u32 rx_wqe_idx; 136*4882a593Smuzhiyun u32 rxq_invalid_cnt; 137*4882a593Smuzhiyun u32 tx_wqe_avail_cnt; 138*4882a593Smuzhiyun bool check_crc; 139*4882a593Smuzhiyun struct shash_desc *hash_desc; 140*4882a593Smuzhiyun struct list_head txpend; 141*4882a593Smuzhiyun struct list_head bufpool; /* free buffers pool list for recv and xmit */ 142*4882a593Smuzhiyun u32 alloc_buf_count; 143*4882a593Smuzhiyun u32 avail_buf_count; /* snapshot of currently available buffers */ 144*4882a593Smuzhiyun spinlock_t bufpool_lock; 145*4882a593Smuzhiyun struct i40iw_puda_buf *alloclist; 146*4882a593Smuzhiyun void (*receive)(struct i40iw_sc_vsi *, struct i40iw_puda_buf *); 147*4882a593Smuzhiyun void (*xmit_complete)(struct i40iw_sc_vsi *, void *); 148*4882a593Smuzhiyun /* puda stats */ 149*4882a593Smuzhiyun u64 stats_buf_alloc_fail; 150*4882a593Smuzhiyun u64 stats_pkt_rcvd; 151*4882a593Smuzhiyun u64 stats_pkt_sent; 152*4882a593Smuzhiyun u64 stats_rcvd_pkt_err; 153*4882a593Smuzhiyun u64 stats_sent_pkt_q; 154*4882a593Smuzhiyun u64 stats_bad_qp_id; 155*4882a593Smuzhiyun }; 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun struct i40iw_puda_buf *i40iw_puda_get_bufpool(struct i40iw_puda_rsrc *rsrc); 158*4882a593Smuzhiyun void i40iw_puda_ret_bufpool(struct i40iw_puda_rsrc *rsrc, 159*4882a593Smuzhiyun struct i40iw_puda_buf *buf); 160*4882a593Smuzhiyun void i40iw_puda_send_buf(struct i40iw_puda_rsrc *rsrc, 161*4882a593Smuzhiyun struct i40iw_puda_buf *buf); 162*4882a593Smuzhiyun enum i40iw_status_code i40iw_puda_send(struct i40iw_sc_qp *qp, 163*4882a593Smuzhiyun struct i40iw_puda_send_info *info); 164*4882a593Smuzhiyun enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_vsi *vsi, 165*4882a593Smuzhiyun struct i40iw_puda_rsrc_info *info); 166*4882a593Smuzhiyun void i40iw_puda_dele_resources(struct i40iw_sc_vsi *vsi, 167*4882a593Smuzhiyun enum puda_resource_type type, 168*4882a593Smuzhiyun bool reset); 169*4882a593Smuzhiyun enum i40iw_status_code i40iw_puda_poll_completion(struct i40iw_sc_dev *dev, 170*4882a593Smuzhiyun struct i40iw_sc_cq *cq, u32 *compl_err); 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun struct i40iw_sc_qp *i40iw_ieq_get_qp(struct i40iw_sc_dev *dev, 173*4882a593Smuzhiyun struct i40iw_puda_buf *buf); 174*4882a593Smuzhiyun enum i40iw_status_code i40iw_puda_get_tcpip_info(struct i40iw_puda_completion_info *info, 175*4882a593Smuzhiyun struct i40iw_puda_buf *buf); 176*4882a593Smuzhiyun enum i40iw_status_code i40iw_ieq_check_mpacrc(struct shash_desc *desc, 177*4882a593Smuzhiyun void *addr, u32 length, u32 value); 178*4882a593Smuzhiyun enum i40iw_status_code i40iw_init_hash_desc(struct shash_desc **desc); 179*4882a593Smuzhiyun void i40iw_ieq_mpa_crc_ae(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp); 180*4882a593Smuzhiyun void i40iw_free_hash_desc(struct shash_desc *desc); 181*4882a593Smuzhiyun void i40iw_ieq_update_tcpip_info(struct i40iw_puda_buf *buf, u16 length, 182*4882a593Smuzhiyun u32 seqnum); 183*4882a593Smuzhiyun enum i40iw_status_code i40iw_cqp_qp_create_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp); 184*4882a593Smuzhiyun enum i40iw_status_code i40iw_cqp_cq_create_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_cq *cq); 185*4882a593Smuzhiyun void i40iw_cqp_qp_destroy_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp); 186*4882a593Smuzhiyun void i40iw_cqp_cq_destroy_cmd(struct i40iw_sc_dev *dev, struct i40iw_sc_cq *cq); 187*4882a593Smuzhiyun void i40iw_ieq_cleanup_qp(struct i40iw_puda_rsrc *ieq, struct i40iw_sc_qp *qp); 188*4882a593Smuzhiyun #endif 189