1*4882a593Smuzhiyun /******************************************************************************* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (c) 2015-2016 Intel Corporation. All rights reserved. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This software is available to you under a choice of one of two 6*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU 7*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file 8*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the 9*4882a593Smuzhiyun * OpenFabrics.org BSD license below: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or 12*4882a593Smuzhiyun * without modification, are permitted provided that the following 13*4882a593Smuzhiyun * conditions are met: 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * - Redistributions of source code must retain the above 16*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 17*4882a593Smuzhiyun * disclaimer. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above 20*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 21*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials 22*4882a593Smuzhiyun * provided with the distribution. 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31*4882a593Smuzhiyun * SOFTWARE. 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun *******************************************************************************/ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifndef I40IW_P_H 36*4882a593Smuzhiyun #define I40IW_P_H 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define PAUSE_TIMER_VALUE 0xFFFF 39*4882a593Smuzhiyun #define REFRESH_THRESHOLD 0x7FFF 40*4882a593Smuzhiyun #define HIGH_THRESHOLD 0x800 41*4882a593Smuzhiyun #define LOW_THRESHOLD 0x200 42*4882a593Smuzhiyun #define ALL_TC2PFC 0xFF 43*4882a593Smuzhiyun #define CQP_COMPL_WAIT_TIME 0x3E8 44*4882a593Smuzhiyun #define CQP_TIMEOUT_THRESHOLD 5 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun void i40iw_debug_buf(struct i40iw_sc_dev *dev, enum i40iw_debug_flag mask, 47*4882a593Smuzhiyun char *desc, u64 *buf, u32 size); 48*4882a593Smuzhiyun /* init operations */ 49*4882a593Smuzhiyun enum i40iw_status_code i40iw_device_init(struct i40iw_sc_dev *dev, 50*4882a593Smuzhiyun struct i40iw_device_init_info *info); 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun void i40iw_sc_cqp_post_sq(struct i40iw_sc_cqp *cqp); 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun u64 *i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp *cqp, u64 scratch); 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun void i40iw_check_cqp_progress(struct i40iw_cqp_timeout *cqp_timeout, struct i40iw_sc_dev *dev); 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun enum i40iw_status_code i40iw_sc_mr_fast_register(struct i40iw_sc_qp *qp, 59*4882a593Smuzhiyun struct i40iw_fast_reg_stag_info *info, 60*4882a593Smuzhiyun bool post_sq); 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun void i40iw_insert_wqe_hdr(u64 *wqe, u64 header); 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* HMC/FPM functions */ 65*4882a593Smuzhiyun enum i40iw_status_code i40iw_sc_init_iw_hmc(struct i40iw_sc_dev *dev, 66*4882a593Smuzhiyun u8 hmc_fn_id); 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun enum i40iw_status_code i40iw_pf_init_vfhmc(struct i40iw_sc_dev *dev, u8 vf_hmc_fn_id, 69*4882a593Smuzhiyun u32 *vf_cnt_array); 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* stats functions */ 72*4882a593Smuzhiyun void i40iw_hw_stats_refresh_all(struct i40iw_vsi_pestat *stats); 73*4882a593Smuzhiyun void i40iw_hw_stats_read_all(struct i40iw_vsi_pestat *stats, struct i40iw_dev_hw_stats *stats_values); 74*4882a593Smuzhiyun void i40iw_hw_stats_read_32(struct i40iw_vsi_pestat *stats, 75*4882a593Smuzhiyun enum i40iw_hw_stats_index_32b index, 76*4882a593Smuzhiyun u64 *value); 77*4882a593Smuzhiyun void i40iw_hw_stats_read_64(struct i40iw_vsi_pestat *stats, 78*4882a593Smuzhiyun enum i40iw_hw_stats_index_64b index, 79*4882a593Smuzhiyun u64 *value); 80*4882a593Smuzhiyun void i40iw_hw_stats_init(struct i40iw_vsi_pestat *stats, u8 index, bool is_pf); 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* vsi misc functions */ 83*4882a593Smuzhiyun enum i40iw_status_code i40iw_vsi_stats_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_stats_info *info); 84*4882a593Smuzhiyun void i40iw_vsi_stats_free(struct i40iw_sc_vsi *vsi); 85*4882a593Smuzhiyun void i40iw_sc_vsi_init(struct i40iw_sc_vsi *vsi, struct i40iw_vsi_init_info *info); 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun void i40iw_change_l2params(struct i40iw_sc_vsi *vsi, struct i40iw_l2params *l2params); 88*4882a593Smuzhiyun void i40iw_qp_add_qos(struct i40iw_sc_qp *qp); 89*4882a593Smuzhiyun void i40iw_qp_rem_qos(struct i40iw_sc_qp *qp); 90*4882a593Smuzhiyun void i40iw_terminate_send_fin(struct i40iw_sc_qp *qp); 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun void i40iw_terminate_connection(struct i40iw_sc_qp *qp, struct i40iw_aeqe_info *info); 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun void i40iw_terminate_received(struct i40iw_sc_qp *qp, struct i40iw_aeqe_info *info); 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun enum i40iw_status_code i40iw_sc_suspend_qp(struct i40iw_sc_cqp *cqp, 97*4882a593Smuzhiyun struct i40iw_sc_qp *qp, u64 scratch); 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun enum i40iw_status_code i40iw_sc_resume_qp(struct i40iw_sc_cqp *cqp, 100*4882a593Smuzhiyun struct i40iw_sc_qp *qp, u64 scratch); 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun enum i40iw_status_code i40iw_sc_static_hmc_pages_allocated(struct i40iw_sc_cqp *cqp, 103*4882a593Smuzhiyun u64 scratch, u8 hmc_fn_id, 104*4882a593Smuzhiyun bool post_sq, 105*4882a593Smuzhiyun bool poll_registers); 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun enum i40iw_status_code i40iw_config_fpm_values(struct i40iw_sc_dev *dev, u32 qp_count); 108*4882a593Smuzhiyun enum i40iw_status_code i40iw_get_rdma_features(struct i40iw_sc_dev *dev); 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun void free_sd_mem(struct i40iw_sc_dev *dev); 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun enum i40iw_status_code i40iw_process_cqp_cmd(struct i40iw_sc_dev *dev, 113*4882a593Smuzhiyun struct cqp_commands_info *pcmdinfo); 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun enum i40iw_status_code i40iw_process_bh(struct i40iw_sc_dev *dev); 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* prototype for functions used for dynamic memory allocation */ 118*4882a593Smuzhiyun enum i40iw_status_code i40iw_allocate_dma_mem(struct i40iw_hw *hw, 119*4882a593Smuzhiyun struct i40iw_dma_mem *mem, u64 size, 120*4882a593Smuzhiyun u32 alignment); 121*4882a593Smuzhiyun void i40iw_free_dma_mem(struct i40iw_hw *hw, struct i40iw_dma_mem *mem); 122*4882a593Smuzhiyun enum i40iw_status_code i40iw_allocate_virt_mem(struct i40iw_hw *hw, 123*4882a593Smuzhiyun struct i40iw_virt_mem *mem, u32 size); 124*4882a593Smuzhiyun enum i40iw_status_code i40iw_free_virt_mem(struct i40iw_hw *hw, 125*4882a593Smuzhiyun struct i40iw_virt_mem *mem); 126*4882a593Smuzhiyun u8 i40iw_get_encoded_wqe_size(u32 wqsize, bool cqpsq); 127*4882a593Smuzhiyun void i40iw_reinitialize_ieq(struct i40iw_sc_dev *dev); 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #endif 130