1*4882a593Smuzhiyun /******************************************************************************* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (c) 2015-2016 Intel Corporation. All rights reserved. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This software is available to you under a choice of one of two 6*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU 7*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file 8*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the 9*4882a593Smuzhiyun * OpenFabrics.org BSD license below: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or 12*4882a593Smuzhiyun * without modification, are permitted provided that the following 13*4882a593Smuzhiyun * conditions are met: 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * - Redistributions of source code must retain the above 16*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 17*4882a593Smuzhiyun * disclaimer. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above 20*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 21*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials 22*4882a593Smuzhiyun * provided with the distribution. 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31*4882a593Smuzhiyun * SOFTWARE. 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun *******************************************************************************/ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifndef I40IW_HMC_H 36*4882a593Smuzhiyun #define I40IW_HMC_H 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #include "i40iw_d.h" 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun struct i40iw_hw; 41*4882a593Smuzhiyun enum i40iw_status_code; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define I40IW_HMC_MAX_BP_COUNT 512 44*4882a593Smuzhiyun #define I40IW_MAX_SD_ENTRIES 11 45*4882a593Smuzhiyun #define I40IW_HW_DBG_HMC_INVALID_BP_MARK 0xCA 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define I40IW_HMC_INFO_SIGNATURE 0x484D5347 48*4882a593Smuzhiyun #define I40IW_HMC_PD_CNT_IN_SD 512 49*4882a593Smuzhiyun #define I40IW_HMC_DIRECT_BP_SIZE 0x200000 50*4882a593Smuzhiyun #define I40IW_HMC_MAX_SD_COUNT 4096 51*4882a593Smuzhiyun #define I40IW_HMC_PAGED_BP_SIZE 4096 52*4882a593Smuzhiyun #define I40IW_HMC_PD_BP_BUF_ALIGNMENT 4096 53*4882a593Smuzhiyun #define I40IW_FIRST_VF_FPM_ID 16 54*4882a593Smuzhiyun #define FPM_MULTIPLIER 1024 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define I40IW_INC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt++) 57*4882a593Smuzhiyun #define I40IW_INC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt++) 58*4882a593Smuzhiyun #define I40IW_INC_BP_REFCNT(bp) ((bp)->ref_cnt++) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define I40IW_DEC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt--) 61*4882a593Smuzhiyun #define I40IW_DEC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt--) 62*4882a593Smuzhiyun #define I40IW_DEC_BP_REFCNT(bp) ((bp)->ref_cnt--) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /** 65*4882a593Smuzhiyun * I40IW_INVALIDATE_PF_HMC_PD - Invalidates the pd cache in the hardware 66*4882a593Smuzhiyun * @hw: pointer to our hw struct 67*4882a593Smuzhiyun * @sd_idx: segment descriptor index 68*4882a593Smuzhiyun * @pd_idx: page descriptor index 69*4882a593Smuzhiyun */ 70*4882a593Smuzhiyun #define I40IW_INVALIDATE_PF_HMC_PD(hw, sd_idx, pd_idx) \ 71*4882a593Smuzhiyun i40iw_wr32((hw), I40E_PFHMC_PDINV, \ 72*4882a593Smuzhiyun (((sd_idx) << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) | \ 73*4882a593Smuzhiyun (0x1 << I40E_PFHMC_PDINV_PMSDPARTSEL_SHIFT) | \ 74*4882a593Smuzhiyun ((pd_idx) << I40E_PFHMC_PDINV_PMPDIDX_SHIFT))) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /** 77*4882a593Smuzhiyun * I40IW_INVALIDATE_VF_HMC_PD - Invalidates the pd cache in the hardware 78*4882a593Smuzhiyun * @hw: pointer to our hw struct 79*4882a593Smuzhiyun * @sd_idx: segment descriptor index 80*4882a593Smuzhiyun * @pd_idx: page descriptor index 81*4882a593Smuzhiyun * @hmc_fn_id: VF's function id 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun #define I40IW_INVALIDATE_VF_HMC_PD(hw, sd_idx, pd_idx, hmc_fn_id) \ 84*4882a593Smuzhiyun i40iw_wr32(hw, I40E_GLHMC_VFPDINV(hmc_fn_id - I40IW_FIRST_VF_FPM_ID), \ 85*4882a593Smuzhiyun ((sd_idx << I40E_PFHMC_PDINV_PMSDIDX_SHIFT) | \ 86*4882a593Smuzhiyun (pd_idx << I40E_PFHMC_PDINV_PMPDIDX_SHIFT))) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun struct i40iw_hmc_obj_info { 89*4882a593Smuzhiyun u64 base; 90*4882a593Smuzhiyun u32 max_cnt; 91*4882a593Smuzhiyun u32 cnt; 92*4882a593Smuzhiyun u64 size; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun enum i40iw_sd_entry_type { 96*4882a593Smuzhiyun I40IW_SD_TYPE_INVALID = 0, 97*4882a593Smuzhiyun I40IW_SD_TYPE_PAGED = 1, 98*4882a593Smuzhiyun I40IW_SD_TYPE_DIRECT = 2 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun struct i40iw_hmc_bp { 102*4882a593Smuzhiyun enum i40iw_sd_entry_type entry_type; 103*4882a593Smuzhiyun struct i40iw_dma_mem addr; 104*4882a593Smuzhiyun u32 sd_pd_index; 105*4882a593Smuzhiyun u32 ref_cnt; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun struct i40iw_hmc_pd_entry { 109*4882a593Smuzhiyun struct i40iw_hmc_bp bp; 110*4882a593Smuzhiyun u32 sd_index; 111*4882a593Smuzhiyun bool rsrc_pg; 112*4882a593Smuzhiyun bool valid; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun struct i40iw_hmc_pd_table { 116*4882a593Smuzhiyun struct i40iw_dma_mem pd_page_addr; 117*4882a593Smuzhiyun struct i40iw_hmc_pd_entry *pd_entry; 118*4882a593Smuzhiyun struct i40iw_virt_mem pd_entry_virt_mem; 119*4882a593Smuzhiyun u32 ref_cnt; 120*4882a593Smuzhiyun u32 sd_index; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun struct i40iw_hmc_sd_entry { 124*4882a593Smuzhiyun enum i40iw_sd_entry_type entry_type; 125*4882a593Smuzhiyun bool valid; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun union { 128*4882a593Smuzhiyun struct i40iw_hmc_pd_table pd_table; 129*4882a593Smuzhiyun struct i40iw_hmc_bp bp; 130*4882a593Smuzhiyun } u; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun struct i40iw_hmc_sd_table { 134*4882a593Smuzhiyun struct i40iw_virt_mem addr; 135*4882a593Smuzhiyun u32 sd_cnt; 136*4882a593Smuzhiyun u32 ref_cnt; 137*4882a593Smuzhiyun struct i40iw_hmc_sd_entry *sd_entry; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun struct i40iw_hmc_info { 141*4882a593Smuzhiyun u32 signature; 142*4882a593Smuzhiyun u8 hmc_fn_id; 143*4882a593Smuzhiyun u16 first_sd_index; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun struct i40iw_hmc_obj_info *hmc_obj; 146*4882a593Smuzhiyun struct i40iw_virt_mem hmc_obj_virt_mem; 147*4882a593Smuzhiyun struct i40iw_hmc_sd_table sd_table; 148*4882a593Smuzhiyun u16 sd_indexes[I40IW_HMC_MAX_SD_COUNT]; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun struct update_sd_entry { 152*4882a593Smuzhiyun u64 cmd; 153*4882a593Smuzhiyun u64 data; 154*4882a593Smuzhiyun }; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun struct i40iw_update_sds_info { 157*4882a593Smuzhiyun u32 cnt; 158*4882a593Smuzhiyun u8 hmc_fn_id; 159*4882a593Smuzhiyun struct update_sd_entry entry[I40IW_MAX_SD_ENTRIES]; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun struct i40iw_ccq_cqe_info; 163*4882a593Smuzhiyun struct i40iw_hmc_fcn_info { 164*4882a593Smuzhiyun void (*callback_fcn)(struct i40iw_sc_dev *, void *, 165*4882a593Smuzhiyun struct i40iw_ccq_cqe_info *); 166*4882a593Smuzhiyun void *cqp_callback_param; 167*4882a593Smuzhiyun u32 vf_id; 168*4882a593Smuzhiyun u16 iw_vf_idx; 169*4882a593Smuzhiyun bool free_fcn; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun enum i40iw_hmc_rsrc_type { 173*4882a593Smuzhiyun I40IW_HMC_IW_QP = 0, 174*4882a593Smuzhiyun I40IW_HMC_IW_CQ = 1, 175*4882a593Smuzhiyun I40IW_HMC_IW_SRQ = 2, 176*4882a593Smuzhiyun I40IW_HMC_IW_HTE = 3, 177*4882a593Smuzhiyun I40IW_HMC_IW_ARP = 4, 178*4882a593Smuzhiyun I40IW_HMC_IW_APBVT_ENTRY = 5, 179*4882a593Smuzhiyun I40IW_HMC_IW_MR = 6, 180*4882a593Smuzhiyun I40IW_HMC_IW_XF = 7, 181*4882a593Smuzhiyun I40IW_HMC_IW_XFFL = 8, 182*4882a593Smuzhiyun I40IW_HMC_IW_Q1 = 9, 183*4882a593Smuzhiyun I40IW_HMC_IW_Q1FL = 10, 184*4882a593Smuzhiyun I40IW_HMC_IW_TIMER = 11, 185*4882a593Smuzhiyun I40IW_HMC_IW_FSIMC = 12, 186*4882a593Smuzhiyun I40IW_HMC_IW_FSIAV = 13, 187*4882a593Smuzhiyun I40IW_HMC_IW_PBLE = 14, 188*4882a593Smuzhiyun I40IW_HMC_IW_MAX = 15, 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun struct i40iw_hmc_create_obj_info { 192*4882a593Smuzhiyun struct i40iw_hmc_info *hmc_info; 193*4882a593Smuzhiyun struct i40iw_virt_mem add_sd_virt_mem; 194*4882a593Smuzhiyun u32 rsrc_type; 195*4882a593Smuzhiyun u32 start_idx; 196*4882a593Smuzhiyun u32 count; 197*4882a593Smuzhiyun u32 add_sd_cnt; 198*4882a593Smuzhiyun enum i40iw_sd_entry_type entry_type; 199*4882a593Smuzhiyun bool is_pf; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun struct i40iw_hmc_del_obj_info { 203*4882a593Smuzhiyun struct i40iw_hmc_info *hmc_info; 204*4882a593Smuzhiyun struct i40iw_virt_mem del_sd_virt_mem; 205*4882a593Smuzhiyun u32 rsrc_type; 206*4882a593Smuzhiyun u32 start_idx; 207*4882a593Smuzhiyun u32 count; 208*4882a593Smuzhiyun u32 del_sd_cnt; 209*4882a593Smuzhiyun bool is_pf; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun enum i40iw_status_code i40iw_copy_dma_mem(struct i40iw_hw *hw, void *dest_buf, 213*4882a593Smuzhiyun struct i40iw_dma_mem *src_mem, u64 src_offset, u64 size); 214*4882a593Smuzhiyun enum i40iw_status_code i40iw_sc_create_hmc_obj(struct i40iw_sc_dev *dev, 215*4882a593Smuzhiyun struct i40iw_hmc_create_obj_info *info); 216*4882a593Smuzhiyun enum i40iw_status_code i40iw_sc_del_hmc_obj(struct i40iw_sc_dev *dev, 217*4882a593Smuzhiyun struct i40iw_hmc_del_obj_info *info, 218*4882a593Smuzhiyun bool reset); 219*4882a593Smuzhiyun enum i40iw_status_code i40iw_hmc_sd_one(struct i40iw_sc_dev *dev, u8 hmc_fn_id, 220*4882a593Smuzhiyun u64 pa, u32 sd_idx, enum i40iw_sd_entry_type type, 221*4882a593Smuzhiyun bool setsd); 222*4882a593Smuzhiyun enum i40iw_status_code i40iw_update_sds_noccq(struct i40iw_sc_dev *dev, 223*4882a593Smuzhiyun struct i40iw_update_sds_info *info); 224*4882a593Smuzhiyun struct i40iw_vfdev *i40iw_vfdev_from_fpm(struct i40iw_sc_dev *dev, u8 hmc_fn_id); 225*4882a593Smuzhiyun struct i40iw_hmc_info *i40iw_vf_hmcinfo_from_fpm(struct i40iw_sc_dev *dev, 226*4882a593Smuzhiyun u8 hmc_fn_id); 227*4882a593Smuzhiyun enum i40iw_status_code i40iw_add_sd_table_entry(struct i40iw_hw *hw, 228*4882a593Smuzhiyun struct i40iw_hmc_info *hmc_info, u32 sd_index, 229*4882a593Smuzhiyun enum i40iw_sd_entry_type type, u64 direct_mode_sz); 230*4882a593Smuzhiyun enum i40iw_status_code i40iw_add_pd_table_entry(struct i40iw_hw *hw, 231*4882a593Smuzhiyun struct i40iw_hmc_info *hmc_info, u32 pd_index, 232*4882a593Smuzhiyun struct i40iw_dma_mem *rsrc_pg); 233*4882a593Smuzhiyun enum i40iw_status_code i40iw_remove_pd_bp(struct i40iw_hw *hw, 234*4882a593Smuzhiyun struct i40iw_hmc_info *hmc_info, u32 idx, bool is_pf); 235*4882a593Smuzhiyun enum i40iw_status_code i40iw_prep_remove_sd_bp(struct i40iw_hmc_info *hmc_info, u32 idx); 236*4882a593Smuzhiyun enum i40iw_status_code i40iw_prep_remove_pd_page(struct i40iw_hmc_info *hmc_info, u32 idx); 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun #define ENTER_SHARED_FUNCTION() 239*4882a593Smuzhiyun #define EXIT_SHARED_FUNCTION() 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun #endif /* I40IW_HMC_H */ 242