1*4882a593Smuzhiyun /******************************************************************************* 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (c) 2015-2016 Intel Corporation. All rights reserved. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * This software is available to you under a choice of one of two 6*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU 7*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file 8*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the 9*4882a593Smuzhiyun * OpenFabrics.org BSD license below: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or 12*4882a593Smuzhiyun * without modification, are permitted provided that the following 13*4882a593Smuzhiyun * conditions are met: 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * - Redistributions of source code must retain the above 16*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 17*4882a593Smuzhiyun * disclaimer. 18*4882a593Smuzhiyun * 19*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above 20*4882a593Smuzhiyun * copyright notice, this list of conditions and the following 21*4882a593Smuzhiyun * disclaimer in the documentation and/or other materials 22*4882a593Smuzhiyun * provided with the distribution. 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25*4882a593Smuzhiyun * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26*4882a593Smuzhiyun * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27*4882a593Smuzhiyun * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28*4882a593Smuzhiyun * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29*4882a593Smuzhiyun * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31*4882a593Smuzhiyun * SOFTWARE. 32*4882a593Smuzhiyun * 33*4882a593Smuzhiyun *******************************************************************************/ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #ifndef I40IW_CM_H 36*4882a593Smuzhiyun #define I40IW_CM_H 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define QUEUE_EVENTS 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define I40IW_MANAGE_APBVT_DEL 0 41*4882a593Smuzhiyun #define I40IW_MANAGE_APBVT_ADD 1 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define I40IW_MPA_REQUEST_ACCEPT 1 44*4882a593Smuzhiyun #define I40IW_MPA_REQUEST_REJECT 2 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* IETF MPA -- defines, enums, structs */ 47*4882a593Smuzhiyun #define IEFT_MPA_KEY_REQ "MPA ID Req Frame" 48*4882a593Smuzhiyun #define IEFT_MPA_KEY_REP "MPA ID Rep Frame" 49*4882a593Smuzhiyun #define IETF_MPA_KEY_SIZE 16 50*4882a593Smuzhiyun #define IETF_MPA_VERSION 1 51*4882a593Smuzhiyun #define IETF_MAX_PRIV_DATA_LEN 512 52*4882a593Smuzhiyun #define IETF_MPA_FRAME_SIZE 20 53*4882a593Smuzhiyun #define IETF_RTR_MSG_SIZE 4 54*4882a593Smuzhiyun #define IETF_MPA_V2_FLAG 0x10 55*4882a593Smuzhiyun #define SNDMARKER_SEQNMASK 0x000001FF 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define I40IW_MAX_IETF_SIZE 32 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* IETF RTR MSG Fields */ 60*4882a593Smuzhiyun #define IETF_PEER_TO_PEER 0x8000 61*4882a593Smuzhiyun #define IETF_FLPDU_ZERO_LEN 0x4000 62*4882a593Smuzhiyun #define IETF_RDMA0_WRITE 0x8000 63*4882a593Smuzhiyun #define IETF_RDMA0_READ 0x4000 64*4882a593Smuzhiyun #define IETF_NO_IRD_ORD 0x3FFF 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* HW-supported IRD sizes*/ 67*4882a593Smuzhiyun #define I40IW_HW_IRD_SETTING_2 2 68*4882a593Smuzhiyun #define I40IW_HW_IRD_SETTING_4 4 69*4882a593Smuzhiyun #define I40IW_HW_IRD_SETTING_8 8 70*4882a593Smuzhiyun #define I40IW_HW_IRD_SETTING_16 16 71*4882a593Smuzhiyun #define I40IW_HW_IRD_SETTING_32 32 72*4882a593Smuzhiyun #define I40IW_HW_IRD_SETTING_64 64 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define MAX_PORTS 65536 75*4882a593Smuzhiyun #define I40IW_VLAN_PRIO_SHIFT 13 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun enum ietf_mpa_flags { 78*4882a593Smuzhiyun IETF_MPA_FLAGS_MARKERS = 0x80, /* receive Markers */ 79*4882a593Smuzhiyun IETF_MPA_FLAGS_CRC = 0x40, /* receive Markers */ 80*4882a593Smuzhiyun IETF_MPA_FLAGS_REJECT = 0x20, /* Reject */ 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun struct ietf_mpa_v1 { 84*4882a593Smuzhiyun u8 key[IETF_MPA_KEY_SIZE]; 85*4882a593Smuzhiyun u8 flags; 86*4882a593Smuzhiyun u8 rev; 87*4882a593Smuzhiyun __be16 priv_data_len; 88*4882a593Smuzhiyun u8 priv_data[]; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define ietf_mpa_req_resp_frame ietf_mpa_frame 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct ietf_rtr_msg { 94*4882a593Smuzhiyun __be16 ctrl_ird; 95*4882a593Smuzhiyun __be16 ctrl_ord; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun struct ietf_mpa_v2 { 99*4882a593Smuzhiyun u8 key[IETF_MPA_KEY_SIZE]; 100*4882a593Smuzhiyun u8 flags; 101*4882a593Smuzhiyun u8 rev; 102*4882a593Smuzhiyun __be16 priv_data_len; 103*4882a593Smuzhiyun struct ietf_rtr_msg rtr_msg; 104*4882a593Smuzhiyun u8 priv_data[]; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun struct i40iw_cm_node; 108*4882a593Smuzhiyun enum i40iw_timer_type { 109*4882a593Smuzhiyun I40IW_TIMER_TYPE_SEND, 110*4882a593Smuzhiyun I40IW_TIMER_TYPE_RECV, 111*4882a593Smuzhiyun I40IW_TIMER_NODE_CLEANUP, 112*4882a593Smuzhiyun I40IW_TIMER_TYPE_CLOSE, 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define I40IW_PASSIVE_STATE_INDICATED 0 116*4882a593Smuzhiyun #define I40IW_DO_NOT_SEND_RESET_EVENT 1 117*4882a593Smuzhiyun #define I40IW_SEND_RESET_EVENT 2 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #define MAX_I40IW_IFS 4 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define SET_ACK 0x1 122*4882a593Smuzhiyun #define SET_SYN 0x2 123*4882a593Smuzhiyun #define SET_FIN 0x4 124*4882a593Smuzhiyun #define SET_RST 0x8 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #define TCP_OPTIONS_PADDING 3 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun struct option_base { 129*4882a593Smuzhiyun u8 optionnum; 130*4882a593Smuzhiyun u8 length; 131*4882a593Smuzhiyun }; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun enum option_numbers { 134*4882a593Smuzhiyun OPTION_NUMBER_END, 135*4882a593Smuzhiyun OPTION_NUMBER_NONE, 136*4882a593Smuzhiyun OPTION_NUMBER_MSS, 137*4882a593Smuzhiyun OPTION_NUMBER_WINDOW_SCALE, 138*4882a593Smuzhiyun OPTION_NUMBER_SACK_PERM, 139*4882a593Smuzhiyun OPTION_NUMBER_SACK, 140*4882a593Smuzhiyun OPTION_NUMBER_WRITE0 = 0xbc 141*4882a593Smuzhiyun }; 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun struct option_mss { 144*4882a593Smuzhiyun u8 optionnum; 145*4882a593Smuzhiyun u8 length; 146*4882a593Smuzhiyun __be16 mss; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun struct option_windowscale { 150*4882a593Smuzhiyun u8 optionnum; 151*4882a593Smuzhiyun u8 length; 152*4882a593Smuzhiyun u8 shiftcount; 153*4882a593Smuzhiyun }; 154*4882a593Smuzhiyun 155*4882a593Smuzhiyun union all_known_options { 156*4882a593Smuzhiyun char as_end; 157*4882a593Smuzhiyun struct option_base as_base; 158*4882a593Smuzhiyun struct option_mss as_mss; 159*4882a593Smuzhiyun struct option_windowscale as_windowscale; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun struct i40iw_timer_entry { 163*4882a593Smuzhiyun struct list_head list; 164*4882a593Smuzhiyun unsigned long timetosend; /* jiffies */ 165*4882a593Smuzhiyun struct i40iw_puda_buf *sqbuf; 166*4882a593Smuzhiyun u32 type; 167*4882a593Smuzhiyun u32 retrycount; 168*4882a593Smuzhiyun u32 retranscount; 169*4882a593Smuzhiyun u32 context; 170*4882a593Smuzhiyun u32 send_retrans; 171*4882a593Smuzhiyun int close_when_complete; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #define I40IW_DEFAULT_RETRYS 64 175*4882a593Smuzhiyun #define I40IW_DEFAULT_RETRANS 8 176*4882a593Smuzhiyun #define I40IW_DEFAULT_TTL 0x40 177*4882a593Smuzhiyun #define I40IW_DEFAULT_RTT_VAR 0x6 178*4882a593Smuzhiyun #define I40IW_DEFAULT_SS_THRESH 0x3FFFFFFF 179*4882a593Smuzhiyun #define I40IW_DEFAULT_REXMIT_THRESH 8 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun #define I40IW_RETRY_TIMEOUT HZ 182*4882a593Smuzhiyun #define I40IW_SHORT_TIME 10 183*4882a593Smuzhiyun #define I40IW_LONG_TIME (2 * HZ) 184*4882a593Smuzhiyun #define I40IW_MAX_TIMEOUT ((unsigned long)(12 * HZ)) 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun #define I40IW_CM_HASHTABLE_SIZE 1024 187*4882a593Smuzhiyun #define I40IW_CM_TCP_TIMER_INTERVAL 3000 188*4882a593Smuzhiyun #define I40IW_CM_DEFAULT_MTU 1540 189*4882a593Smuzhiyun #define I40IW_CM_DEFAULT_FRAME_CNT 10 190*4882a593Smuzhiyun #define I40IW_CM_THREAD_STACK_SIZE 256 191*4882a593Smuzhiyun #define I40IW_CM_DEFAULT_RCV_WND 64240 192*4882a593Smuzhiyun #define I40IW_CM_DEFAULT_RCV_WND_SCALED 0x3fffc 193*4882a593Smuzhiyun #define I40IW_CM_DEFAULT_RCV_WND_SCALE 2 194*4882a593Smuzhiyun #define I40IW_CM_DEFAULT_FREE_PKTS 0x000A 195*4882a593Smuzhiyun #define I40IW_CM_FREE_PKT_LO_WATERMARK 2 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun #define I40IW_CM_DEFAULT_MSS 536 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun #define I40IW_CM_DEF_SEQ 0x159bf75f 200*4882a593Smuzhiyun #define I40IW_CM_DEF_LOCAL_ID 0x3b47 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun #define I40IW_CM_DEF_SEQ2 0x18ed5740 203*4882a593Smuzhiyun #define I40IW_CM_DEF_LOCAL_ID2 0xb807 204*4882a593Smuzhiyun #define MAX_CM_BUFFER (I40IW_MAX_IETF_SIZE + IETF_MAX_PRIV_DATA_LEN) 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun typedef u32 i40iw_addr_t; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun #define i40iw_cm_tsa_context i40iw_qp_context 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun struct i40iw_qp; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun /* cm node transition states */ 213*4882a593Smuzhiyun enum i40iw_cm_node_state { 214*4882a593Smuzhiyun I40IW_CM_STATE_UNKNOWN, 215*4882a593Smuzhiyun I40IW_CM_STATE_INITED, 216*4882a593Smuzhiyun I40IW_CM_STATE_LISTENING, 217*4882a593Smuzhiyun I40IW_CM_STATE_SYN_RCVD, 218*4882a593Smuzhiyun I40IW_CM_STATE_SYN_SENT, 219*4882a593Smuzhiyun I40IW_CM_STATE_ONE_SIDE_ESTABLISHED, 220*4882a593Smuzhiyun I40IW_CM_STATE_ESTABLISHED, 221*4882a593Smuzhiyun I40IW_CM_STATE_ACCEPTING, 222*4882a593Smuzhiyun I40IW_CM_STATE_MPAREQ_SENT, 223*4882a593Smuzhiyun I40IW_CM_STATE_MPAREQ_RCVD, 224*4882a593Smuzhiyun I40IW_CM_STATE_MPAREJ_RCVD, 225*4882a593Smuzhiyun I40IW_CM_STATE_OFFLOADED, 226*4882a593Smuzhiyun I40IW_CM_STATE_FIN_WAIT1, 227*4882a593Smuzhiyun I40IW_CM_STATE_FIN_WAIT2, 228*4882a593Smuzhiyun I40IW_CM_STATE_CLOSE_WAIT, 229*4882a593Smuzhiyun I40IW_CM_STATE_TIME_WAIT, 230*4882a593Smuzhiyun I40IW_CM_STATE_LAST_ACK, 231*4882a593Smuzhiyun I40IW_CM_STATE_CLOSING, 232*4882a593Smuzhiyun I40IW_CM_STATE_LISTENER_DESTROYED, 233*4882a593Smuzhiyun I40IW_CM_STATE_CLOSED 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun 236*4882a593Smuzhiyun enum mpa_frame_version { 237*4882a593Smuzhiyun IETF_MPA_V1 = 1, 238*4882a593Smuzhiyun IETF_MPA_V2 = 2 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun enum mpa_frame_key { 242*4882a593Smuzhiyun MPA_KEY_REQUEST, 243*4882a593Smuzhiyun MPA_KEY_REPLY 244*4882a593Smuzhiyun }; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun enum send_rdma0 { 247*4882a593Smuzhiyun SEND_RDMA_READ_ZERO = 1, 248*4882a593Smuzhiyun SEND_RDMA_WRITE_ZERO = 2 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun enum i40iw_tcpip_pkt_type { 252*4882a593Smuzhiyun I40IW_PKT_TYPE_UNKNOWN, 253*4882a593Smuzhiyun I40IW_PKT_TYPE_SYN, 254*4882a593Smuzhiyun I40IW_PKT_TYPE_SYNACK, 255*4882a593Smuzhiyun I40IW_PKT_TYPE_ACK, 256*4882a593Smuzhiyun I40IW_PKT_TYPE_FIN, 257*4882a593Smuzhiyun I40IW_PKT_TYPE_RST 258*4882a593Smuzhiyun }; 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun /* CM context params */ 261*4882a593Smuzhiyun struct i40iw_cm_tcp_context { 262*4882a593Smuzhiyun u8 client; 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun u32 loc_seq_num; 265*4882a593Smuzhiyun u32 loc_ack_num; 266*4882a593Smuzhiyun u32 rem_ack_num; 267*4882a593Smuzhiyun u32 rcv_nxt; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun u32 loc_id; 270*4882a593Smuzhiyun u32 rem_id; 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun u32 snd_wnd; 273*4882a593Smuzhiyun u32 max_snd_wnd; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun u32 rcv_wnd; 276*4882a593Smuzhiyun u32 mss; 277*4882a593Smuzhiyun u8 snd_wscale; 278*4882a593Smuzhiyun u8 rcv_wscale; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun enum i40iw_cm_listener_state { 282*4882a593Smuzhiyun I40IW_CM_LISTENER_PASSIVE_STATE = 1, 283*4882a593Smuzhiyun I40IW_CM_LISTENER_ACTIVE_STATE = 2, 284*4882a593Smuzhiyun I40IW_CM_LISTENER_EITHER_STATE = 3 285*4882a593Smuzhiyun }; 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun struct i40iw_cm_listener { 288*4882a593Smuzhiyun struct list_head list; 289*4882a593Smuzhiyun struct i40iw_cm_core *cm_core; 290*4882a593Smuzhiyun u8 loc_mac[ETH_ALEN]; 291*4882a593Smuzhiyun u32 loc_addr[4]; 292*4882a593Smuzhiyun u16 loc_port; 293*4882a593Smuzhiyun struct iw_cm_id *cm_id; 294*4882a593Smuzhiyun atomic_t ref_count; 295*4882a593Smuzhiyun struct i40iw_device *iwdev; 296*4882a593Smuzhiyun atomic_t pend_accepts_cnt; 297*4882a593Smuzhiyun int backlog; 298*4882a593Smuzhiyun enum i40iw_cm_listener_state listener_state; 299*4882a593Smuzhiyun u32 reused_node; 300*4882a593Smuzhiyun u8 user_pri; 301*4882a593Smuzhiyun u8 tos; 302*4882a593Smuzhiyun u16 vlan_id; 303*4882a593Smuzhiyun bool qhash_set; 304*4882a593Smuzhiyun bool ipv4; 305*4882a593Smuzhiyun struct list_head child_listen_list; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun }; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun struct i40iw_kmem_info { 310*4882a593Smuzhiyun void *addr; 311*4882a593Smuzhiyun u32 size; 312*4882a593Smuzhiyun }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun /* per connection node and node state information */ 315*4882a593Smuzhiyun struct i40iw_cm_node { 316*4882a593Smuzhiyun u32 loc_addr[4], rem_addr[4]; 317*4882a593Smuzhiyun u16 loc_port, rem_port; 318*4882a593Smuzhiyun u16 vlan_id; 319*4882a593Smuzhiyun enum i40iw_cm_node_state state; 320*4882a593Smuzhiyun u8 loc_mac[ETH_ALEN]; 321*4882a593Smuzhiyun u8 rem_mac[ETH_ALEN]; 322*4882a593Smuzhiyun atomic_t ref_count; 323*4882a593Smuzhiyun struct i40iw_qp *iwqp; 324*4882a593Smuzhiyun struct i40iw_device *iwdev; 325*4882a593Smuzhiyun struct i40iw_sc_dev *dev; 326*4882a593Smuzhiyun struct i40iw_cm_tcp_context tcp_cntxt; 327*4882a593Smuzhiyun struct i40iw_cm_core *cm_core; 328*4882a593Smuzhiyun struct i40iw_cm_node *loopbackpartner; 329*4882a593Smuzhiyun struct i40iw_timer_entry *send_entry; 330*4882a593Smuzhiyun struct i40iw_timer_entry *close_entry; 331*4882a593Smuzhiyun spinlock_t retrans_list_lock; /* cm transmit packet */ 332*4882a593Smuzhiyun enum send_rdma0 send_rdma0_op; 333*4882a593Smuzhiyun u16 ird_size; 334*4882a593Smuzhiyun u16 ord_size; 335*4882a593Smuzhiyun u16 mpav2_ird_ord; 336*4882a593Smuzhiyun struct iw_cm_id *cm_id; 337*4882a593Smuzhiyun struct list_head list; 338*4882a593Smuzhiyun bool accelerated; 339*4882a593Smuzhiyun struct i40iw_cm_listener *listener; 340*4882a593Smuzhiyun int apbvt_set; 341*4882a593Smuzhiyun int accept_pend; 342*4882a593Smuzhiyun struct list_head timer_entry; 343*4882a593Smuzhiyun struct list_head reset_entry; 344*4882a593Smuzhiyun struct list_head teardown_entry; 345*4882a593Smuzhiyun atomic_t passive_state; 346*4882a593Smuzhiyun bool qhash_set; 347*4882a593Smuzhiyun u8 user_pri; 348*4882a593Smuzhiyun u8 tos; 349*4882a593Smuzhiyun bool ipv4; 350*4882a593Smuzhiyun bool snd_mark_en; 351*4882a593Smuzhiyun u16 lsmm_size; 352*4882a593Smuzhiyun enum mpa_frame_version mpa_frame_rev; 353*4882a593Smuzhiyun struct i40iw_kmem_info pdata; 354*4882a593Smuzhiyun union { 355*4882a593Smuzhiyun struct ietf_mpa_v1 mpa_frame; 356*4882a593Smuzhiyun struct ietf_mpa_v2 mpa_v2_frame; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun u8 pdata_buf[IETF_MAX_PRIV_DATA_LEN]; 360*4882a593Smuzhiyun struct i40iw_kmem_info mpa_hdr; 361*4882a593Smuzhiyun bool ack_rcvd; 362*4882a593Smuzhiyun }; 363*4882a593Smuzhiyun 364*4882a593Smuzhiyun /* structure for client or CM to fill when making CM api calls. */ 365*4882a593Smuzhiyun /* - only need to set relevant data, based on op. */ 366*4882a593Smuzhiyun struct i40iw_cm_info { 367*4882a593Smuzhiyun struct iw_cm_id *cm_id; 368*4882a593Smuzhiyun u16 loc_port; 369*4882a593Smuzhiyun u16 rem_port; 370*4882a593Smuzhiyun u32 loc_addr[4]; 371*4882a593Smuzhiyun u32 rem_addr[4]; 372*4882a593Smuzhiyun u16 vlan_id; 373*4882a593Smuzhiyun int backlog; 374*4882a593Smuzhiyun u8 user_pri; 375*4882a593Smuzhiyun u8 tos; 376*4882a593Smuzhiyun bool ipv4; 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun /* CM event codes */ 380*4882a593Smuzhiyun enum i40iw_cm_event_type { 381*4882a593Smuzhiyun I40IW_CM_EVENT_UNKNOWN, 382*4882a593Smuzhiyun I40IW_CM_EVENT_ESTABLISHED, 383*4882a593Smuzhiyun I40IW_CM_EVENT_MPA_REQ, 384*4882a593Smuzhiyun I40IW_CM_EVENT_MPA_CONNECT, 385*4882a593Smuzhiyun I40IW_CM_EVENT_MPA_ACCEPT, 386*4882a593Smuzhiyun I40IW_CM_EVENT_MPA_REJECT, 387*4882a593Smuzhiyun I40IW_CM_EVENT_MPA_ESTABLISHED, 388*4882a593Smuzhiyun I40IW_CM_EVENT_CONNECTED, 389*4882a593Smuzhiyun I40IW_CM_EVENT_RESET, 390*4882a593Smuzhiyun I40IW_CM_EVENT_ABORTED 391*4882a593Smuzhiyun }; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun /* event to post to CM event handler */ 394*4882a593Smuzhiyun struct i40iw_cm_event { 395*4882a593Smuzhiyun enum i40iw_cm_event_type type; 396*4882a593Smuzhiyun struct i40iw_cm_info cm_info; 397*4882a593Smuzhiyun struct work_struct event_work; 398*4882a593Smuzhiyun struct i40iw_cm_node *cm_node; 399*4882a593Smuzhiyun }; 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun struct i40iw_cm_core { 402*4882a593Smuzhiyun struct i40iw_device *iwdev; 403*4882a593Smuzhiyun struct i40iw_sc_dev *dev; 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun struct list_head listen_nodes; 406*4882a593Smuzhiyun struct list_head accelerated_list; 407*4882a593Smuzhiyun struct list_head non_accelerated_list; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun struct timer_list tcp_timer; 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun struct workqueue_struct *event_wq; 412*4882a593Smuzhiyun struct workqueue_struct *disconn_wq; 413*4882a593Smuzhiyun 414*4882a593Smuzhiyun spinlock_t ht_lock; /* manage hash table */ 415*4882a593Smuzhiyun spinlock_t listen_list_lock; /* listen list */ 416*4882a593Smuzhiyun spinlock_t apbvt_lock; /*manage apbvt entries*/ 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun unsigned long ports_in_use[BITS_TO_LONGS(MAX_PORTS)]; 419*4882a593Smuzhiyun 420*4882a593Smuzhiyun u64 stats_nodes_created; 421*4882a593Smuzhiyun u64 stats_nodes_destroyed; 422*4882a593Smuzhiyun u64 stats_listen_created; 423*4882a593Smuzhiyun u64 stats_listen_destroyed; 424*4882a593Smuzhiyun u64 stats_listen_nodes_created; 425*4882a593Smuzhiyun u64 stats_listen_nodes_destroyed; 426*4882a593Smuzhiyun u64 stats_loopbacks; 427*4882a593Smuzhiyun u64 stats_accepts; 428*4882a593Smuzhiyun u64 stats_rejects; 429*4882a593Smuzhiyun u64 stats_connect_errs; 430*4882a593Smuzhiyun u64 stats_passive_errs; 431*4882a593Smuzhiyun u64 stats_pkt_retrans; 432*4882a593Smuzhiyun u64 stats_backlog_drops; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun int i40iw_schedule_cm_timer(struct i40iw_cm_node *cm_node, 436*4882a593Smuzhiyun struct i40iw_puda_buf *sqbuf, 437*4882a593Smuzhiyun enum i40iw_timer_type type, 438*4882a593Smuzhiyun int send_retrans, 439*4882a593Smuzhiyun int close_when_complete); 440*4882a593Smuzhiyun 441*4882a593Smuzhiyun int i40iw_accept(struct iw_cm_id *, struct iw_cm_conn_param *); 442*4882a593Smuzhiyun int i40iw_reject(struct iw_cm_id *, const void *, u8); 443*4882a593Smuzhiyun int i40iw_connect(struct iw_cm_id *, struct iw_cm_conn_param *); 444*4882a593Smuzhiyun int i40iw_create_listen(struct iw_cm_id *, int); 445*4882a593Smuzhiyun int i40iw_destroy_listen(struct iw_cm_id *); 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun int i40iw_cm_start(struct i40iw_device *); 448*4882a593Smuzhiyun int i40iw_cm_stop(struct i40iw_device *); 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun int i40iw_arp_table(struct i40iw_device *iwdev, 451*4882a593Smuzhiyun u32 *ip_addr, 452*4882a593Smuzhiyun bool ipv4, 453*4882a593Smuzhiyun u8 *mac_addr, 454*4882a593Smuzhiyun u32 action); 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun void i40iw_if_notify(struct i40iw_device *iwdev, struct net_device *netdev, 457*4882a593Smuzhiyun u32 *ipaddr, bool ipv4, bool ifup); 458*4882a593Smuzhiyun void i40iw_cm_teardown_connections(struct i40iw_device *iwdev, u32 *ipaddr, 459*4882a593Smuzhiyun struct i40iw_cm_info *nfo, 460*4882a593Smuzhiyun bool disconnect_all); 461*4882a593Smuzhiyun bool i40iw_port_in_use(struct i40iw_cm_core *cm_core, u16 port); 462*4882a593Smuzhiyun #endif /* I40IW_CM_H */ 463