1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright(c) 2017 - 2018 Intel Corporation.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is provided under a dual BSD/GPLv2 license. When using or
5*4882a593Smuzhiyun * redistributing this file, you may do so under either license.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * GPL LICENSE SUMMARY
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
10*4882a593Smuzhiyun * it under the terms of version 2 of the GNU General Public License as
11*4882a593Smuzhiyun * published by the Free Software Foundation.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but
14*4882a593Smuzhiyun * WITHOUT ANY WARRANTY; without even the implied warranty of
15*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16*4882a593Smuzhiyun * General Public License for more details.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * BSD LICENSE
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without
21*4882a593Smuzhiyun * modification, are permitted provided that the following conditions
22*4882a593Smuzhiyun * are met:
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * - Redistributions of source code must retain the above copyright
25*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer.
26*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above copyright
27*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in
28*4882a593Smuzhiyun * the documentation and/or other materials provided with the
29*4882a593Smuzhiyun * distribution.
30*4882a593Smuzhiyun * - Neither the name of Intel Corporation nor the names of its
31*4882a593Smuzhiyun * contributors may be used to endorse or promote products derived
32*4882a593Smuzhiyun * from this software without specific prior written permission.
33*4882a593Smuzhiyun *
34*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35*4882a593Smuzhiyun * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36*4882a593Smuzhiyun * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37*4882a593Smuzhiyun * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38*4882a593Smuzhiyun * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39*4882a593Smuzhiyun * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40*4882a593Smuzhiyun * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41*4882a593Smuzhiyun * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42*4882a593Smuzhiyun * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44*4882a593Smuzhiyun * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45*4882a593Smuzhiyun *
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /*
49*4882a593Smuzhiyun * This file contains HFI1 support for VNIC SDMA functionality
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #include "sdma.h"
53*4882a593Smuzhiyun #include "vnic.h"
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define HFI1_VNIC_SDMA_Q_ACTIVE BIT(0)
56*4882a593Smuzhiyun #define HFI1_VNIC_SDMA_Q_DEFERRED BIT(1)
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define HFI1_VNIC_TXREQ_NAME_LEN 32
59*4882a593Smuzhiyun #define HFI1_VNIC_SDMA_DESC_WTRMRK 64
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /*
62*4882a593Smuzhiyun * struct vnic_txreq - VNIC transmit descriptor
63*4882a593Smuzhiyun * @txreq: sdma transmit request
64*4882a593Smuzhiyun * @sdma: vnic sdma pointer
65*4882a593Smuzhiyun * @skb: skb to send
66*4882a593Smuzhiyun * @pad: pad buffer
67*4882a593Smuzhiyun * @plen: pad length
68*4882a593Smuzhiyun * @pbc_val: pbc value
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun struct vnic_txreq {
71*4882a593Smuzhiyun struct sdma_txreq txreq;
72*4882a593Smuzhiyun struct hfi1_vnic_sdma *sdma;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun struct sk_buff *skb;
75*4882a593Smuzhiyun unsigned char pad[HFI1_VNIC_MAX_PAD];
76*4882a593Smuzhiyun u16 plen;
77*4882a593Smuzhiyun __le64 pbc_val;
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
vnic_sdma_complete(struct sdma_txreq * txreq,int status)80*4882a593Smuzhiyun static void vnic_sdma_complete(struct sdma_txreq *txreq,
81*4882a593Smuzhiyun int status)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun struct vnic_txreq *tx = container_of(txreq, struct vnic_txreq, txreq);
84*4882a593Smuzhiyun struct hfi1_vnic_sdma *vnic_sdma = tx->sdma;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun sdma_txclean(vnic_sdma->dd, txreq);
87*4882a593Smuzhiyun dev_kfree_skb_any(tx->skb);
88*4882a593Smuzhiyun kmem_cache_free(vnic_sdma->dd->vnic.txreq_cache, tx);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
build_vnic_ulp_payload(struct sdma_engine * sde,struct vnic_txreq * tx)91*4882a593Smuzhiyun static noinline int build_vnic_ulp_payload(struct sdma_engine *sde,
92*4882a593Smuzhiyun struct vnic_txreq *tx)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun int i, ret = 0;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun ret = sdma_txadd_kvaddr(
97*4882a593Smuzhiyun sde->dd,
98*4882a593Smuzhiyun &tx->txreq,
99*4882a593Smuzhiyun tx->skb->data,
100*4882a593Smuzhiyun skb_headlen(tx->skb));
101*4882a593Smuzhiyun if (unlikely(ret))
102*4882a593Smuzhiyun goto bail_txadd;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun for (i = 0; i < skb_shinfo(tx->skb)->nr_frags; i++) {
105*4882a593Smuzhiyun skb_frag_t *frag = &skb_shinfo(tx->skb)->frags[i];
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* combine physically continuous fragments later? */
108*4882a593Smuzhiyun ret = sdma_txadd_page(sde->dd,
109*4882a593Smuzhiyun &tx->txreq,
110*4882a593Smuzhiyun skb_frag_page(frag),
111*4882a593Smuzhiyun skb_frag_off(frag),
112*4882a593Smuzhiyun skb_frag_size(frag));
113*4882a593Smuzhiyun if (unlikely(ret))
114*4882a593Smuzhiyun goto bail_txadd;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun if (tx->plen)
118*4882a593Smuzhiyun ret = sdma_txadd_kvaddr(sde->dd, &tx->txreq,
119*4882a593Smuzhiyun tx->pad + HFI1_VNIC_MAX_PAD - tx->plen,
120*4882a593Smuzhiyun tx->plen);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun bail_txadd:
123*4882a593Smuzhiyun return ret;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
build_vnic_tx_desc(struct sdma_engine * sde,struct vnic_txreq * tx,u64 pbc)126*4882a593Smuzhiyun static int build_vnic_tx_desc(struct sdma_engine *sde,
127*4882a593Smuzhiyun struct vnic_txreq *tx,
128*4882a593Smuzhiyun u64 pbc)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun int ret = 0;
131*4882a593Smuzhiyun u16 hdrbytes = 2 << 2; /* PBC */
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun ret = sdma_txinit_ahg(
134*4882a593Smuzhiyun &tx->txreq,
135*4882a593Smuzhiyun 0,
136*4882a593Smuzhiyun hdrbytes + tx->skb->len + tx->plen,
137*4882a593Smuzhiyun 0,
138*4882a593Smuzhiyun 0,
139*4882a593Smuzhiyun NULL,
140*4882a593Smuzhiyun 0,
141*4882a593Smuzhiyun vnic_sdma_complete);
142*4882a593Smuzhiyun if (unlikely(ret))
143*4882a593Smuzhiyun goto bail_txadd;
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun /* add pbc */
146*4882a593Smuzhiyun tx->pbc_val = cpu_to_le64(pbc);
147*4882a593Smuzhiyun ret = sdma_txadd_kvaddr(
148*4882a593Smuzhiyun sde->dd,
149*4882a593Smuzhiyun &tx->txreq,
150*4882a593Smuzhiyun &tx->pbc_val,
151*4882a593Smuzhiyun hdrbytes);
152*4882a593Smuzhiyun if (unlikely(ret))
153*4882a593Smuzhiyun goto bail_txadd;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun /* add the ulp payload */
156*4882a593Smuzhiyun ret = build_vnic_ulp_payload(sde, tx);
157*4882a593Smuzhiyun bail_txadd:
158*4882a593Smuzhiyun return ret;
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun /* setup the last plen bypes of pad */
hfi1_vnic_update_pad(unsigned char * pad,u8 plen)162*4882a593Smuzhiyun static inline void hfi1_vnic_update_pad(unsigned char *pad, u8 plen)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun pad[HFI1_VNIC_MAX_PAD - 1] = plen - OPA_VNIC_ICRC_TAIL_LEN;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
hfi1_vnic_send_dma(struct hfi1_devdata * dd,u8 q_idx,struct hfi1_vnic_vport_info * vinfo,struct sk_buff * skb,u64 pbc,u8 plen)167*4882a593Smuzhiyun int hfi1_vnic_send_dma(struct hfi1_devdata *dd, u8 q_idx,
168*4882a593Smuzhiyun struct hfi1_vnic_vport_info *vinfo,
169*4882a593Smuzhiyun struct sk_buff *skb, u64 pbc, u8 plen)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun struct hfi1_vnic_sdma *vnic_sdma = &vinfo->sdma[q_idx];
172*4882a593Smuzhiyun struct sdma_engine *sde = vnic_sdma->sde;
173*4882a593Smuzhiyun struct vnic_txreq *tx;
174*4882a593Smuzhiyun int ret = -ECOMM;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun if (unlikely(READ_ONCE(vnic_sdma->state) != HFI1_VNIC_SDMA_Q_ACTIVE))
177*4882a593Smuzhiyun goto tx_err;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun if (unlikely(!sde || !sdma_running(sde)))
180*4882a593Smuzhiyun goto tx_err;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun tx = kmem_cache_alloc(dd->vnic.txreq_cache, GFP_ATOMIC);
183*4882a593Smuzhiyun if (unlikely(!tx)) {
184*4882a593Smuzhiyun ret = -ENOMEM;
185*4882a593Smuzhiyun goto tx_err;
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun tx->sdma = vnic_sdma;
189*4882a593Smuzhiyun tx->skb = skb;
190*4882a593Smuzhiyun hfi1_vnic_update_pad(tx->pad, plen);
191*4882a593Smuzhiyun tx->plen = plen;
192*4882a593Smuzhiyun ret = build_vnic_tx_desc(sde, tx, pbc);
193*4882a593Smuzhiyun if (unlikely(ret))
194*4882a593Smuzhiyun goto free_desc;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun ret = sdma_send_txreq(sde, iowait_get_ib_work(&vnic_sdma->wait),
197*4882a593Smuzhiyun &tx->txreq, vnic_sdma->pkts_sent);
198*4882a593Smuzhiyun /* When -ECOMM, sdma callback will be called with ABORT status */
199*4882a593Smuzhiyun if (unlikely(ret && unlikely(ret != -ECOMM)))
200*4882a593Smuzhiyun goto free_desc;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun if (!ret) {
203*4882a593Smuzhiyun vnic_sdma->pkts_sent = true;
204*4882a593Smuzhiyun iowait_starve_clear(vnic_sdma->pkts_sent, &vnic_sdma->wait);
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun return ret;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun free_desc:
209*4882a593Smuzhiyun sdma_txclean(dd, &tx->txreq);
210*4882a593Smuzhiyun kmem_cache_free(dd->vnic.txreq_cache, tx);
211*4882a593Smuzhiyun tx_err:
212*4882a593Smuzhiyun if (ret != -EBUSY)
213*4882a593Smuzhiyun dev_kfree_skb_any(skb);
214*4882a593Smuzhiyun else
215*4882a593Smuzhiyun vnic_sdma->pkts_sent = false;
216*4882a593Smuzhiyun return ret;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun /*
220*4882a593Smuzhiyun * hfi1_vnic_sdma_sleep - vnic sdma sleep function
221*4882a593Smuzhiyun *
222*4882a593Smuzhiyun * This function gets called from sdma_send_txreq() when there are not enough
223*4882a593Smuzhiyun * sdma descriptors available to send the packet. It adds Tx queue's wait
224*4882a593Smuzhiyun * structure to sdma engine's dmawait list to be woken up when descriptors
225*4882a593Smuzhiyun * become available.
226*4882a593Smuzhiyun */
hfi1_vnic_sdma_sleep(struct sdma_engine * sde,struct iowait_work * wait,struct sdma_txreq * txreq,uint seq,bool pkts_sent)227*4882a593Smuzhiyun static int hfi1_vnic_sdma_sleep(struct sdma_engine *sde,
228*4882a593Smuzhiyun struct iowait_work *wait,
229*4882a593Smuzhiyun struct sdma_txreq *txreq,
230*4882a593Smuzhiyun uint seq,
231*4882a593Smuzhiyun bool pkts_sent)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun struct hfi1_vnic_sdma *vnic_sdma =
234*4882a593Smuzhiyun container_of(wait->iow, struct hfi1_vnic_sdma, wait);
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun write_seqlock(&sde->waitlock);
237*4882a593Smuzhiyun if (sdma_progress(sde, seq, txreq)) {
238*4882a593Smuzhiyun write_sequnlock(&sde->waitlock);
239*4882a593Smuzhiyun return -EAGAIN;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun vnic_sdma->state = HFI1_VNIC_SDMA_Q_DEFERRED;
243*4882a593Smuzhiyun if (list_empty(&vnic_sdma->wait.list)) {
244*4882a593Smuzhiyun iowait_get_priority(wait->iow);
245*4882a593Smuzhiyun iowait_queue(pkts_sent, wait->iow, &sde->dmawait);
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun write_sequnlock(&sde->waitlock);
248*4882a593Smuzhiyun return -EBUSY;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun /*
252*4882a593Smuzhiyun * hfi1_vnic_sdma_wakeup - vnic sdma wakeup function
253*4882a593Smuzhiyun *
254*4882a593Smuzhiyun * This function gets called when SDMA descriptors becomes available and Tx
255*4882a593Smuzhiyun * queue's wait structure was previously added to sdma engine's dmawait list.
256*4882a593Smuzhiyun * It notifies the upper driver about Tx queue wakeup.
257*4882a593Smuzhiyun */
hfi1_vnic_sdma_wakeup(struct iowait * wait,int reason)258*4882a593Smuzhiyun static void hfi1_vnic_sdma_wakeup(struct iowait *wait, int reason)
259*4882a593Smuzhiyun {
260*4882a593Smuzhiyun struct hfi1_vnic_sdma *vnic_sdma =
261*4882a593Smuzhiyun container_of(wait, struct hfi1_vnic_sdma, wait);
262*4882a593Smuzhiyun struct hfi1_vnic_vport_info *vinfo = vnic_sdma->vinfo;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun vnic_sdma->state = HFI1_VNIC_SDMA_Q_ACTIVE;
265*4882a593Smuzhiyun if (__netif_subqueue_stopped(vinfo->netdev, vnic_sdma->q_idx))
266*4882a593Smuzhiyun netif_wake_subqueue(vinfo->netdev, vnic_sdma->q_idx);
267*4882a593Smuzhiyun };
268*4882a593Smuzhiyun
hfi1_vnic_sdma_write_avail(struct hfi1_vnic_vport_info * vinfo,u8 q_idx)269*4882a593Smuzhiyun inline bool hfi1_vnic_sdma_write_avail(struct hfi1_vnic_vport_info *vinfo,
270*4882a593Smuzhiyun u8 q_idx)
271*4882a593Smuzhiyun {
272*4882a593Smuzhiyun struct hfi1_vnic_sdma *vnic_sdma = &vinfo->sdma[q_idx];
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun return (READ_ONCE(vnic_sdma->state) == HFI1_VNIC_SDMA_Q_ACTIVE);
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun
hfi1_vnic_sdma_init(struct hfi1_vnic_vport_info * vinfo)277*4882a593Smuzhiyun void hfi1_vnic_sdma_init(struct hfi1_vnic_vport_info *vinfo)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun int i;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun for (i = 0; i < vinfo->num_tx_q; i++) {
282*4882a593Smuzhiyun struct hfi1_vnic_sdma *vnic_sdma = &vinfo->sdma[i];
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun iowait_init(&vnic_sdma->wait, 0, NULL, NULL,
285*4882a593Smuzhiyun hfi1_vnic_sdma_sleep,
286*4882a593Smuzhiyun hfi1_vnic_sdma_wakeup, NULL, NULL);
287*4882a593Smuzhiyun vnic_sdma->sde = &vinfo->dd->per_sdma[i];
288*4882a593Smuzhiyun vnic_sdma->dd = vinfo->dd;
289*4882a593Smuzhiyun vnic_sdma->vinfo = vinfo;
290*4882a593Smuzhiyun vnic_sdma->q_idx = i;
291*4882a593Smuzhiyun vnic_sdma->state = HFI1_VNIC_SDMA_Q_ACTIVE;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun /* Add a free descriptor watermark for wakeups */
294*4882a593Smuzhiyun if (vnic_sdma->sde->descq_cnt > HFI1_VNIC_SDMA_DESC_WTRMRK) {
295*4882a593Smuzhiyun struct iowait_work *work;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun INIT_LIST_HEAD(&vnic_sdma->stx.list);
298*4882a593Smuzhiyun vnic_sdma->stx.num_desc = HFI1_VNIC_SDMA_DESC_WTRMRK;
299*4882a593Smuzhiyun work = iowait_get_ib_work(&vnic_sdma->wait);
300*4882a593Smuzhiyun list_add_tail(&vnic_sdma->stx.list, &work->tx_head);
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun
hfi1_vnic_txreq_init(struct hfi1_devdata * dd)305*4882a593Smuzhiyun int hfi1_vnic_txreq_init(struct hfi1_devdata *dd)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun char buf[HFI1_VNIC_TXREQ_NAME_LEN];
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun snprintf(buf, sizeof(buf), "hfi1_%u_vnic_txreq_cache", dd->unit);
310*4882a593Smuzhiyun dd->vnic.txreq_cache = kmem_cache_create(buf,
311*4882a593Smuzhiyun sizeof(struct vnic_txreq),
312*4882a593Smuzhiyun 0, SLAB_HWCACHE_ALIGN,
313*4882a593Smuzhiyun NULL);
314*4882a593Smuzhiyun if (!dd->vnic.txreq_cache)
315*4882a593Smuzhiyun return -ENOMEM;
316*4882a593Smuzhiyun return 0;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun
hfi1_vnic_txreq_deinit(struct hfi1_devdata * dd)319*4882a593Smuzhiyun void hfi1_vnic_txreq_deinit(struct hfi1_devdata *dd)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun kmem_cache_destroy(dd->vnic.txreq_cache);
322*4882a593Smuzhiyun dd->vnic.txreq_cache = NULL;
323*4882a593Smuzhiyun }
324