xref: /OK3568_Linux_fs/kernel/drivers/infiniband/hw/hfi1/user_sdma.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun #ifndef _HFI1_USER_SDMA_H
2*4882a593Smuzhiyun #define _HFI1_USER_SDMA_H
3*4882a593Smuzhiyun /*
4*4882a593Smuzhiyun  * Copyright(c) 2020 - Cornelis Networks, Inc.
5*4882a593Smuzhiyun  * Copyright(c) 2015 - 2018 Intel Corporation.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * This file is provided under a dual BSD/GPLv2 license.  When using or
8*4882a593Smuzhiyun  * redistributing this file, you may do so under either license.
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * GPL LICENSE SUMMARY
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify
13*4882a593Smuzhiyun  * it under the terms of version 2 of the GNU General Public License as
14*4882a593Smuzhiyun  * published by the Free Software Foundation.
15*4882a593Smuzhiyun  *
16*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but
17*4882a593Smuzhiyun  * WITHOUT ANY WARRANTY; without even the implied warranty of
18*4882a593Smuzhiyun  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
19*4882a593Smuzhiyun  * General Public License for more details.
20*4882a593Smuzhiyun  *
21*4882a593Smuzhiyun  * BSD LICENSE
22*4882a593Smuzhiyun  *
23*4882a593Smuzhiyun  * Redistribution and use in source and binary forms, with or without
24*4882a593Smuzhiyun  * modification, are permitted provided that the following conditions
25*4882a593Smuzhiyun  * are met:
26*4882a593Smuzhiyun  *
27*4882a593Smuzhiyun  *  - Redistributions of source code must retain the above copyright
28*4882a593Smuzhiyun  *    notice, this list of conditions and the following disclaimer.
29*4882a593Smuzhiyun  *  - Redistributions in binary form must reproduce the above copyright
30*4882a593Smuzhiyun  *    notice, this list of conditions and the following disclaimer in
31*4882a593Smuzhiyun  *    the documentation and/or other materials provided with the
32*4882a593Smuzhiyun  *    distribution.
33*4882a593Smuzhiyun  *  - Neither the name of Intel Corporation nor the names of its
34*4882a593Smuzhiyun  *    contributors may be used to endorse or promote products derived
35*4882a593Smuzhiyun  *    from this software without specific prior written permission.
36*4882a593Smuzhiyun  *
37*4882a593Smuzhiyun  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
38*4882a593Smuzhiyun  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
39*4882a593Smuzhiyun  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
40*4882a593Smuzhiyun  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
41*4882a593Smuzhiyun  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
42*4882a593Smuzhiyun  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
43*4882a593Smuzhiyun  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
44*4882a593Smuzhiyun  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
45*4882a593Smuzhiyun  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46*4882a593Smuzhiyun  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
47*4882a593Smuzhiyun  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48*4882a593Smuzhiyun  *
49*4882a593Smuzhiyun  */
50*4882a593Smuzhiyun #include <linux/device.h>
51*4882a593Smuzhiyun #include <linux/wait.h>
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #include "common.h"
54*4882a593Smuzhiyun #include "iowait.h"
55*4882a593Smuzhiyun #include "user_exp_rcv.h"
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun /* The maximum number of Data io vectors per message/request */
58*4882a593Smuzhiyun #define MAX_VECTORS_PER_REQ 8
59*4882a593Smuzhiyun /*
60*4882a593Smuzhiyun  * Maximum number of packet to send from each message/request
61*4882a593Smuzhiyun  * before moving to the next one.
62*4882a593Smuzhiyun  */
63*4882a593Smuzhiyun #define MAX_PKTS_PER_QUEUE 16
64*4882a593Smuzhiyun 
65*4882a593Smuzhiyun #define num_pages(x) (1 + ((((x) - 1) & PAGE_MASK) >> PAGE_SHIFT))
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun #define req_opcode(x) \
68*4882a593Smuzhiyun 	(((x) >> HFI1_SDMA_REQ_OPCODE_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK)
69*4882a593Smuzhiyun #define req_version(x) \
70*4882a593Smuzhiyun 	(((x) >> HFI1_SDMA_REQ_VERSION_SHIFT) & HFI1_SDMA_REQ_OPCODE_MASK)
71*4882a593Smuzhiyun #define req_iovcnt(x) \
72*4882a593Smuzhiyun 	(((x) >> HFI1_SDMA_REQ_IOVCNT_SHIFT) & HFI1_SDMA_REQ_IOVCNT_MASK)
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun /* Number of BTH.PSN bits used for sequence number in expected rcvs */
75*4882a593Smuzhiyun #define BTH_SEQ_MASK 0x7ffull
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun #define AHG_KDETH_INTR_SHIFT 12
78*4882a593Smuzhiyun #define AHG_KDETH_SH_SHIFT   13
79*4882a593Smuzhiyun #define AHG_KDETH_ARRAY_SIZE  9
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun #define PBC2LRH(x) ((((x) & 0xfff) << 2) - 4)
82*4882a593Smuzhiyun #define LRH2PBC(x) ((((x) >> 2) + 1) & 0xfff)
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun /**
85*4882a593Smuzhiyun  * Build an SDMA AHG header update descriptor and save it to an array.
86*4882a593Smuzhiyun  * @arr        - Array to save the descriptor to.
87*4882a593Smuzhiyun  * @idx        - Index of the array at which the descriptor will be saved.
88*4882a593Smuzhiyun  * @array_size - Size of the array arr.
89*4882a593Smuzhiyun  * @dw         - Update index into the header in DWs.
90*4882a593Smuzhiyun  * @bit        - Start bit.
91*4882a593Smuzhiyun  * @width      - Field width.
92*4882a593Smuzhiyun  * @value      - 16 bits of immediate data to write into the field.
93*4882a593Smuzhiyun  * Returns -ERANGE if idx is invalid. If successful, returns the next index
94*4882a593Smuzhiyun  * (idx + 1) of the array to be used for the next descriptor.
95*4882a593Smuzhiyun  */
ahg_header_set(u32 * arr,int idx,size_t array_size,u8 dw,u8 bit,u8 width,u16 value)96*4882a593Smuzhiyun static inline int ahg_header_set(u32 *arr, int idx, size_t array_size,
97*4882a593Smuzhiyun 				 u8 dw, u8 bit, u8 width, u16 value)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun 	if ((size_t)idx >= array_size)
100*4882a593Smuzhiyun 		return -ERANGE;
101*4882a593Smuzhiyun 	arr[idx++] = sdma_build_ahg_descriptor(value, dw, bit, width);
102*4882a593Smuzhiyun 	return idx;
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun /* Tx request flag bits */
106*4882a593Smuzhiyun #define TXREQ_FLAGS_REQ_ACK   BIT(0)      /* Set the ACK bit in the header */
107*4882a593Smuzhiyun #define TXREQ_FLAGS_REQ_DISABLE_SH BIT(1) /* Disable header suppression */
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun enum pkt_q_sdma_state {
110*4882a593Smuzhiyun 	SDMA_PKT_Q_ACTIVE,
111*4882a593Smuzhiyun 	SDMA_PKT_Q_DEFERRED,
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun #define SDMA_IOWAIT_TIMEOUT 1000 /* in milliseconds */
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun #define SDMA_DBG(req, fmt, ...)				     \
117*4882a593Smuzhiyun 	hfi1_cdbg(SDMA, "[%u:%u:%u:%u] " fmt, (req)->pq->dd->unit, \
118*4882a593Smuzhiyun 		 (req)->pq->ctxt, (req)->pq->subctxt, (req)->info.comp_idx, \
119*4882a593Smuzhiyun 		 ##__VA_ARGS__)
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun struct hfi1_user_sdma_pkt_q {
122*4882a593Smuzhiyun 	u16 ctxt;
123*4882a593Smuzhiyun 	u16 subctxt;
124*4882a593Smuzhiyun 	u16 n_max_reqs;
125*4882a593Smuzhiyun 	atomic_t n_reqs;
126*4882a593Smuzhiyun 	u16 reqidx;
127*4882a593Smuzhiyun 	struct hfi1_devdata *dd;
128*4882a593Smuzhiyun 	struct kmem_cache *txreq_cache;
129*4882a593Smuzhiyun 	struct user_sdma_request *reqs;
130*4882a593Smuzhiyun 	unsigned long *req_in_use;
131*4882a593Smuzhiyun 	struct iowait busy;
132*4882a593Smuzhiyun 	enum pkt_q_sdma_state state;
133*4882a593Smuzhiyun 	wait_queue_head_t wait;
134*4882a593Smuzhiyun 	unsigned long unpinned;
135*4882a593Smuzhiyun 	struct mmu_rb_handler *handler;
136*4882a593Smuzhiyun 	atomic_t n_locked;
137*4882a593Smuzhiyun };
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun struct hfi1_user_sdma_comp_q {
140*4882a593Smuzhiyun 	u16 nentries;
141*4882a593Smuzhiyun 	struct hfi1_sdma_comp_entry *comps;
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun struct sdma_mmu_node {
145*4882a593Smuzhiyun 	struct mmu_rb_node rb;
146*4882a593Smuzhiyun 	struct hfi1_user_sdma_pkt_q *pq;
147*4882a593Smuzhiyun 	atomic_t refcount;
148*4882a593Smuzhiyun 	struct page **pages;
149*4882a593Smuzhiyun 	unsigned int npages;
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun struct user_sdma_iovec {
153*4882a593Smuzhiyun 	struct list_head list;
154*4882a593Smuzhiyun 	struct iovec iov;
155*4882a593Smuzhiyun 	/* number of pages in this vector */
156*4882a593Smuzhiyun 	unsigned int npages;
157*4882a593Smuzhiyun 	/* array of pinned pages for this vector */
158*4882a593Smuzhiyun 	struct page **pages;
159*4882a593Smuzhiyun 	/*
160*4882a593Smuzhiyun 	 * offset into the virtual address space of the vector at
161*4882a593Smuzhiyun 	 * which we last left off.
162*4882a593Smuzhiyun 	 */
163*4882a593Smuzhiyun 	u64 offset;
164*4882a593Smuzhiyun 	struct sdma_mmu_node *node;
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun /* evict operation argument */
168*4882a593Smuzhiyun struct evict_data {
169*4882a593Smuzhiyun 	u32 cleared;	/* count evicted so far */
170*4882a593Smuzhiyun 	u32 target;	/* target count to evict */
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun struct user_sdma_request {
174*4882a593Smuzhiyun 	/* This is the original header from user space */
175*4882a593Smuzhiyun 	struct hfi1_pkt_header hdr;
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	/* Read mostly fields */
178*4882a593Smuzhiyun 	struct hfi1_user_sdma_pkt_q *pq ____cacheline_aligned_in_smp;
179*4882a593Smuzhiyun 	struct hfi1_user_sdma_comp_q *cq;
180*4882a593Smuzhiyun 	/*
181*4882a593Smuzhiyun 	 * Pointer to the SDMA engine for this request.
182*4882a593Smuzhiyun 	 * Since different request could be on different VLs,
183*4882a593Smuzhiyun 	 * each request will need it's own engine pointer.
184*4882a593Smuzhiyun 	 */
185*4882a593Smuzhiyun 	struct sdma_engine *sde;
186*4882a593Smuzhiyun 	struct sdma_req_info info;
187*4882a593Smuzhiyun 	/* TID array values copied from the tid_iov vector */
188*4882a593Smuzhiyun 	u32 *tids;
189*4882a593Smuzhiyun 	/* total length of the data in the request */
190*4882a593Smuzhiyun 	u32 data_len;
191*4882a593Smuzhiyun 	/* number of elements copied to the tids array */
192*4882a593Smuzhiyun 	u16 n_tids;
193*4882a593Smuzhiyun 	/*
194*4882a593Smuzhiyun 	 * We copy the iovs for this request (based on
195*4882a593Smuzhiyun 	 * info.iovcnt). These are only the data vectors
196*4882a593Smuzhiyun 	 */
197*4882a593Smuzhiyun 	u8 data_iovs;
198*4882a593Smuzhiyun 	s8 ahg_idx;
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	/* Writeable fields shared with interrupt */
201*4882a593Smuzhiyun 	u16 seqcomp ____cacheline_aligned_in_smp;
202*4882a593Smuzhiyun 	u16 seqsubmitted;
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	/* Send side fields */
205*4882a593Smuzhiyun 	struct list_head txps ____cacheline_aligned_in_smp;
206*4882a593Smuzhiyun 	u16 seqnum;
207*4882a593Smuzhiyun 	/*
208*4882a593Smuzhiyun 	 * KDETH.OFFSET (TID) field
209*4882a593Smuzhiyun 	 * The offset can cover multiple packets, depending on the
210*4882a593Smuzhiyun 	 * size of the TID entry.
211*4882a593Smuzhiyun 	 */
212*4882a593Smuzhiyun 	u32 tidoffset;
213*4882a593Smuzhiyun 	/*
214*4882a593Smuzhiyun 	 * KDETH.Offset (Eager) field
215*4882a593Smuzhiyun 	 * We need to remember the initial value so the headers
216*4882a593Smuzhiyun 	 * can be updated properly.
217*4882a593Smuzhiyun 	 */
218*4882a593Smuzhiyun 	u32 koffset;
219*4882a593Smuzhiyun 	u32 sent;
220*4882a593Smuzhiyun 	/* TID index copied from the tid_iov vector */
221*4882a593Smuzhiyun 	u16 tididx;
222*4882a593Smuzhiyun 	/* progress index moving along the iovs array */
223*4882a593Smuzhiyun 	u8 iov_idx;
224*4882a593Smuzhiyun 	u8 has_error;
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	struct user_sdma_iovec iovs[MAX_VECTORS_PER_REQ];
227*4882a593Smuzhiyun } ____cacheline_aligned_in_smp;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun /*
230*4882a593Smuzhiyun  * A single txreq could span up to 3 physical pages when the MTU
231*4882a593Smuzhiyun  * is sufficiently large (> 4K). Each of the IOV pointers also
232*4882a593Smuzhiyun  * needs it's own set of flags so the vector has been handled
233*4882a593Smuzhiyun  * independently of each other.
234*4882a593Smuzhiyun  */
235*4882a593Smuzhiyun struct user_sdma_txreq {
236*4882a593Smuzhiyun 	/* Packet header for the txreq */
237*4882a593Smuzhiyun 	struct hfi1_pkt_header hdr;
238*4882a593Smuzhiyun 	struct sdma_txreq txreq;
239*4882a593Smuzhiyun 	struct list_head list;
240*4882a593Smuzhiyun 	struct user_sdma_request *req;
241*4882a593Smuzhiyun 	u16 flags;
242*4882a593Smuzhiyun 	u16 seqnum;
243*4882a593Smuzhiyun };
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun int hfi1_user_sdma_alloc_queues(struct hfi1_ctxtdata *uctxt,
246*4882a593Smuzhiyun 				struct hfi1_filedata *fd);
247*4882a593Smuzhiyun int hfi1_user_sdma_free_queues(struct hfi1_filedata *fd,
248*4882a593Smuzhiyun 			       struct hfi1_ctxtdata *uctxt);
249*4882a593Smuzhiyun int hfi1_user_sdma_process_request(struct hfi1_filedata *fd,
250*4882a593Smuzhiyun 				   struct iovec *iovec, unsigned long dim,
251*4882a593Smuzhiyun 				   unsigned long *count);
252*4882a593Smuzhiyun 
mm_from_sdma_node(struct sdma_mmu_node * node)253*4882a593Smuzhiyun static inline struct mm_struct *mm_from_sdma_node(struct sdma_mmu_node *node)
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun 	return node->rb.handler->mn.mm;
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun 
258*4882a593Smuzhiyun #endif /* _HFI1_USER_SDMA_H */
259