xref: /OK3568_Linux_fs/kernel/drivers/infiniband/hw/hfi1/uc.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright(c) 2015 - 2018 Intel Corporation.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * This file is provided under a dual BSD/GPLv2 license.  When using or
5*4882a593Smuzhiyun  * redistributing this file, you may do so under either license.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * GPL LICENSE SUMMARY
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify
10*4882a593Smuzhiyun  * it under the terms of version 2 of the GNU General Public License as
11*4882a593Smuzhiyun  * published by the Free Software Foundation.
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but
14*4882a593Smuzhiyun  * WITHOUT ANY WARRANTY; without even the implied warranty of
15*4882a593Smuzhiyun  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16*4882a593Smuzhiyun  * General Public License for more details.
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  * BSD LICENSE
19*4882a593Smuzhiyun  *
20*4882a593Smuzhiyun  * Redistribution and use in source and binary forms, with or without
21*4882a593Smuzhiyun  * modification, are permitted provided that the following conditions
22*4882a593Smuzhiyun  * are met:
23*4882a593Smuzhiyun  *
24*4882a593Smuzhiyun  *  - Redistributions of source code must retain the above copyright
25*4882a593Smuzhiyun  *    notice, this list of conditions and the following disclaimer.
26*4882a593Smuzhiyun  *  - Redistributions in binary form must reproduce the above copyright
27*4882a593Smuzhiyun  *    notice, this list of conditions and the following disclaimer in
28*4882a593Smuzhiyun  *    the documentation and/or other materials provided with the
29*4882a593Smuzhiyun  *    distribution.
30*4882a593Smuzhiyun  *  - Neither the name of Intel Corporation nor the names of its
31*4882a593Smuzhiyun  *    contributors may be used to endorse or promote products derived
32*4882a593Smuzhiyun  *    from this software without specific prior written permission.
33*4882a593Smuzhiyun  *
34*4882a593Smuzhiyun  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35*4882a593Smuzhiyun  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36*4882a593Smuzhiyun  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37*4882a593Smuzhiyun  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38*4882a593Smuzhiyun  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39*4882a593Smuzhiyun  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40*4882a593Smuzhiyun  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41*4882a593Smuzhiyun  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42*4882a593Smuzhiyun  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43*4882a593Smuzhiyun  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44*4882a593Smuzhiyun  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45*4882a593Smuzhiyun  *
46*4882a593Smuzhiyun  */
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #include "hfi.h"
49*4882a593Smuzhiyun #include "verbs_txreq.h"
50*4882a593Smuzhiyun #include "qp.h"
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun /* cut down ridiculously long IB macro names */
53*4882a593Smuzhiyun #define OP(x) UC_OP(x)
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun /**
56*4882a593Smuzhiyun  * hfi1_make_uc_req - construct a request packet (SEND, RDMA write)
57*4882a593Smuzhiyun  * @qp: a pointer to the QP
58*4882a593Smuzhiyun  *
59*4882a593Smuzhiyun  * Assume s_lock is held.
60*4882a593Smuzhiyun  *
61*4882a593Smuzhiyun  * Return 1 if constructed; otherwise, return 0.
62*4882a593Smuzhiyun  */
hfi1_make_uc_req(struct rvt_qp * qp,struct hfi1_pkt_state * ps)63*4882a593Smuzhiyun int hfi1_make_uc_req(struct rvt_qp *qp, struct hfi1_pkt_state *ps)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
66*4882a593Smuzhiyun 	struct ib_other_headers *ohdr;
67*4882a593Smuzhiyun 	struct rvt_swqe *wqe;
68*4882a593Smuzhiyun 	u32 hwords;
69*4882a593Smuzhiyun 	u32 bth0 = 0;
70*4882a593Smuzhiyun 	u32 len;
71*4882a593Smuzhiyun 	u32 pmtu = qp->pmtu;
72*4882a593Smuzhiyun 	int middle = 0;
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	ps->s_txreq = get_txreq(ps->dev, qp);
75*4882a593Smuzhiyun 	if (!ps->s_txreq)
76*4882a593Smuzhiyun 		goto bail_no_tx;
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun 	if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_SEND_OK)) {
79*4882a593Smuzhiyun 		if (!(ib_rvt_state_ops[qp->state] & RVT_FLUSH_SEND))
80*4882a593Smuzhiyun 			goto bail;
81*4882a593Smuzhiyun 		/* We are in the error state, flush the work request. */
82*4882a593Smuzhiyun 		if (qp->s_last == READ_ONCE(qp->s_head))
83*4882a593Smuzhiyun 			goto bail;
84*4882a593Smuzhiyun 		/* If DMAs are in progress, we can't flush immediately. */
85*4882a593Smuzhiyun 		if (iowait_sdma_pending(&priv->s_iowait)) {
86*4882a593Smuzhiyun 			qp->s_flags |= RVT_S_WAIT_DMA;
87*4882a593Smuzhiyun 			goto bail;
88*4882a593Smuzhiyun 		}
89*4882a593Smuzhiyun 		clear_ahg(qp);
90*4882a593Smuzhiyun 		wqe = rvt_get_swqe_ptr(qp, qp->s_last);
91*4882a593Smuzhiyun 		rvt_send_complete(qp, wqe, IB_WC_WR_FLUSH_ERR);
92*4882a593Smuzhiyun 		goto done_free_tx;
93*4882a593Smuzhiyun 	}
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	if (priv->hdr_type == HFI1_PKT_TYPE_9B) {
96*4882a593Smuzhiyun 		/* header size in 32-bit words LRH+BTH = (8+12)/4. */
97*4882a593Smuzhiyun 		hwords = 5;
98*4882a593Smuzhiyun 		if (rdma_ah_get_ah_flags(&qp->remote_ah_attr) & IB_AH_GRH)
99*4882a593Smuzhiyun 			ohdr = &ps->s_txreq->phdr.hdr.ibh.u.l.oth;
100*4882a593Smuzhiyun 		else
101*4882a593Smuzhiyun 			ohdr = &ps->s_txreq->phdr.hdr.ibh.u.oth;
102*4882a593Smuzhiyun 	} else {
103*4882a593Smuzhiyun 		/* header size in 32-bit words 16B LRH+BTH = (16+12)/4. */
104*4882a593Smuzhiyun 		hwords = 7;
105*4882a593Smuzhiyun 		if ((rdma_ah_get_ah_flags(&qp->remote_ah_attr) & IB_AH_GRH) &&
106*4882a593Smuzhiyun 		    (hfi1_check_mcast(rdma_ah_get_dlid(&qp->remote_ah_attr))))
107*4882a593Smuzhiyun 			ohdr = &ps->s_txreq->phdr.hdr.opah.u.l.oth;
108*4882a593Smuzhiyun 		else
109*4882a593Smuzhiyun 			ohdr = &ps->s_txreq->phdr.hdr.opah.u.oth;
110*4882a593Smuzhiyun 	}
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	/* Get the next send request. */
113*4882a593Smuzhiyun 	wqe = rvt_get_swqe_ptr(qp, qp->s_cur);
114*4882a593Smuzhiyun 	qp->s_wqe = NULL;
115*4882a593Smuzhiyun 	switch (qp->s_state) {
116*4882a593Smuzhiyun 	default:
117*4882a593Smuzhiyun 		if (!(ib_rvt_state_ops[qp->state] &
118*4882a593Smuzhiyun 		    RVT_PROCESS_NEXT_SEND_OK))
119*4882a593Smuzhiyun 			goto bail;
120*4882a593Smuzhiyun 		/* Check if send work queue is empty. */
121*4882a593Smuzhiyun 		if (qp->s_cur == READ_ONCE(qp->s_head)) {
122*4882a593Smuzhiyun 			clear_ahg(qp);
123*4882a593Smuzhiyun 			goto bail;
124*4882a593Smuzhiyun 		}
125*4882a593Smuzhiyun 		/*
126*4882a593Smuzhiyun 		 * Local operations are processed immediately
127*4882a593Smuzhiyun 		 * after all prior requests have completed.
128*4882a593Smuzhiyun 		 */
129*4882a593Smuzhiyun 		if (wqe->wr.opcode == IB_WR_REG_MR ||
130*4882a593Smuzhiyun 		    wqe->wr.opcode == IB_WR_LOCAL_INV) {
131*4882a593Smuzhiyun 			int local_ops = 0;
132*4882a593Smuzhiyun 			int err = 0;
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 			if (qp->s_last != qp->s_cur)
135*4882a593Smuzhiyun 				goto bail;
136*4882a593Smuzhiyun 			if (++qp->s_cur == qp->s_size)
137*4882a593Smuzhiyun 				qp->s_cur = 0;
138*4882a593Smuzhiyun 			if (!(wqe->wr.send_flags & RVT_SEND_COMPLETION_ONLY)) {
139*4882a593Smuzhiyun 				err = rvt_invalidate_rkey(
140*4882a593Smuzhiyun 					qp, wqe->wr.ex.invalidate_rkey);
141*4882a593Smuzhiyun 				local_ops = 1;
142*4882a593Smuzhiyun 			}
143*4882a593Smuzhiyun 			rvt_send_complete(qp, wqe, err ? IB_WC_LOC_PROT_ERR
144*4882a593Smuzhiyun 							: IB_WC_SUCCESS);
145*4882a593Smuzhiyun 			if (local_ops)
146*4882a593Smuzhiyun 				atomic_dec(&qp->local_ops_pending);
147*4882a593Smuzhiyun 			goto done_free_tx;
148*4882a593Smuzhiyun 		}
149*4882a593Smuzhiyun 		/*
150*4882a593Smuzhiyun 		 * Start a new request.
151*4882a593Smuzhiyun 		 */
152*4882a593Smuzhiyun 		qp->s_psn = wqe->psn;
153*4882a593Smuzhiyun 		qp->s_sge.sge = wqe->sg_list[0];
154*4882a593Smuzhiyun 		qp->s_sge.sg_list = wqe->sg_list + 1;
155*4882a593Smuzhiyun 		qp->s_sge.num_sge = wqe->wr.num_sge;
156*4882a593Smuzhiyun 		qp->s_sge.total_len = wqe->length;
157*4882a593Smuzhiyun 		len = wqe->length;
158*4882a593Smuzhiyun 		qp->s_len = len;
159*4882a593Smuzhiyun 		switch (wqe->wr.opcode) {
160*4882a593Smuzhiyun 		case IB_WR_SEND:
161*4882a593Smuzhiyun 		case IB_WR_SEND_WITH_IMM:
162*4882a593Smuzhiyun 			if (len > pmtu) {
163*4882a593Smuzhiyun 				qp->s_state = OP(SEND_FIRST);
164*4882a593Smuzhiyun 				len = pmtu;
165*4882a593Smuzhiyun 				break;
166*4882a593Smuzhiyun 			}
167*4882a593Smuzhiyun 			if (wqe->wr.opcode == IB_WR_SEND) {
168*4882a593Smuzhiyun 				qp->s_state = OP(SEND_ONLY);
169*4882a593Smuzhiyun 			} else {
170*4882a593Smuzhiyun 				qp->s_state =
171*4882a593Smuzhiyun 					OP(SEND_ONLY_WITH_IMMEDIATE);
172*4882a593Smuzhiyun 				/* Immediate data comes after the BTH */
173*4882a593Smuzhiyun 				ohdr->u.imm_data = wqe->wr.ex.imm_data;
174*4882a593Smuzhiyun 				hwords += 1;
175*4882a593Smuzhiyun 			}
176*4882a593Smuzhiyun 			if (wqe->wr.send_flags & IB_SEND_SOLICITED)
177*4882a593Smuzhiyun 				bth0 |= IB_BTH_SOLICITED;
178*4882a593Smuzhiyun 			qp->s_wqe = wqe;
179*4882a593Smuzhiyun 			if (++qp->s_cur >= qp->s_size)
180*4882a593Smuzhiyun 				qp->s_cur = 0;
181*4882a593Smuzhiyun 			break;
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun 		case IB_WR_RDMA_WRITE:
184*4882a593Smuzhiyun 		case IB_WR_RDMA_WRITE_WITH_IMM:
185*4882a593Smuzhiyun 			ohdr->u.rc.reth.vaddr =
186*4882a593Smuzhiyun 				cpu_to_be64(wqe->rdma_wr.remote_addr);
187*4882a593Smuzhiyun 			ohdr->u.rc.reth.rkey =
188*4882a593Smuzhiyun 				cpu_to_be32(wqe->rdma_wr.rkey);
189*4882a593Smuzhiyun 			ohdr->u.rc.reth.length = cpu_to_be32(len);
190*4882a593Smuzhiyun 			hwords += sizeof(struct ib_reth) / 4;
191*4882a593Smuzhiyun 			if (len > pmtu) {
192*4882a593Smuzhiyun 				qp->s_state = OP(RDMA_WRITE_FIRST);
193*4882a593Smuzhiyun 				len = pmtu;
194*4882a593Smuzhiyun 				break;
195*4882a593Smuzhiyun 			}
196*4882a593Smuzhiyun 			if (wqe->wr.opcode == IB_WR_RDMA_WRITE) {
197*4882a593Smuzhiyun 				qp->s_state = OP(RDMA_WRITE_ONLY);
198*4882a593Smuzhiyun 			} else {
199*4882a593Smuzhiyun 				qp->s_state =
200*4882a593Smuzhiyun 					OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE);
201*4882a593Smuzhiyun 				/* Immediate data comes after the RETH */
202*4882a593Smuzhiyun 				ohdr->u.rc.imm_data = wqe->wr.ex.imm_data;
203*4882a593Smuzhiyun 				hwords += 1;
204*4882a593Smuzhiyun 				if (wqe->wr.send_flags & IB_SEND_SOLICITED)
205*4882a593Smuzhiyun 					bth0 |= IB_BTH_SOLICITED;
206*4882a593Smuzhiyun 			}
207*4882a593Smuzhiyun 			qp->s_wqe = wqe;
208*4882a593Smuzhiyun 			if (++qp->s_cur >= qp->s_size)
209*4882a593Smuzhiyun 				qp->s_cur = 0;
210*4882a593Smuzhiyun 			break;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 		default:
213*4882a593Smuzhiyun 			goto bail;
214*4882a593Smuzhiyun 		}
215*4882a593Smuzhiyun 		break;
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	case OP(SEND_FIRST):
218*4882a593Smuzhiyun 		qp->s_state = OP(SEND_MIDDLE);
219*4882a593Smuzhiyun 		fallthrough;
220*4882a593Smuzhiyun 	case OP(SEND_MIDDLE):
221*4882a593Smuzhiyun 		len = qp->s_len;
222*4882a593Smuzhiyun 		if (len > pmtu) {
223*4882a593Smuzhiyun 			len = pmtu;
224*4882a593Smuzhiyun 			middle = HFI1_CAP_IS_KSET(SDMA_AHG);
225*4882a593Smuzhiyun 			break;
226*4882a593Smuzhiyun 		}
227*4882a593Smuzhiyun 		if (wqe->wr.opcode == IB_WR_SEND) {
228*4882a593Smuzhiyun 			qp->s_state = OP(SEND_LAST);
229*4882a593Smuzhiyun 		} else {
230*4882a593Smuzhiyun 			qp->s_state = OP(SEND_LAST_WITH_IMMEDIATE);
231*4882a593Smuzhiyun 			/* Immediate data comes after the BTH */
232*4882a593Smuzhiyun 			ohdr->u.imm_data = wqe->wr.ex.imm_data;
233*4882a593Smuzhiyun 			hwords += 1;
234*4882a593Smuzhiyun 		}
235*4882a593Smuzhiyun 		if (wqe->wr.send_flags & IB_SEND_SOLICITED)
236*4882a593Smuzhiyun 			bth0 |= IB_BTH_SOLICITED;
237*4882a593Smuzhiyun 		qp->s_wqe = wqe;
238*4882a593Smuzhiyun 		if (++qp->s_cur >= qp->s_size)
239*4882a593Smuzhiyun 			qp->s_cur = 0;
240*4882a593Smuzhiyun 		break;
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun 	case OP(RDMA_WRITE_FIRST):
243*4882a593Smuzhiyun 		qp->s_state = OP(RDMA_WRITE_MIDDLE);
244*4882a593Smuzhiyun 		fallthrough;
245*4882a593Smuzhiyun 	case OP(RDMA_WRITE_MIDDLE):
246*4882a593Smuzhiyun 		len = qp->s_len;
247*4882a593Smuzhiyun 		if (len > pmtu) {
248*4882a593Smuzhiyun 			len = pmtu;
249*4882a593Smuzhiyun 			middle = HFI1_CAP_IS_KSET(SDMA_AHG);
250*4882a593Smuzhiyun 			break;
251*4882a593Smuzhiyun 		}
252*4882a593Smuzhiyun 		if (wqe->wr.opcode == IB_WR_RDMA_WRITE) {
253*4882a593Smuzhiyun 			qp->s_state = OP(RDMA_WRITE_LAST);
254*4882a593Smuzhiyun 		} else {
255*4882a593Smuzhiyun 			qp->s_state =
256*4882a593Smuzhiyun 				OP(RDMA_WRITE_LAST_WITH_IMMEDIATE);
257*4882a593Smuzhiyun 			/* Immediate data comes after the BTH */
258*4882a593Smuzhiyun 			ohdr->u.imm_data = wqe->wr.ex.imm_data;
259*4882a593Smuzhiyun 			hwords += 1;
260*4882a593Smuzhiyun 			if (wqe->wr.send_flags & IB_SEND_SOLICITED)
261*4882a593Smuzhiyun 				bth0 |= IB_BTH_SOLICITED;
262*4882a593Smuzhiyun 		}
263*4882a593Smuzhiyun 		qp->s_wqe = wqe;
264*4882a593Smuzhiyun 		if (++qp->s_cur >= qp->s_size)
265*4882a593Smuzhiyun 			qp->s_cur = 0;
266*4882a593Smuzhiyun 		break;
267*4882a593Smuzhiyun 	}
268*4882a593Smuzhiyun 	qp->s_len -= len;
269*4882a593Smuzhiyun 	ps->s_txreq->hdr_dwords = hwords;
270*4882a593Smuzhiyun 	ps->s_txreq->sde = priv->s_sde;
271*4882a593Smuzhiyun 	ps->s_txreq->ss = &qp->s_sge;
272*4882a593Smuzhiyun 	ps->s_txreq->s_cur_size = len;
273*4882a593Smuzhiyun 	hfi1_make_ruc_header(qp, ohdr, bth0 | (qp->s_state << 24),
274*4882a593Smuzhiyun 			     qp->remote_qpn, mask_psn(qp->s_psn++),
275*4882a593Smuzhiyun 			     middle, ps);
276*4882a593Smuzhiyun 	return 1;
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun done_free_tx:
279*4882a593Smuzhiyun 	hfi1_put_txreq(ps->s_txreq);
280*4882a593Smuzhiyun 	ps->s_txreq = NULL;
281*4882a593Smuzhiyun 	return 1;
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun bail:
284*4882a593Smuzhiyun 	hfi1_put_txreq(ps->s_txreq);
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun bail_no_tx:
287*4882a593Smuzhiyun 	ps->s_txreq = NULL;
288*4882a593Smuzhiyun 	qp->s_flags &= ~RVT_S_BUSY;
289*4882a593Smuzhiyun 	return 0;
290*4882a593Smuzhiyun }
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun /**
293*4882a593Smuzhiyun  * hfi1_uc_rcv - handle an incoming UC packet
294*4882a593Smuzhiyun  * @ibp: the port the packet came in on
295*4882a593Smuzhiyun  * @hdr: the header of the packet
296*4882a593Smuzhiyun  * @rcv_flags: flags relevant to rcv processing
297*4882a593Smuzhiyun  * @data: the packet data
298*4882a593Smuzhiyun  * @tlen: the length of the packet
299*4882a593Smuzhiyun  * @qp: the QP for this packet.
300*4882a593Smuzhiyun  *
301*4882a593Smuzhiyun  * This is called from qp_rcv() to process an incoming UC packet
302*4882a593Smuzhiyun  * for the given QP.
303*4882a593Smuzhiyun  * Called at interrupt level.
304*4882a593Smuzhiyun  */
hfi1_uc_rcv(struct hfi1_packet * packet)305*4882a593Smuzhiyun void hfi1_uc_rcv(struct hfi1_packet *packet)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun 	struct hfi1_ibport *ibp = rcd_to_iport(packet->rcd);
308*4882a593Smuzhiyun 	void *data = packet->payload;
309*4882a593Smuzhiyun 	u32 tlen = packet->tlen;
310*4882a593Smuzhiyun 	struct rvt_qp *qp = packet->qp;
311*4882a593Smuzhiyun 	struct ib_other_headers *ohdr = packet->ohdr;
312*4882a593Smuzhiyun 	u32 opcode = packet->opcode;
313*4882a593Smuzhiyun 	u32 hdrsize = packet->hlen;
314*4882a593Smuzhiyun 	u32 psn;
315*4882a593Smuzhiyun 	u32 pad = packet->pad;
316*4882a593Smuzhiyun 	struct ib_wc wc;
317*4882a593Smuzhiyun 	u32 pmtu = qp->pmtu;
318*4882a593Smuzhiyun 	struct ib_reth *reth;
319*4882a593Smuzhiyun 	int ret;
320*4882a593Smuzhiyun 	u8 extra_bytes = pad + packet->extra_byte + (SIZE_OF_CRC << 2);
321*4882a593Smuzhiyun 
322*4882a593Smuzhiyun 	if (hfi1_ruc_check_hdr(ibp, packet))
323*4882a593Smuzhiyun 		return;
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	process_ecn(qp, packet);
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	psn = ib_bth_get_psn(ohdr);
328*4882a593Smuzhiyun 	/* Compare the PSN verses the expected PSN. */
329*4882a593Smuzhiyun 	if (unlikely(cmp_psn(psn, qp->r_psn) != 0)) {
330*4882a593Smuzhiyun 		/*
331*4882a593Smuzhiyun 		 * Handle a sequence error.
332*4882a593Smuzhiyun 		 * Silently drop any current message.
333*4882a593Smuzhiyun 		 */
334*4882a593Smuzhiyun 		qp->r_psn = psn;
335*4882a593Smuzhiyun inv:
336*4882a593Smuzhiyun 		if (qp->r_state == OP(SEND_FIRST) ||
337*4882a593Smuzhiyun 		    qp->r_state == OP(SEND_MIDDLE)) {
338*4882a593Smuzhiyun 			set_bit(RVT_R_REWIND_SGE, &qp->r_aflags);
339*4882a593Smuzhiyun 			qp->r_sge.num_sge = 0;
340*4882a593Smuzhiyun 		} else {
341*4882a593Smuzhiyun 			rvt_put_ss(&qp->r_sge);
342*4882a593Smuzhiyun 		}
343*4882a593Smuzhiyun 		qp->r_state = OP(SEND_LAST);
344*4882a593Smuzhiyun 		switch (opcode) {
345*4882a593Smuzhiyun 		case OP(SEND_FIRST):
346*4882a593Smuzhiyun 		case OP(SEND_ONLY):
347*4882a593Smuzhiyun 		case OP(SEND_ONLY_WITH_IMMEDIATE):
348*4882a593Smuzhiyun 			goto send_first;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 		case OP(RDMA_WRITE_FIRST):
351*4882a593Smuzhiyun 		case OP(RDMA_WRITE_ONLY):
352*4882a593Smuzhiyun 		case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE):
353*4882a593Smuzhiyun 			goto rdma_first;
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 		default:
356*4882a593Smuzhiyun 			goto drop;
357*4882a593Smuzhiyun 		}
358*4882a593Smuzhiyun 	}
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 	/* Check for opcode sequence errors. */
361*4882a593Smuzhiyun 	switch (qp->r_state) {
362*4882a593Smuzhiyun 	case OP(SEND_FIRST):
363*4882a593Smuzhiyun 	case OP(SEND_MIDDLE):
364*4882a593Smuzhiyun 		if (opcode == OP(SEND_MIDDLE) ||
365*4882a593Smuzhiyun 		    opcode == OP(SEND_LAST) ||
366*4882a593Smuzhiyun 		    opcode == OP(SEND_LAST_WITH_IMMEDIATE))
367*4882a593Smuzhiyun 			break;
368*4882a593Smuzhiyun 		goto inv;
369*4882a593Smuzhiyun 
370*4882a593Smuzhiyun 	case OP(RDMA_WRITE_FIRST):
371*4882a593Smuzhiyun 	case OP(RDMA_WRITE_MIDDLE):
372*4882a593Smuzhiyun 		if (opcode == OP(RDMA_WRITE_MIDDLE) ||
373*4882a593Smuzhiyun 		    opcode == OP(RDMA_WRITE_LAST) ||
374*4882a593Smuzhiyun 		    opcode == OP(RDMA_WRITE_LAST_WITH_IMMEDIATE))
375*4882a593Smuzhiyun 			break;
376*4882a593Smuzhiyun 		goto inv;
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	default:
379*4882a593Smuzhiyun 		if (opcode == OP(SEND_FIRST) ||
380*4882a593Smuzhiyun 		    opcode == OP(SEND_ONLY) ||
381*4882a593Smuzhiyun 		    opcode == OP(SEND_ONLY_WITH_IMMEDIATE) ||
382*4882a593Smuzhiyun 		    opcode == OP(RDMA_WRITE_FIRST) ||
383*4882a593Smuzhiyun 		    opcode == OP(RDMA_WRITE_ONLY) ||
384*4882a593Smuzhiyun 		    opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE))
385*4882a593Smuzhiyun 			break;
386*4882a593Smuzhiyun 		goto inv;
387*4882a593Smuzhiyun 	}
388*4882a593Smuzhiyun 
389*4882a593Smuzhiyun 	if (qp->state == IB_QPS_RTR && !(qp->r_flags & RVT_R_COMM_EST))
390*4882a593Smuzhiyun 		rvt_comm_est(qp);
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun 	/* OK, process the packet. */
393*4882a593Smuzhiyun 	switch (opcode) {
394*4882a593Smuzhiyun 	case OP(SEND_FIRST):
395*4882a593Smuzhiyun 	case OP(SEND_ONLY):
396*4882a593Smuzhiyun 	case OP(SEND_ONLY_WITH_IMMEDIATE):
397*4882a593Smuzhiyun send_first:
398*4882a593Smuzhiyun 		if (test_and_clear_bit(RVT_R_REWIND_SGE, &qp->r_aflags)) {
399*4882a593Smuzhiyun 			qp->r_sge = qp->s_rdma_read_sge;
400*4882a593Smuzhiyun 		} else {
401*4882a593Smuzhiyun 			ret = rvt_get_rwqe(qp, false);
402*4882a593Smuzhiyun 			if (ret < 0)
403*4882a593Smuzhiyun 				goto op_err;
404*4882a593Smuzhiyun 			if (!ret)
405*4882a593Smuzhiyun 				goto drop;
406*4882a593Smuzhiyun 			/*
407*4882a593Smuzhiyun 			 * qp->s_rdma_read_sge will be the owner
408*4882a593Smuzhiyun 			 * of the mr references.
409*4882a593Smuzhiyun 			 */
410*4882a593Smuzhiyun 			qp->s_rdma_read_sge = qp->r_sge;
411*4882a593Smuzhiyun 		}
412*4882a593Smuzhiyun 		qp->r_rcv_len = 0;
413*4882a593Smuzhiyun 		if (opcode == OP(SEND_ONLY))
414*4882a593Smuzhiyun 			goto no_immediate_data;
415*4882a593Smuzhiyun 		else if (opcode == OP(SEND_ONLY_WITH_IMMEDIATE))
416*4882a593Smuzhiyun 			goto send_last_imm;
417*4882a593Smuzhiyun 		fallthrough;
418*4882a593Smuzhiyun 	case OP(SEND_MIDDLE):
419*4882a593Smuzhiyun 		/* Check for invalid length PMTU or posted rwqe len. */
420*4882a593Smuzhiyun 		/*
421*4882a593Smuzhiyun 		 * There will be no padding for 9B packet but 16B packets
422*4882a593Smuzhiyun 		 * will come in with some padding since we always add
423*4882a593Smuzhiyun 		 * CRC and LT bytes which will need to be flit aligned
424*4882a593Smuzhiyun 		 */
425*4882a593Smuzhiyun 		if (unlikely(tlen != (hdrsize + pmtu + extra_bytes)))
426*4882a593Smuzhiyun 			goto rewind;
427*4882a593Smuzhiyun 		qp->r_rcv_len += pmtu;
428*4882a593Smuzhiyun 		if (unlikely(qp->r_rcv_len > qp->r_len))
429*4882a593Smuzhiyun 			goto rewind;
430*4882a593Smuzhiyun 		rvt_copy_sge(qp, &qp->r_sge, data, pmtu, false, false);
431*4882a593Smuzhiyun 		break;
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	case OP(SEND_LAST_WITH_IMMEDIATE):
434*4882a593Smuzhiyun send_last_imm:
435*4882a593Smuzhiyun 		wc.ex.imm_data = ohdr->u.imm_data;
436*4882a593Smuzhiyun 		wc.wc_flags = IB_WC_WITH_IMM;
437*4882a593Smuzhiyun 		goto send_last;
438*4882a593Smuzhiyun 	case OP(SEND_LAST):
439*4882a593Smuzhiyun no_immediate_data:
440*4882a593Smuzhiyun 		wc.ex.imm_data = 0;
441*4882a593Smuzhiyun 		wc.wc_flags = 0;
442*4882a593Smuzhiyun send_last:
443*4882a593Smuzhiyun 		/* Check for invalid length. */
444*4882a593Smuzhiyun 		/* LAST len should be >= 1 */
445*4882a593Smuzhiyun 		if (unlikely(tlen < (hdrsize + extra_bytes)))
446*4882a593Smuzhiyun 			goto rewind;
447*4882a593Smuzhiyun 		/* Don't count the CRC. */
448*4882a593Smuzhiyun 		tlen -= (hdrsize + extra_bytes);
449*4882a593Smuzhiyun 		wc.byte_len = tlen + qp->r_rcv_len;
450*4882a593Smuzhiyun 		if (unlikely(wc.byte_len > qp->r_len))
451*4882a593Smuzhiyun 			goto rewind;
452*4882a593Smuzhiyun 		wc.opcode = IB_WC_RECV;
453*4882a593Smuzhiyun 		rvt_copy_sge(qp, &qp->r_sge, data, tlen, false, false);
454*4882a593Smuzhiyun 		rvt_put_ss(&qp->s_rdma_read_sge);
455*4882a593Smuzhiyun last_imm:
456*4882a593Smuzhiyun 		wc.wr_id = qp->r_wr_id;
457*4882a593Smuzhiyun 		wc.status = IB_WC_SUCCESS;
458*4882a593Smuzhiyun 		wc.qp = &qp->ibqp;
459*4882a593Smuzhiyun 		wc.src_qp = qp->remote_qpn;
460*4882a593Smuzhiyun 		wc.slid = rdma_ah_get_dlid(&qp->remote_ah_attr) & U16_MAX;
461*4882a593Smuzhiyun 		/*
462*4882a593Smuzhiyun 		 * It seems that IB mandates the presence of an SL in a
463*4882a593Smuzhiyun 		 * work completion only for the UD transport (see section
464*4882a593Smuzhiyun 		 * 11.4.2 of IBTA Vol. 1).
465*4882a593Smuzhiyun 		 *
466*4882a593Smuzhiyun 		 * However, the way the SL is chosen below is consistent
467*4882a593Smuzhiyun 		 * with the way that IB/qib works and is trying avoid
468*4882a593Smuzhiyun 		 * introducing incompatibilities.
469*4882a593Smuzhiyun 		 *
470*4882a593Smuzhiyun 		 * See also OPA Vol. 1, section 9.7.6, and table 9-17.
471*4882a593Smuzhiyun 		 */
472*4882a593Smuzhiyun 		wc.sl = rdma_ah_get_sl(&qp->remote_ah_attr);
473*4882a593Smuzhiyun 		/* zero fields that are N/A */
474*4882a593Smuzhiyun 		wc.vendor_err = 0;
475*4882a593Smuzhiyun 		wc.pkey_index = 0;
476*4882a593Smuzhiyun 		wc.dlid_path_bits = 0;
477*4882a593Smuzhiyun 		wc.port_num = 0;
478*4882a593Smuzhiyun 		/* Signal completion event if the solicited bit is set. */
479*4882a593Smuzhiyun 		rvt_recv_cq(qp, &wc, ib_bth_is_solicited(ohdr));
480*4882a593Smuzhiyun 		break;
481*4882a593Smuzhiyun 
482*4882a593Smuzhiyun 	case OP(RDMA_WRITE_FIRST):
483*4882a593Smuzhiyun 	case OP(RDMA_WRITE_ONLY):
484*4882a593Smuzhiyun 	case OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE): /* consume RWQE */
485*4882a593Smuzhiyun rdma_first:
486*4882a593Smuzhiyun 		if (unlikely(!(qp->qp_access_flags &
487*4882a593Smuzhiyun 			       IB_ACCESS_REMOTE_WRITE))) {
488*4882a593Smuzhiyun 			goto drop;
489*4882a593Smuzhiyun 		}
490*4882a593Smuzhiyun 		reth = &ohdr->u.rc.reth;
491*4882a593Smuzhiyun 		qp->r_len = be32_to_cpu(reth->length);
492*4882a593Smuzhiyun 		qp->r_rcv_len = 0;
493*4882a593Smuzhiyun 		qp->r_sge.sg_list = NULL;
494*4882a593Smuzhiyun 		if (qp->r_len != 0) {
495*4882a593Smuzhiyun 			u32 rkey = be32_to_cpu(reth->rkey);
496*4882a593Smuzhiyun 			u64 vaddr = be64_to_cpu(reth->vaddr);
497*4882a593Smuzhiyun 			int ok;
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 			/* Check rkey */
500*4882a593Smuzhiyun 			ok = rvt_rkey_ok(qp, &qp->r_sge.sge, qp->r_len,
501*4882a593Smuzhiyun 					 vaddr, rkey, IB_ACCESS_REMOTE_WRITE);
502*4882a593Smuzhiyun 			if (unlikely(!ok))
503*4882a593Smuzhiyun 				goto drop;
504*4882a593Smuzhiyun 			qp->r_sge.num_sge = 1;
505*4882a593Smuzhiyun 		} else {
506*4882a593Smuzhiyun 			qp->r_sge.num_sge = 0;
507*4882a593Smuzhiyun 			qp->r_sge.sge.mr = NULL;
508*4882a593Smuzhiyun 			qp->r_sge.sge.vaddr = NULL;
509*4882a593Smuzhiyun 			qp->r_sge.sge.length = 0;
510*4882a593Smuzhiyun 			qp->r_sge.sge.sge_length = 0;
511*4882a593Smuzhiyun 		}
512*4882a593Smuzhiyun 		if (opcode == OP(RDMA_WRITE_ONLY)) {
513*4882a593Smuzhiyun 			goto rdma_last;
514*4882a593Smuzhiyun 		} else if (opcode == OP(RDMA_WRITE_ONLY_WITH_IMMEDIATE)) {
515*4882a593Smuzhiyun 			wc.ex.imm_data = ohdr->u.rc.imm_data;
516*4882a593Smuzhiyun 			goto rdma_last_imm;
517*4882a593Smuzhiyun 		}
518*4882a593Smuzhiyun 		fallthrough;
519*4882a593Smuzhiyun 	case OP(RDMA_WRITE_MIDDLE):
520*4882a593Smuzhiyun 		/* Check for invalid length PMTU or posted rwqe len. */
521*4882a593Smuzhiyun 		if (unlikely(tlen != (hdrsize + pmtu + 4)))
522*4882a593Smuzhiyun 			goto drop;
523*4882a593Smuzhiyun 		qp->r_rcv_len += pmtu;
524*4882a593Smuzhiyun 		if (unlikely(qp->r_rcv_len > qp->r_len))
525*4882a593Smuzhiyun 			goto drop;
526*4882a593Smuzhiyun 		rvt_copy_sge(qp, &qp->r_sge, data, pmtu, true, false);
527*4882a593Smuzhiyun 		break;
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	case OP(RDMA_WRITE_LAST_WITH_IMMEDIATE):
530*4882a593Smuzhiyun 		wc.ex.imm_data = ohdr->u.imm_data;
531*4882a593Smuzhiyun rdma_last_imm:
532*4882a593Smuzhiyun 		wc.wc_flags = IB_WC_WITH_IMM;
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 		/* Check for invalid length. */
535*4882a593Smuzhiyun 		/* LAST len should be >= 1 */
536*4882a593Smuzhiyun 		if (unlikely(tlen < (hdrsize + pad + 4)))
537*4882a593Smuzhiyun 			goto drop;
538*4882a593Smuzhiyun 		/* Don't count the CRC. */
539*4882a593Smuzhiyun 		tlen -= (hdrsize + extra_bytes);
540*4882a593Smuzhiyun 		if (unlikely(tlen + qp->r_rcv_len != qp->r_len))
541*4882a593Smuzhiyun 			goto drop;
542*4882a593Smuzhiyun 		if (test_and_clear_bit(RVT_R_REWIND_SGE, &qp->r_aflags)) {
543*4882a593Smuzhiyun 			rvt_put_ss(&qp->s_rdma_read_sge);
544*4882a593Smuzhiyun 		} else {
545*4882a593Smuzhiyun 			ret = rvt_get_rwqe(qp, true);
546*4882a593Smuzhiyun 			if (ret < 0)
547*4882a593Smuzhiyun 				goto op_err;
548*4882a593Smuzhiyun 			if (!ret)
549*4882a593Smuzhiyun 				goto drop;
550*4882a593Smuzhiyun 		}
551*4882a593Smuzhiyun 		wc.byte_len = qp->r_len;
552*4882a593Smuzhiyun 		wc.opcode = IB_WC_RECV_RDMA_WITH_IMM;
553*4882a593Smuzhiyun 		rvt_copy_sge(qp, &qp->r_sge, data, tlen, true, false);
554*4882a593Smuzhiyun 		rvt_put_ss(&qp->r_sge);
555*4882a593Smuzhiyun 		goto last_imm;
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 	case OP(RDMA_WRITE_LAST):
558*4882a593Smuzhiyun rdma_last:
559*4882a593Smuzhiyun 		/* Check for invalid length. */
560*4882a593Smuzhiyun 		/* LAST len should be >= 1 */
561*4882a593Smuzhiyun 		if (unlikely(tlen < (hdrsize + pad + 4)))
562*4882a593Smuzhiyun 			goto drop;
563*4882a593Smuzhiyun 		/* Don't count the CRC. */
564*4882a593Smuzhiyun 		tlen -= (hdrsize + extra_bytes);
565*4882a593Smuzhiyun 		if (unlikely(tlen + qp->r_rcv_len != qp->r_len))
566*4882a593Smuzhiyun 			goto drop;
567*4882a593Smuzhiyun 		rvt_copy_sge(qp, &qp->r_sge, data, tlen, true, false);
568*4882a593Smuzhiyun 		rvt_put_ss(&qp->r_sge);
569*4882a593Smuzhiyun 		break;
570*4882a593Smuzhiyun 
571*4882a593Smuzhiyun 	default:
572*4882a593Smuzhiyun 		/* Drop packet for unknown opcodes. */
573*4882a593Smuzhiyun 		goto drop;
574*4882a593Smuzhiyun 	}
575*4882a593Smuzhiyun 	qp->r_psn++;
576*4882a593Smuzhiyun 	qp->r_state = opcode;
577*4882a593Smuzhiyun 	return;
578*4882a593Smuzhiyun 
579*4882a593Smuzhiyun rewind:
580*4882a593Smuzhiyun 	set_bit(RVT_R_REWIND_SGE, &qp->r_aflags);
581*4882a593Smuzhiyun 	qp->r_sge.num_sge = 0;
582*4882a593Smuzhiyun drop:
583*4882a593Smuzhiyun 	ibp->rvp.n_pkt_drops++;
584*4882a593Smuzhiyun 	return;
585*4882a593Smuzhiyun 
586*4882a593Smuzhiyun op_err:
587*4882a593Smuzhiyun 	rvt_rc_error(qp, IB_WC_LOC_QP_OP_ERR);
588*4882a593Smuzhiyun }
589