1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright(c) 2016 Intel Corporation.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is provided under a dual BSD/GPLv2 license. When using or
5*4882a593Smuzhiyun * redistributing this file, you may do so under either license.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * GPL LICENSE SUMMARY
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
10*4882a593Smuzhiyun * it under the terms of version 2 of the GNU General Public License as
11*4882a593Smuzhiyun * published by the Free Software Foundation.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but
14*4882a593Smuzhiyun * WITHOUT ANY WARRANTY; without even the implied warranty of
15*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16*4882a593Smuzhiyun * General Public License for more details.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * BSD LICENSE
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without
21*4882a593Smuzhiyun * modification, are permitted provided that the following conditions
22*4882a593Smuzhiyun * are met:
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * - Redistributions of source code must retain the above copyright
25*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer.
26*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above copyright
27*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in
28*4882a593Smuzhiyun * the documentation and/or other materials provided with the
29*4882a593Smuzhiyun * distribution.
30*4882a593Smuzhiyun * - Neither the name of Intel Corporation nor the names of its
31*4882a593Smuzhiyun * contributors may be used to endorse or promote products derived
32*4882a593Smuzhiyun * from this software without specific prior written permission.
33*4882a593Smuzhiyun *
34*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35*4882a593Smuzhiyun * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36*4882a593Smuzhiyun * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37*4882a593Smuzhiyun * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38*4882a593Smuzhiyun * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39*4882a593Smuzhiyun * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40*4882a593Smuzhiyun * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41*4882a593Smuzhiyun * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42*4882a593Smuzhiyun * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44*4882a593Smuzhiyun * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45*4882a593Smuzhiyun *
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #ifndef HFI1_SDMA_TXREQ_H
49*4882a593Smuzhiyun #define HFI1_SDMA_TXREQ_H
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* increased for AHG */
52*4882a593Smuzhiyun #define NUM_DESC 6
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * struct sdma_desc - canonical fragment descriptor
56*4882a593Smuzhiyun *
57*4882a593Smuzhiyun * This is the descriptor carried in the tx request
58*4882a593Smuzhiyun * corresponding to each fragment.
59*4882a593Smuzhiyun *
60*4882a593Smuzhiyun */
61*4882a593Smuzhiyun struct sdma_desc {
62*4882a593Smuzhiyun /* private: don't use directly */
63*4882a593Smuzhiyun u64 qw[2];
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /**
67*4882a593Smuzhiyun * struct sdma_txreq - the sdma_txreq structure (one per packet)
68*4882a593Smuzhiyun * @list: for use by user and by queuing for wait
69*4882a593Smuzhiyun *
70*4882a593Smuzhiyun * This is the representation of a packet which consists of some
71*4882a593Smuzhiyun * number of fragments. Storage is provided to within the structure.
72*4882a593Smuzhiyun * for all fragments.
73*4882a593Smuzhiyun *
74*4882a593Smuzhiyun * The storage for the descriptors are automatically extended as needed
75*4882a593Smuzhiyun * when the currently allocation is exceeded.
76*4882a593Smuzhiyun *
77*4882a593Smuzhiyun * The user (Verbs or PSM) may overload this structure with fields
78*4882a593Smuzhiyun * specific to their use by putting this struct first in their struct.
79*4882a593Smuzhiyun * The method of allocation of the overloaded structure is user dependent
80*4882a593Smuzhiyun *
81*4882a593Smuzhiyun * The list is the only public field in the structure.
82*4882a593Smuzhiyun *
83*4882a593Smuzhiyun */
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #define SDMA_TXREQ_S_OK 0
86*4882a593Smuzhiyun #define SDMA_TXREQ_S_SENDERROR 1
87*4882a593Smuzhiyun #define SDMA_TXREQ_S_ABORTED 2
88*4882a593Smuzhiyun #define SDMA_TXREQ_S_SHUTDOWN 3
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun /* flags bits */
91*4882a593Smuzhiyun #define SDMA_TXREQ_F_URGENT 0x0001
92*4882a593Smuzhiyun #define SDMA_TXREQ_F_AHG_COPY 0x0002
93*4882a593Smuzhiyun #define SDMA_TXREQ_F_USE_AHG 0x0004
94*4882a593Smuzhiyun #define SDMA_TXREQ_F_VIP 0x0010
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun struct sdma_txreq;
97*4882a593Smuzhiyun typedef void (*callback_t)(struct sdma_txreq *, int);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun struct iowait;
100*4882a593Smuzhiyun struct sdma_txreq {
101*4882a593Smuzhiyun struct list_head list;
102*4882a593Smuzhiyun /* private: */
103*4882a593Smuzhiyun struct sdma_desc *descp;
104*4882a593Smuzhiyun /* private: */
105*4882a593Smuzhiyun void *coalesce_buf;
106*4882a593Smuzhiyun /* private: */
107*4882a593Smuzhiyun struct iowait *wait;
108*4882a593Smuzhiyun /* private: */
109*4882a593Smuzhiyun callback_t complete;
110*4882a593Smuzhiyun #ifdef CONFIG_HFI1_DEBUG_SDMA_ORDER
111*4882a593Smuzhiyun u64 sn;
112*4882a593Smuzhiyun #endif
113*4882a593Smuzhiyun /* private: - used in coalesce/pad processing */
114*4882a593Smuzhiyun u16 packet_len;
115*4882a593Smuzhiyun /* private: - down-counted to trigger last */
116*4882a593Smuzhiyun u16 tlen;
117*4882a593Smuzhiyun /* private: */
118*4882a593Smuzhiyun u16 num_desc;
119*4882a593Smuzhiyun /* private: */
120*4882a593Smuzhiyun u16 desc_limit;
121*4882a593Smuzhiyun /* private: */
122*4882a593Smuzhiyun u16 next_descq_idx;
123*4882a593Smuzhiyun /* private: */
124*4882a593Smuzhiyun u16 coalesce_idx;
125*4882a593Smuzhiyun /* private: flags */
126*4882a593Smuzhiyun u16 flags;
127*4882a593Smuzhiyun /* private: */
128*4882a593Smuzhiyun struct sdma_desc descs[NUM_DESC];
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun
sdma_txreq_built(struct sdma_txreq * tx)131*4882a593Smuzhiyun static inline int sdma_txreq_built(struct sdma_txreq *tx)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun return tx->num_desc;
134*4882a593Smuzhiyun }
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun #endif /* HFI1_SDMA_TXREQ_H */
137