1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright(c) 2015, 2016 Intel Corporation. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * This file is provided under a dual BSD/GPLv2 license. When using or 5*4882a593Smuzhiyun * redistributing this file, you may do so under either license. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * GPL LICENSE SUMMARY 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 10*4882a593Smuzhiyun * it under the terms of version 2 of the GNU General Public License as 11*4882a593Smuzhiyun * published by the Free Software Foundation. 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but 14*4882a593Smuzhiyun * WITHOUT ANY WARRANTY; without even the implied warranty of 15*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16*4882a593Smuzhiyun * General Public License for more details. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * BSD LICENSE 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without 21*4882a593Smuzhiyun * modification, are permitted provided that the following conditions 22*4882a593Smuzhiyun * are met: 23*4882a593Smuzhiyun * 24*4882a593Smuzhiyun * - Redistributions of source code must retain the above copyright 25*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer. 26*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above copyright 27*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in 28*4882a593Smuzhiyun * the documentation and/or other materials provided with the 29*4882a593Smuzhiyun * distribution. 30*4882a593Smuzhiyun * - Neither the name of Intel Corporation nor the names of its 31*4882a593Smuzhiyun * contributors may be used to endorse or promote products derived 32*4882a593Smuzhiyun * from this software without specific prior written permission. 33*4882a593Smuzhiyun * 34*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 35*4882a593Smuzhiyun * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 36*4882a593Smuzhiyun * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 37*4882a593Smuzhiyun * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 38*4882a593Smuzhiyun * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 39*4882a593Smuzhiyun * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 40*4882a593Smuzhiyun * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 41*4882a593Smuzhiyun * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 42*4882a593Smuzhiyun * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 43*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 44*4882a593Smuzhiyun * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 45*4882a593Smuzhiyun * 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun /* QSFP support common definitions, for hfi driver */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define QSFP_DEV 0xA0 50*4882a593Smuzhiyun #define QSFP_PWR_LAG_MSEC 2000 51*4882a593Smuzhiyun #define QSFP_MODPRS_LAG_MSEC 20 52*4882a593Smuzhiyun /* 128 byte pages, per SFF 8636 rev 2.4 */ 53*4882a593Smuzhiyun #define QSFP_MAX_NUM_PAGES 5 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * Below are masks for QSFP pins. Pins are the same for HFI0 and HFI1. 57*4882a593Smuzhiyun * _N means asserted low 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun #define QSFP_HFI0_I2CCLK BIT(0) 60*4882a593Smuzhiyun #define QSFP_HFI0_I2CDAT BIT(1) 61*4882a593Smuzhiyun #define QSFP_HFI0_RESET_N BIT(2) 62*4882a593Smuzhiyun #define QSFP_HFI0_INT_N BIT(3) 63*4882a593Smuzhiyun #define QSFP_HFI0_MODPRST_N BIT(4) 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* QSFP is paged at 256 bytes */ 66*4882a593Smuzhiyun #define QSFP_PAGESIZE 256 67*4882a593Smuzhiyun /* Reads/writes cannot cross 128 byte boundaries */ 68*4882a593Smuzhiyun #define QSFP_RW_BOUNDARY 128 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* number of bytes in i2c offset for QSFP devices */ 71*4882a593Smuzhiyun #define __QSFP_OFFSET_SIZE 1 /* num address bytes */ 72*4882a593Smuzhiyun #define QSFP_OFFSET_SIZE (__QSFP_OFFSET_SIZE << 8) /* shifted value */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* Defined fields that Intel requires of qualified cables */ 75*4882a593Smuzhiyun /* Byte 0 is Identifier, not checked */ 76*4882a593Smuzhiyun /* Byte 1 is reserved "status MSB" */ 77*4882a593Smuzhiyun #define QSFP_MONITOR_VAL_START 22 78*4882a593Smuzhiyun #define QSFP_MONITOR_VAL_END 81 79*4882a593Smuzhiyun #define QSFP_MONITOR_RANGE (QSFP_MONITOR_VAL_END - QSFP_MONITOR_VAL_START + 1) 80*4882a593Smuzhiyun #define QSFP_TX_CTRL_BYTE_OFFS 86 81*4882a593Smuzhiyun #define QSFP_PWR_CTRL_BYTE_OFFS 93 82*4882a593Smuzhiyun #define QSFP_CDR_CTRL_BYTE_OFFS 98 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define QSFP_PAGE_SELECT_BYTE_OFFS 127 85*4882a593Smuzhiyun /* Byte 128 is Identifier: must be 0x0c for QSFP, or 0x0d for QSFP+ */ 86*4882a593Smuzhiyun #define QSFP_MOD_ID_OFFS 128 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * Byte 129 is "Extended Identifier". 89*4882a593Smuzhiyun * For bits [7:6]: 0:1.5W, 1:2.0W, 2:2.5W, 3:3.5W 90*4882a593Smuzhiyun * For bits [1:0]: 0:Unused, 1:4W, 2:4.5W, 3:5W 91*4882a593Smuzhiyun */ 92*4882a593Smuzhiyun #define QSFP_MOD_PWR_OFFS 129 93*4882a593Smuzhiyun /* Byte 130 is Connector type. Not Intel req'd */ 94*4882a593Smuzhiyun /* Bytes 131..138 are Transceiver types, bit maps for various tech, none IB */ 95*4882a593Smuzhiyun /* Byte 139 is encoding. code 0x01 is 8b10b. Not Intel req'd */ 96*4882a593Smuzhiyun /* byte 140 is nominal bit-rate, in units of 100Mbits/sec */ 97*4882a593Smuzhiyun #define QSFP_NOM_BIT_RATE_100_OFFS 140 98*4882a593Smuzhiyun /* Byte 141 is Extended Rate Select. Not Intel req'd */ 99*4882a593Smuzhiyun /* Bytes 142..145 are lengths for various fiber types. Not Intel req'd */ 100*4882a593Smuzhiyun /* Byte 146 is length for Copper. Units of 1 meter */ 101*4882a593Smuzhiyun #define QSFP_MOD_LEN_OFFS 146 102*4882a593Smuzhiyun /* 103*4882a593Smuzhiyun * Byte 147 is Device technology. D0..3 not Intel req'd 104*4882a593Smuzhiyun * D4..7 select from 15 choices, translated by table: 105*4882a593Smuzhiyun */ 106*4882a593Smuzhiyun #define QSFP_MOD_TECH_OFFS 147 107*4882a593Smuzhiyun extern const char *const hfi1_qsfp_devtech[16]; 108*4882a593Smuzhiyun /* Active Equalization includes fiber, copper full EQ, and copper near Eq */ 109*4882a593Smuzhiyun #define QSFP_IS_ACTIVE(tech) ((0xA2FF >> ((tech) >> 4)) & 1) 110*4882a593Smuzhiyun /* Active Equalization includes fiber, copper full EQ, and copper far Eq */ 111*4882a593Smuzhiyun #define QSFP_IS_ACTIVE_FAR(tech) ((0x32FF >> ((tech) >> 4)) & 1) 112*4882a593Smuzhiyun /* Attenuation should be valid for copper other than full/near Eq */ 113*4882a593Smuzhiyun #define QSFP_HAS_ATTEN(tech) ((0x4D00 >> ((tech) >> 4)) & 1) 114*4882a593Smuzhiyun /* Length is only valid if technology is "copper" */ 115*4882a593Smuzhiyun #define QSFP_IS_CU(tech) ((0xED00 >> ((tech) >> 4)) & 1) 116*4882a593Smuzhiyun #define QSFP_TECH_1490 9 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #define QSFP_OUI(oui) (((unsigned)oui[0] << 16) | ((unsigned)oui[1] << 8) | \ 119*4882a593Smuzhiyun oui[2]) 120*4882a593Smuzhiyun #define QSFP_OUI_AMPHENOL 0x415048 121*4882a593Smuzhiyun #define QSFP_OUI_FINISAR 0x009065 122*4882a593Smuzhiyun #define QSFP_OUI_GORE 0x002177 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* Bytes 148..163 are Vendor Name, Left-justified Blank-filled */ 125*4882a593Smuzhiyun #define QSFP_VEND_OFFS 148 126*4882a593Smuzhiyun #define QSFP_VEND_LEN 16 127*4882a593Smuzhiyun /* Byte 164 is IB Extended transceiver codes Bits D0..3 are SDR,DDR,QDR,EDR */ 128*4882a593Smuzhiyun #define QSFP_IBXCV_OFFS 164 129*4882a593Smuzhiyun /* Bytes 165..167 are Vendor OUI number */ 130*4882a593Smuzhiyun #define QSFP_VOUI_OFFS 165 131*4882a593Smuzhiyun #define QSFP_VOUI_LEN 3 132*4882a593Smuzhiyun /* Bytes 168..183 are Vendor Part Number, string */ 133*4882a593Smuzhiyun #define QSFP_PN_OFFS 168 134*4882a593Smuzhiyun #define QSFP_PN_LEN 16 135*4882a593Smuzhiyun /* Bytes 184,185 are Vendor Rev. Left Justified, Blank-filled */ 136*4882a593Smuzhiyun #define QSFP_REV_OFFS 184 137*4882a593Smuzhiyun #define QSFP_REV_LEN 2 138*4882a593Smuzhiyun /* 139*4882a593Smuzhiyun * Bytes 186,187 are Wavelength, if Optical. Not Intel req'd 140*4882a593Smuzhiyun * If copper, they are attenuation in dB: 141*4882a593Smuzhiyun * Byte 186 is at 2.5Gb/sec (SDR), Byte 187 at 5.0Gb/sec (DDR) 142*4882a593Smuzhiyun */ 143*4882a593Smuzhiyun #define QSFP_ATTEN_OFFS 186 144*4882a593Smuzhiyun #define QSFP_ATTEN_LEN 2 145*4882a593Smuzhiyun /* 146*4882a593Smuzhiyun * Bytes 188,189 are Wavelength tolerance, if optical 147*4882a593Smuzhiyun * If copper, they are attenuation in dB: 148*4882a593Smuzhiyun * Byte 188 is at 12.5 Gb/s, Byte 189 at 25 Gb/s 149*4882a593Smuzhiyun */ 150*4882a593Smuzhiyun #define QSFP_CU_ATTEN_7G_OFFS 188 151*4882a593Smuzhiyun #define QSFP_CU_ATTEN_12G_OFFS 189 152*4882a593Smuzhiyun /* Byte 190 is Max Case Temp. Not Intel req'd */ 153*4882a593Smuzhiyun /* Byte 191 is LSB of sum of bytes 128..190. Not Intel req'd */ 154*4882a593Smuzhiyun #define QSFP_CC_OFFS 191 155*4882a593Smuzhiyun #define QSFP_EQ_INFO_OFFS 193 156*4882a593Smuzhiyun #define QSFP_CDR_INFO_OFFS 194 157*4882a593Smuzhiyun /* Bytes 196..211 are Serial Number, String */ 158*4882a593Smuzhiyun #define QSFP_SN_OFFS 196 159*4882a593Smuzhiyun #define QSFP_SN_LEN 16 160*4882a593Smuzhiyun /* Bytes 212..219 are date-code YYMMDD (MM==1 for Jan) */ 161*4882a593Smuzhiyun #define QSFP_DATE_OFFS 212 162*4882a593Smuzhiyun #define QSFP_DATE_LEN 6 163*4882a593Smuzhiyun /* Bytes 218,219 are optional lot-code, string */ 164*4882a593Smuzhiyun #define QSFP_LOT_OFFS 218 165*4882a593Smuzhiyun #define QSFP_LOT_LEN 2 166*4882a593Smuzhiyun /* Bytes 220, 221 indicate monitoring options, Not Intel req'd */ 167*4882a593Smuzhiyun /* Byte 222 indicates nominal bitrate in units of 250Mbits/sec */ 168*4882a593Smuzhiyun #define QSFP_NOM_BIT_RATE_250_OFFS 222 169*4882a593Smuzhiyun /* Byte 223 is LSB of sum of bytes 192..222 */ 170*4882a593Smuzhiyun #define QSFP_CC_EXT_OFFS 223 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* 173*4882a593Smuzhiyun * Interrupt flag masks 174*4882a593Smuzhiyun */ 175*4882a593Smuzhiyun #define QSFP_DATA_NOT_READY 0x01 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun #define QSFP_HIGH_TEMP_ALARM 0x80 178*4882a593Smuzhiyun #define QSFP_LOW_TEMP_ALARM 0x40 179*4882a593Smuzhiyun #define QSFP_HIGH_TEMP_WARNING 0x20 180*4882a593Smuzhiyun #define QSFP_LOW_TEMP_WARNING 0x10 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun #define QSFP_HIGH_VCC_ALARM 0x80 183*4882a593Smuzhiyun #define QSFP_LOW_VCC_ALARM 0x40 184*4882a593Smuzhiyun #define QSFP_HIGH_VCC_WARNING 0x20 185*4882a593Smuzhiyun #define QSFP_LOW_VCC_WARNING 0x10 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #define QSFP_HIGH_POWER_ALARM 0x88 188*4882a593Smuzhiyun #define QSFP_LOW_POWER_ALARM 0x44 189*4882a593Smuzhiyun #define QSFP_HIGH_POWER_WARNING 0x22 190*4882a593Smuzhiyun #define QSFP_LOW_POWER_WARNING 0x11 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun #define QSFP_HIGH_BIAS_ALARM 0x88 193*4882a593Smuzhiyun #define QSFP_LOW_BIAS_ALARM 0x44 194*4882a593Smuzhiyun #define QSFP_HIGH_BIAS_WARNING 0x22 195*4882a593Smuzhiyun #define QSFP_LOW_BIAS_WARNING 0x11 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun #define QSFP_ATTEN_SDR(attenarray) (attenarray[0]) 198*4882a593Smuzhiyun #define QSFP_ATTEN_DDR(attenarray) (attenarray[1]) 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun /* 201*4882a593Smuzhiyun * struct qsfp_data encapsulates state of QSFP device for one port. 202*4882a593Smuzhiyun * it will be part of port-specific data if a board supports QSFP. 203*4882a593Smuzhiyun * 204*4882a593Smuzhiyun * Since multiple board-types use QSFP, and their pport_data structs 205*4882a593Smuzhiyun * differ (in the chip-specific section), we need a pointer to its head. 206*4882a593Smuzhiyun * 207*4882a593Smuzhiyun * Avoiding premature optimization, we will have one work_struct per port, 208*4882a593Smuzhiyun * and let the qsfp_lock arbitrate access to common resources. 209*4882a593Smuzhiyun * 210*4882a593Smuzhiyun */ 211*4882a593Smuzhiyun struct qsfp_data { 212*4882a593Smuzhiyun /* Helps to find our way */ 213*4882a593Smuzhiyun struct hfi1_pportdata *ppd; 214*4882a593Smuzhiyun struct work_struct qsfp_work; 215*4882a593Smuzhiyun u8 cache[QSFP_MAX_NUM_PAGES * 128]; 216*4882a593Smuzhiyun /* protect qsfp data */ 217*4882a593Smuzhiyun spinlock_t qsfp_lock; 218*4882a593Smuzhiyun u8 check_interrupt_flags; 219*4882a593Smuzhiyun u8 reset_needed; 220*4882a593Smuzhiyun u8 limiting_active; 221*4882a593Smuzhiyun u8 cache_valid; 222*4882a593Smuzhiyun u8 cache_refresh_required; 223*4882a593Smuzhiyun }; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun int refresh_qsfp_cache(struct hfi1_pportdata *ppd, 226*4882a593Smuzhiyun struct qsfp_data *cp); 227*4882a593Smuzhiyun int get_qsfp_power_class(u8 power_byte); 228*4882a593Smuzhiyun int qsfp_mod_present(struct hfi1_pportdata *ppd); 229*4882a593Smuzhiyun int get_cable_info(struct hfi1_devdata *dd, u32 port_num, u32 addr, 230*4882a593Smuzhiyun u32 len, u8 *data); 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun int i2c_write(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, 233*4882a593Smuzhiyun int offset, void *bp, int len); 234*4882a593Smuzhiyun int i2c_read(struct hfi1_pportdata *ppd, u32 target, int i2c_addr, 235*4882a593Smuzhiyun int offset, void *bp, int len); 236*4882a593Smuzhiyun int qsfp_write(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp, 237*4882a593Smuzhiyun int len); 238*4882a593Smuzhiyun int qsfp_read(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp, 239*4882a593Smuzhiyun int len); 240*4882a593Smuzhiyun int one_qsfp_write(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp, 241*4882a593Smuzhiyun int len); 242*4882a593Smuzhiyun int one_qsfp_read(struct hfi1_pportdata *ppd, u32 target, int addr, void *bp, 243*4882a593Smuzhiyun int len); 244*4882a593Smuzhiyun struct hfi1_asic_data; 245*4882a593Smuzhiyun int set_up_i2c(struct hfi1_devdata *dd, struct hfi1_asic_data *ad); 246*4882a593Smuzhiyun void clean_up_i2c(struct hfi1_devdata *dd, struct hfi1_asic_data *ad); 247