xref: /OK3568_Linux_fs/kernel/drivers/infiniband/hw/hfi1/qp.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright(c) 2015 - 2020 Intel Corporation.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * This file is provided under a dual BSD/GPLv2 license.  When using or
5*4882a593Smuzhiyun  * redistributing this file, you may do so under either license.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * GPL LICENSE SUMMARY
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * This program is free software; you can redistribute it and/or modify
10*4882a593Smuzhiyun  * it under the terms of version 2 of the GNU General Public License as
11*4882a593Smuzhiyun  * published by the Free Software Foundation.
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * This program is distributed in the hope that it will be useful, but
14*4882a593Smuzhiyun  * WITHOUT ANY WARRANTY; without even the implied warranty of
15*4882a593Smuzhiyun  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16*4882a593Smuzhiyun  * General Public License for more details.
17*4882a593Smuzhiyun  *
18*4882a593Smuzhiyun  * BSD LICENSE
19*4882a593Smuzhiyun  *
20*4882a593Smuzhiyun  * Redistribution and use in source and binary forms, with or without
21*4882a593Smuzhiyun  * modification, are permitted provided that the following conditions
22*4882a593Smuzhiyun  * are met:
23*4882a593Smuzhiyun  *
24*4882a593Smuzhiyun  *  - Redistributions of source code must retain the above copyright
25*4882a593Smuzhiyun  *    notice, this list of conditions and the following disclaimer.
26*4882a593Smuzhiyun  *  - Redistributions in binary form must reproduce the above copyright
27*4882a593Smuzhiyun  *    notice, this list of conditions and the following disclaimer in
28*4882a593Smuzhiyun  *    the documentation and/or other materials provided with the
29*4882a593Smuzhiyun  *    distribution.
30*4882a593Smuzhiyun  *  - Neither the name of Intel Corporation nor the names of its
31*4882a593Smuzhiyun  *    contributors may be used to endorse or promote products derived
32*4882a593Smuzhiyun  *    from this software without specific prior written permission.
33*4882a593Smuzhiyun  *
34*4882a593Smuzhiyun  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35*4882a593Smuzhiyun  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36*4882a593Smuzhiyun  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37*4882a593Smuzhiyun  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38*4882a593Smuzhiyun  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39*4882a593Smuzhiyun  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40*4882a593Smuzhiyun  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41*4882a593Smuzhiyun  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42*4882a593Smuzhiyun  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43*4882a593Smuzhiyun  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44*4882a593Smuzhiyun  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45*4882a593Smuzhiyun  *
46*4882a593Smuzhiyun  */
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #include <linux/err.h>
49*4882a593Smuzhiyun #include <linux/vmalloc.h>
50*4882a593Smuzhiyun #include <linux/hash.h>
51*4882a593Smuzhiyun #include <linux/module.h>
52*4882a593Smuzhiyun #include <linux/seq_file.h>
53*4882a593Smuzhiyun #include <rdma/rdma_vt.h>
54*4882a593Smuzhiyun #include <rdma/rdmavt_qp.h>
55*4882a593Smuzhiyun #include <rdma/ib_verbs.h>
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #include "hfi.h"
58*4882a593Smuzhiyun #include "qp.h"
59*4882a593Smuzhiyun #include "trace.h"
60*4882a593Smuzhiyun #include "verbs_txreq.h"
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun unsigned int hfi1_qp_table_size = 256;
63*4882a593Smuzhiyun module_param_named(qp_table_size, hfi1_qp_table_size, uint, S_IRUGO);
64*4882a593Smuzhiyun MODULE_PARM_DESC(qp_table_size, "QP table size");
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun static void flush_tx_list(struct rvt_qp *qp);
67*4882a593Smuzhiyun static int iowait_sleep(
68*4882a593Smuzhiyun 	struct sdma_engine *sde,
69*4882a593Smuzhiyun 	struct iowait_work *wait,
70*4882a593Smuzhiyun 	struct sdma_txreq *stx,
71*4882a593Smuzhiyun 	unsigned int seq,
72*4882a593Smuzhiyun 	bool pkts_sent);
73*4882a593Smuzhiyun static void iowait_wakeup(struct iowait *wait, int reason);
74*4882a593Smuzhiyun static void iowait_sdma_drained(struct iowait *wait);
75*4882a593Smuzhiyun static void qp_pio_drain(struct rvt_qp *qp);
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun const struct rvt_operation_params hfi1_post_parms[RVT_OPERATION_MAX] = {
78*4882a593Smuzhiyun [IB_WR_RDMA_WRITE] = {
79*4882a593Smuzhiyun 	.length = sizeof(struct ib_rdma_wr),
80*4882a593Smuzhiyun 	.qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
81*4882a593Smuzhiyun },
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun [IB_WR_RDMA_READ] = {
84*4882a593Smuzhiyun 	.length = sizeof(struct ib_rdma_wr),
85*4882a593Smuzhiyun 	.qpt_support = BIT(IB_QPT_RC),
86*4882a593Smuzhiyun 	.flags = RVT_OPERATION_ATOMIC,
87*4882a593Smuzhiyun },
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun [IB_WR_ATOMIC_CMP_AND_SWP] = {
90*4882a593Smuzhiyun 	.length = sizeof(struct ib_atomic_wr),
91*4882a593Smuzhiyun 	.qpt_support = BIT(IB_QPT_RC),
92*4882a593Smuzhiyun 	.flags = RVT_OPERATION_ATOMIC | RVT_OPERATION_ATOMIC_SGE,
93*4882a593Smuzhiyun },
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun [IB_WR_ATOMIC_FETCH_AND_ADD] = {
96*4882a593Smuzhiyun 	.length = sizeof(struct ib_atomic_wr),
97*4882a593Smuzhiyun 	.qpt_support = BIT(IB_QPT_RC),
98*4882a593Smuzhiyun 	.flags = RVT_OPERATION_ATOMIC | RVT_OPERATION_ATOMIC_SGE,
99*4882a593Smuzhiyun },
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun [IB_WR_RDMA_WRITE_WITH_IMM] = {
102*4882a593Smuzhiyun 	.length = sizeof(struct ib_rdma_wr),
103*4882a593Smuzhiyun 	.qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
104*4882a593Smuzhiyun },
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun [IB_WR_SEND] = {
107*4882a593Smuzhiyun 	.length = sizeof(struct ib_send_wr),
108*4882a593Smuzhiyun 	.qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) |
109*4882a593Smuzhiyun 		       BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
110*4882a593Smuzhiyun },
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun [IB_WR_SEND_WITH_IMM] = {
113*4882a593Smuzhiyun 	.length = sizeof(struct ib_send_wr),
114*4882a593Smuzhiyun 	.qpt_support = BIT(IB_QPT_UD) | BIT(IB_QPT_SMI) | BIT(IB_QPT_GSI) |
115*4882a593Smuzhiyun 		       BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
116*4882a593Smuzhiyun },
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun [IB_WR_REG_MR] = {
119*4882a593Smuzhiyun 	.length = sizeof(struct ib_reg_wr),
120*4882a593Smuzhiyun 	.qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
121*4882a593Smuzhiyun 	.flags = RVT_OPERATION_LOCAL,
122*4882a593Smuzhiyun },
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun [IB_WR_LOCAL_INV] = {
125*4882a593Smuzhiyun 	.length = sizeof(struct ib_send_wr),
126*4882a593Smuzhiyun 	.qpt_support = BIT(IB_QPT_UC) | BIT(IB_QPT_RC),
127*4882a593Smuzhiyun 	.flags = RVT_OPERATION_LOCAL,
128*4882a593Smuzhiyun },
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun [IB_WR_SEND_WITH_INV] = {
131*4882a593Smuzhiyun 	.length = sizeof(struct ib_send_wr),
132*4882a593Smuzhiyun 	.qpt_support = BIT(IB_QPT_RC),
133*4882a593Smuzhiyun },
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun [IB_WR_OPFN] = {
136*4882a593Smuzhiyun 	.length = sizeof(struct ib_atomic_wr),
137*4882a593Smuzhiyun 	.qpt_support = BIT(IB_QPT_RC),
138*4882a593Smuzhiyun 	.flags = RVT_OPERATION_USE_RESERVE,
139*4882a593Smuzhiyun },
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun [IB_WR_TID_RDMA_WRITE] = {
142*4882a593Smuzhiyun 	.length = sizeof(struct ib_rdma_wr),
143*4882a593Smuzhiyun 	.qpt_support = BIT(IB_QPT_RC),
144*4882a593Smuzhiyun 	.flags = RVT_OPERATION_IGN_RNR_CNT,
145*4882a593Smuzhiyun },
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun 
flush_list_head(struct list_head * l)149*4882a593Smuzhiyun static void flush_list_head(struct list_head *l)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	while (!list_empty(l)) {
152*4882a593Smuzhiyun 		struct sdma_txreq *tx;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 		tx = list_first_entry(
155*4882a593Smuzhiyun 			l,
156*4882a593Smuzhiyun 			struct sdma_txreq,
157*4882a593Smuzhiyun 			list);
158*4882a593Smuzhiyun 		list_del_init(&tx->list);
159*4882a593Smuzhiyun 		hfi1_put_txreq(
160*4882a593Smuzhiyun 			container_of(tx, struct verbs_txreq, txreq));
161*4882a593Smuzhiyun 	}
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun 
flush_tx_list(struct rvt_qp * qp)164*4882a593Smuzhiyun static void flush_tx_list(struct rvt_qp *qp)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	flush_list_head(&iowait_get_ib_work(&priv->s_iowait)->tx_head);
169*4882a593Smuzhiyun 	flush_list_head(&iowait_get_tid_work(&priv->s_iowait)->tx_head);
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun 
flush_iowait(struct rvt_qp * qp)172*4882a593Smuzhiyun static void flush_iowait(struct rvt_qp *qp)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
175*4882a593Smuzhiyun 	unsigned long flags;
176*4882a593Smuzhiyun 	seqlock_t *lock = priv->s_iowait.lock;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	if (!lock)
179*4882a593Smuzhiyun 		return;
180*4882a593Smuzhiyun 	write_seqlock_irqsave(lock, flags);
181*4882a593Smuzhiyun 	if (!list_empty(&priv->s_iowait.list)) {
182*4882a593Smuzhiyun 		list_del_init(&priv->s_iowait.list);
183*4882a593Smuzhiyun 		priv->s_iowait.lock = NULL;
184*4882a593Smuzhiyun 		rvt_put_qp(qp);
185*4882a593Smuzhiyun 	}
186*4882a593Smuzhiyun 	write_sequnlock_irqrestore(lock, flags);
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun /**
190*4882a593Smuzhiyun  * This function is what we would push to the core layer if we wanted to be a
191*4882a593Smuzhiyun  * "first class citizen".  Instead we hide this here and rely on Verbs ULPs
192*4882a593Smuzhiyun  * to blindly pass the MTU enum value from the PathRecord to us.
193*4882a593Smuzhiyun  */
verbs_mtu_enum_to_int(struct ib_device * dev,enum ib_mtu mtu)194*4882a593Smuzhiyun static inline int verbs_mtu_enum_to_int(struct ib_device *dev, enum ib_mtu mtu)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun 	/* Constraining 10KB packets to 8KB packets */
197*4882a593Smuzhiyun 	if (mtu == (enum ib_mtu)OPA_MTU_10240)
198*4882a593Smuzhiyun 		mtu = (enum ib_mtu)OPA_MTU_8192;
199*4882a593Smuzhiyun 	return opa_mtu_enum_to_int((enum opa_mtu)mtu);
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun 
hfi1_check_modify_qp(struct rvt_qp * qp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)202*4882a593Smuzhiyun int hfi1_check_modify_qp(struct rvt_qp *qp, struct ib_qp_attr *attr,
203*4882a593Smuzhiyun 			 int attr_mask, struct ib_udata *udata)
204*4882a593Smuzhiyun {
205*4882a593Smuzhiyun 	struct ib_qp *ibqp = &qp->ibqp;
206*4882a593Smuzhiyun 	struct hfi1_ibdev *dev = to_idev(ibqp->device);
207*4882a593Smuzhiyun 	struct hfi1_devdata *dd = dd_from_dev(dev);
208*4882a593Smuzhiyun 	u8 sc;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	if (attr_mask & IB_QP_AV) {
211*4882a593Smuzhiyun 		sc = ah_to_sc(ibqp->device, &attr->ah_attr);
212*4882a593Smuzhiyun 		if (sc == 0xf)
213*4882a593Smuzhiyun 			return -EINVAL;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 		if (!qp_to_sdma_engine(qp, sc) &&
216*4882a593Smuzhiyun 		    dd->flags & HFI1_HAS_SEND_DMA)
217*4882a593Smuzhiyun 			return -EINVAL;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 		if (!qp_to_send_context(qp, sc))
220*4882a593Smuzhiyun 			return -EINVAL;
221*4882a593Smuzhiyun 	}
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	if (attr_mask & IB_QP_ALT_PATH) {
224*4882a593Smuzhiyun 		sc = ah_to_sc(ibqp->device, &attr->alt_ah_attr);
225*4882a593Smuzhiyun 		if (sc == 0xf)
226*4882a593Smuzhiyun 			return -EINVAL;
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun 		if (!qp_to_sdma_engine(qp, sc) &&
229*4882a593Smuzhiyun 		    dd->flags & HFI1_HAS_SEND_DMA)
230*4882a593Smuzhiyun 			return -EINVAL;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 		if (!qp_to_send_context(qp, sc))
233*4882a593Smuzhiyun 			return -EINVAL;
234*4882a593Smuzhiyun 	}
235*4882a593Smuzhiyun 
236*4882a593Smuzhiyun 	return 0;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun /*
240*4882a593Smuzhiyun  * qp_set_16b - Set the hdr_type based on whether the slid or the
241*4882a593Smuzhiyun  * dlid in the connection is extended. Only applicable for RC and UC
242*4882a593Smuzhiyun  * QPs. UD QPs determine this on the fly from the ah in the wqe
243*4882a593Smuzhiyun  */
qp_set_16b(struct rvt_qp * qp)244*4882a593Smuzhiyun static inline void qp_set_16b(struct rvt_qp *qp)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun 	struct hfi1_pportdata *ppd;
247*4882a593Smuzhiyun 	struct hfi1_ibport *ibp;
248*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun 	/* Update ah_attr to account for extended LIDs */
251*4882a593Smuzhiyun 	hfi1_update_ah_attr(qp->ibqp.device, &qp->remote_ah_attr);
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	/* Create 32 bit LIDs */
254*4882a593Smuzhiyun 	hfi1_make_opa_lid(&qp->remote_ah_attr);
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun 	if (!(rdma_ah_get_ah_flags(&qp->remote_ah_attr) & IB_AH_GRH))
257*4882a593Smuzhiyun 		return;
258*4882a593Smuzhiyun 
259*4882a593Smuzhiyun 	ibp = to_iport(qp->ibqp.device, qp->port_num);
260*4882a593Smuzhiyun 	ppd = ppd_from_ibp(ibp);
261*4882a593Smuzhiyun 	priv->hdr_type = hfi1_get_hdr_type(ppd->lid, &qp->remote_ah_attr);
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun 
hfi1_modify_qp(struct rvt_qp * qp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)264*4882a593Smuzhiyun void hfi1_modify_qp(struct rvt_qp *qp, struct ib_qp_attr *attr,
265*4882a593Smuzhiyun 		    int attr_mask, struct ib_udata *udata)
266*4882a593Smuzhiyun {
267*4882a593Smuzhiyun 	struct ib_qp *ibqp = &qp->ibqp;
268*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	if (attr_mask & IB_QP_AV) {
271*4882a593Smuzhiyun 		priv->s_sc = ah_to_sc(ibqp->device, &qp->remote_ah_attr);
272*4882a593Smuzhiyun 		priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc);
273*4882a593Smuzhiyun 		priv->s_sendcontext = qp_to_send_context(qp, priv->s_sc);
274*4882a593Smuzhiyun 		qp_set_16b(qp);
275*4882a593Smuzhiyun 	}
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	if (attr_mask & IB_QP_PATH_MIG_STATE &&
278*4882a593Smuzhiyun 	    attr->path_mig_state == IB_MIG_MIGRATED &&
279*4882a593Smuzhiyun 	    qp->s_mig_state == IB_MIG_ARMED) {
280*4882a593Smuzhiyun 		qp->s_flags |= HFI1_S_AHG_CLEAR;
281*4882a593Smuzhiyun 		priv->s_sc = ah_to_sc(ibqp->device, &qp->remote_ah_attr);
282*4882a593Smuzhiyun 		priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc);
283*4882a593Smuzhiyun 		priv->s_sendcontext = qp_to_send_context(qp, priv->s_sc);
284*4882a593Smuzhiyun 		qp_set_16b(qp);
285*4882a593Smuzhiyun 	}
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	opfn_qp_init(qp, attr, attr_mask);
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun /**
291*4882a593Smuzhiyun  * hfi1_setup_wqe - set up the wqe
292*4882a593Smuzhiyun  * @qp - The qp
293*4882a593Smuzhiyun  * @wqe - The built wqe
294*4882a593Smuzhiyun  * @call_send - Determine if the send should be posted or scheduled.
295*4882a593Smuzhiyun  *
296*4882a593Smuzhiyun  * Perform setup of the wqe.  This is called
297*4882a593Smuzhiyun  * prior to inserting the wqe into the ring but after
298*4882a593Smuzhiyun  * the wqe has been setup by RDMAVT. This function
299*4882a593Smuzhiyun  * allows the driver the opportunity to perform
300*4882a593Smuzhiyun  * validation and additional setup of the wqe.
301*4882a593Smuzhiyun  *
302*4882a593Smuzhiyun  * Returns 0 on success, -EINVAL on failure
303*4882a593Smuzhiyun  *
304*4882a593Smuzhiyun  */
hfi1_setup_wqe(struct rvt_qp * qp,struct rvt_swqe * wqe,bool * call_send)305*4882a593Smuzhiyun int hfi1_setup_wqe(struct rvt_qp *qp, struct rvt_swqe *wqe, bool *call_send)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun 	struct hfi1_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
308*4882a593Smuzhiyun 	struct rvt_ah *ah;
309*4882a593Smuzhiyun 	struct hfi1_pportdata *ppd;
310*4882a593Smuzhiyun 	struct hfi1_devdata *dd;
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun 	switch (qp->ibqp.qp_type) {
313*4882a593Smuzhiyun 	case IB_QPT_RC:
314*4882a593Smuzhiyun 		hfi1_setup_tid_rdma_wqe(qp, wqe);
315*4882a593Smuzhiyun 		fallthrough;
316*4882a593Smuzhiyun 	case IB_QPT_UC:
317*4882a593Smuzhiyun 		if (wqe->length > 0x80000000U)
318*4882a593Smuzhiyun 			return -EINVAL;
319*4882a593Smuzhiyun 		if (wqe->length > qp->pmtu)
320*4882a593Smuzhiyun 			*call_send = false;
321*4882a593Smuzhiyun 		break;
322*4882a593Smuzhiyun 	case IB_QPT_SMI:
323*4882a593Smuzhiyun 		/*
324*4882a593Smuzhiyun 		 * SM packets should exclusively use VL15 and their SL is
325*4882a593Smuzhiyun 		 * ignored (IBTA v1.3, Section 3.5.8.2). Therefore, when ah
326*4882a593Smuzhiyun 		 * is created, SL is 0 in most cases and as a result some
327*4882a593Smuzhiyun 		 * fields (vl and pmtu) in ah may not be set correctly,
328*4882a593Smuzhiyun 		 * depending on the SL2SC and SC2VL tables at the time.
329*4882a593Smuzhiyun 		 */
330*4882a593Smuzhiyun 		ppd = ppd_from_ibp(ibp);
331*4882a593Smuzhiyun 		dd = dd_from_ppd(ppd);
332*4882a593Smuzhiyun 		if (wqe->length > dd->vld[15].mtu)
333*4882a593Smuzhiyun 			return -EINVAL;
334*4882a593Smuzhiyun 		break;
335*4882a593Smuzhiyun 	case IB_QPT_GSI:
336*4882a593Smuzhiyun 	case IB_QPT_UD:
337*4882a593Smuzhiyun 		ah = rvt_get_swqe_ah(wqe);
338*4882a593Smuzhiyun 		if (wqe->length > (1 << ah->log_pmtu))
339*4882a593Smuzhiyun 			return -EINVAL;
340*4882a593Smuzhiyun 		if (ibp->sl_to_sc[rdma_ah_get_sl(&ah->attr)] == 0xf)
341*4882a593Smuzhiyun 			return -EINVAL;
342*4882a593Smuzhiyun 	default:
343*4882a593Smuzhiyun 		break;
344*4882a593Smuzhiyun 	}
345*4882a593Smuzhiyun 
346*4882a593Smuzhiyun 	/*
347*4882a593Smuzhiyun 	 * System latency between send and schedule is large enough that
348*4882a593Smuzhiyun 	 * forcing call_send to true for piothreshold packets is necessary.
349*4882a593Smuzhiyun 	 */
350*4882a593Smuzhiyun 	if (wqe->length <= piothreshold)
351*4882a593Smuzhiyun 		*call_send = true;
352*4882a593Smuzhiyun 	return 0;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun /**
356*4882a593Smuzhiyun  * _hfi1_schedule_send - schedule progress
357*4882a593Smuzhiyun  * @qp: the QP
358*4882a593Smuzhiyun  *
359*4882a593Smuzhiyun  * This schedules qp progress w/o regard to the s_flags.
360*4882a593Smuzhiyun  *
361*4882a593Smuzhiyun  * It is only used in the post send, which doesn't hold
362*4882a593Smuzhiyun  * the s_lock.
363*4882a593Smuzhiyun  */
_hfi1_schedule_send(struct rvt_qp * qp)364*4882a593Smuzhiyun bool _hfi1_schedule_send(struct rvt_qp *qp)
365*4882a593Smuzhiyun {
366*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
367*4882a593Smuzhiyun 	struct hfi1_ibport *ibp =
368*4882a593Smuzhiyun 		to_iport(qp->ibqp.device, qp->port_num);
369*4882a593Smuzhiyun 	struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
370*4882a593Smuzhiyun 	struct hfi1_devdata *dd = ppd->dd;
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	if (dd->flags & HFI1_SHUTDOWN)
373*4882a593Smuzhiyun 		return true;
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 	return iowait_schedule(&priv->s_iowait, ppd->hfi1_wq,
376*4882a593Smuzhiyun 			       priv->s_sde ?
377*4882a593Smuzhiyun 			       priv->s_sde->cpu :
378*4882a593Smuzhiyun 			       cpumask_first(cpumask_of_node(dd->node)));
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun 
qp_pio_drain(struct rvt_qp * qp)381*4882a593Smuzhiyun static void qp_pio_drain(struct rvt_qp *qp)
382*4882a593Smuzhiyun {
383*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	if (!priv->s_sendcontext)
386*4882a593Smuzhiyun 		return;
387*4882a593Smuzhiyun 	while (iowait_pio_pending(&priv->s_iowait)) {
388*4882a593Smuzhiyun 		write_seqlock_irq(&priv->s_sendcontext->waitlock);
389*4882a593Smuzhiyun 		hfi1_sc_wantpiobuf_intr(priv->s_sendcontext, 1);
390*4882a593Smuzhiyun 		write_sequnlock_irq(&priv->s_sendcontext->waitlock);
391*4882a593Smuzhiyun 		iowait_pio_drain(&priv->s_iowait);
392*4882a593Smuzhiyun 		write_seqlock_irq(&priv->s_sendcontext->waitlock);
393*4882a593Smuzhiyun 		hfi1_sc_wantpiobuf_intr(priv->s_sendcontext, 0);
394*4882a593Smuzhiyun 		write_sequnlock_irq(&priv->s_sendcontext->waitlock);
395*4882a593Smuzhiyun 	}
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun /**
399*4882a593Smuzhiyun  * hfi1_schedule_send - schedule progress
400*4882a593Smuzhiyun  * @qp: the QP
401*4882a593Smuzhiyun  *
402*4882a593Smuzhiyun  * This schedules qp progress and caller should hold
403*4882a593Smuzhiyun  * the s_lock.
404*4882a593Smuzhiyun  * @return true if the first leg is scheduled;
405*4882a593Smuzhiyun  * false if the first leg is not scheduled.
406*4882a593Smuzhiyun  */
hfi1_schedule_send(struct rvt_qp * qp)407*4882a593Smuzhiyun bool hfi1_schedule_send(struct rvt_qp *qp)
408*4882a593Smuzhiyun {
409*4882a593Smuzhiyun 	lockdep_assert_held(&qp->s_lock);
410*4882a593Smuzhiyun 	if (hfi1_send_ok(qp)) {
411*4882a593Smuzhiyun 		_hfi1_schedule_send(qp);
412*4882a593Smuzhiyun 		return true;
413*4882a593Smuzhiyun 	}
414*4882a593Smuzhiyun 	if (qp->s_flags & HFI1_S_ANY_WAIT_IO)
415*4882a593Smuzhiyun 		iowait_set_flag(&((struct hfi1_qp_priv *)qp->priv)->s_iowait,
416*4882a593Smuzhiyun 				IOWAIT_PENDING_IB);
417*4882a593Smuzhiyun 	return false;
418*4882a593Smuzhiyun }
419*4882a593Smuzhiyun 
hfi1_qp_schedule(struct rvt_qp * qp)420*4882a593Smuzhiyun static void hfi1_qp_schedule(struct rvt_qp *qp)
421*4882a593Smuzhiyun {
422*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
423*4882a593Smuzhiyun 	bool ret;
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	if (iowait_flag_set(&priv->s_iowait, IOWAIT_PENDING_IB)) {
426*4882a593Smuzhiyun 		ret = hfi1_schedule_send(qp);
427*4882a593Smuzhiyun 		if (ret)
428*4882a593Smuzhiyun 			iowait_clear_flag(&priv->s_iowait, IOWAIT_PENDING_IB);
429*4882a593Smuzhiyun 	}
430*4882a593Smuzhiyun 	if (iowait_flag_set(&priv->s_iowait, IOWAIT_PENDING_TID)) {
431*4882a593Smuzhiyun 		ret = hfi1_schedule_tid_send(qp);
432*4882a593Smuzhiyun 		if (ret)
433*4882a593Smuzhiyun 			iowait_clear_flag(&priv->s_iowait, IOWAIT_PENDING_TID);
434*4882a593Smuzhiyun 	}
435*4882a593Smuzhiyun }
436*4882a593Smuzhiyun 
hfi1_qp_wakeup(struct rvt_qp * qp,u32 flag)437*4882a593Smuzhiyun void hfi1_qp_wakeup(struct rvt_qp *qp, u32 flag)
438*4882a593Smuzhiyun {
439*4882a593Smuzhiyun 	unsigned long flags;
440*4882a593Smuzhiyun 
441*4882a593Smuzhiyun 	spin_lock_irqsave(&qp->s_lock, flags);
442*4882a593Smuzhiyun 	if (qp->s_flags & flag) {
443*4882a593Smuzhiyun 		qp->s_flags &= ~flag;
444*4882a593Smuzhiyun 		trace_hfi1_qpwakeup(qp, flag);
445*4882a593Smuzhiyun 		hfi1_qp_schedule(qp);
446*4882a593Smuzhiyun 	}
447*4882a593Smuzhiyun 	spin_unlock_irqrestore(&qp->s_lock, flags);
448*4882a593Smuzhiyun 	/* Notify hfi1_destroy_qp() if it is waiting. */
449*4882a593Smuzhiyun 	rvt_put_qp(qp);
450*4882a593Smuzhiyun }
451*4882a593Smuzhiyun 
hfi1_qp_unbusy(struct rvt_qp * qp,struct iowait_work * wait)452*4882a593Smuzhiyun void hfi1_qp_unbusy(struct rvt_qp *qp, struct iowait_work *wait)
453*4882a593Smuzhiyun {
454*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	if (iowait_set_work_flag(wait) == IOWAIT_IB_SE) {
457*4882a593Smuzhiyun 		qp->s_flags &= ~RVT_S_BUSY;
458*4882a593Smuzhiyun 		/*
459*4882a593Smuzhiyun 		 * If we are sending a first-leg packet from the second leg,
460*4882a593Smuzhiyun 		 * we need to clear the busy flag from priv->s_flags to
461*4882a593Smuzhiyun 		 * avoid a race condition when the qp wakes up before
462*4882a593Smuzhiyun 		 * the call to hfi1_verbs_send() returns to the second
463*4882a593Smuzhiyun 		 * leg. In that case, the second leg will terminate without
464*4882a593Smuzhiyun 		 * being re-scheduled, resulting in failure to send TID RDMA
465*4882a593Smuzhiyun 		 * WRITE DATA and TID RDMA ACK packets.
466*4882a593Smuzhiyun 		 */
467*4882a593Smuzhiyun 		if (priv->s_flags & HFI1_S_TID_BUSY_SET) {
468*4882a593Smuzhiyun 			priv->s_flags &= ~(HFI1_S_TID_BUSY_SET |
469*4882a593Smuzhiyun 					   RVT_S_BUSY);
470*4882a593Smuzhiyun 			iowait_set_flag(&priv->s_iowait, IOWAIT_PENDING_TID);
471*4882a593Smuzhiyun 		}
472*4882a593Smuzhiyun 	} else {
473*4882a593Smuzhiyun 		priv->s_flags &= ~RVT_S_BUSY;
474*4882a593Smuzhiyun 	}
475*4882a593Smuzhiyun }
476*4882a593Smuzhiyun 
iowait_sleep(struct sdma_engine * sde,struct iowait_work * wait,struct sdma_txreq * stx,uint seq,bool pkts_sent)477*4882a593Smuzhiyun static int iowait_sleep(
478*4882a593Smuzhiyun 	struct sdma_engine *sde,
479*4882a593Smuzhiyun 	struct iowait_work *wait,
480*4882a593Smuzhiyun 	struct sdma_txreq *stx,
481*4882a593Smuzhiyun 	uint seq,
482*4882a593Smuzhiyun 	bool pkts_sent)
483*4882a593Smuzhiyun {
484*4882a593Smuzhiyun 	struct verbs_txreq *tx = container_of(stx, struct verbs_txreq, txreq);
485*4882a593Smuzhiyun 	struct rvt_qp *qp;
486*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv;
487*4882a593Smuzhiyun 	unsigned long flags;
488*4882a593Smuzhiyun 	int ret = 0;
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	qp = tx->qp;
491*4882a593Smuzhiyun 	priv = qp->priv;
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun 	spin_lock_irqsave(&qp->s_lock, flags);
494*4882a593Smuzhiyun 	if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
495*4882a593Smuzhiyun 		/*
496*4882a593Smuzhiyun 		 * If we couldn't queue the DMA request, save the info
497*4882a593Smuzhiyun 		 * and try again later rather than destroying the
498*4882a593Smuzhiyun 		 * buffer and undoing the side effects of the copy.
499*4882a593Smuzhiyun 		 */
500*4882a593Smuzhiyun 		/* Make a common routine? */
501*4882a593Smuzhiyun 		list_add_tail(&stx->list, &wait->tx_head);
502*4882a593Smuzhiyun 		write_seqlock(&sde->waitlock);
503*4882a593Smuzhiyun 		if (sdma_progress(sde, seq, stx))
504*4882a593Smuzhiyun 			goto eagain;
505*4882a593Smuzhiyun 		if (list_empty(&priv->s_iowait.list)) {
506*4882a593Smuzhiyun 			struct hfi1_ibport *ibp =
507*4882a593Smuzhiyun 				to_iport(qp->ibqp.device, qp->port_num);
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 			ibp->rvp.n_dmawait++;
510*4882a593Smuzhiyun 			qp->s_flags |= RVT_S_WAIT_DMA_DESC;
511*4882a593Smuzhiyun 			iowait_get_priority(&priv->s_iowait);
512*4882a593Smuzhiyun 			iowait_queue(pkts_sent, &priv->s_iowait,
513*4882a593Smuzhiyun 				     &sde->dmawait);
514*4882a593Smuzhiyun 			priv->s_iowait.lock = &sde->waitlock;
515*4882a593Smuzhiyun 			trace_hfi1_qpsleep(qp, RVT_S_WAIT_DMA_DESC);
516*4882a593Smuzhiyun 			rvt_get_qp(qp);
517*4882a593Smuzhiyun 		}
518*4882a593Smuzhiyun 		write_sequnlock(&sde->waitlock);
519*4882a593Smuzhiyun 		hfi1_qp_unbusy(qp, wait);
520*4882a593Smuzhiyun 		spin_unlock_irqrestore(&qp->s_lock, flags);
521*4882a593Smuzhiyun 		ret = -EBUSY;
522*4882a593Smuzhiyun 	} else {
523*4882a593Smuzhiyun 		spin_unlock_irqrestore(&qp->s_lock, flags);
524*4882a593Smuzhiyun 		hfi1_put_txreq(tx);
525*4882a593Smuzhiyun 	}
526*4882a593Smuzhiyun 	return ret;
527*4882a593Smuzhiyun eagain:
528*4882a593Smuzhiyun 	write_sequnlock(&sde->waitlock);
529*4882a593Smuzhiyun 	spin_unlock_irqrestore(&qp->s_lock, flags);
530*4882a593Smuzhiyun 	list_del_init(&stx->list);
531*4882a593Smuzhiyun 	return -EAGAIN;
532*4882a593Smuzhiyun }
533*4882a593Smuzhiyun 
iowait_wakeup(struct iowait * wait,int reason)534*4882a593Smuzhiyun static void iowait_wakeup(struct iowait *wait, int reason)
535*4882a593Smuzhiyun {
536*4882a593Smuzhiyun 	struct rvt_qp *qp = iowait_to_qp(wait);
537*4882a593Smuzhiyun 
538*4882a593Smuzhiyun 	WARN_ON(reason != SDMA_AVAIL_REASON);
539*4882a593Smuzhiyun 	hfi1_qp_wakeup(qp, RVT_S_WAIT_DMA_DESC);
540*4882a593Smuzhiyun }
541*4882a593Smuzhiyun 
iowait_sdma_drained(struct iowait * wait)542*4882a593Smuzhiyun static void iowait_sdma_drained(struct iowait *wait)
543*4882a593Smuzhiyun {
544*4882a593Smuzhiyun 	struct rvt_qp *qp = iowait_to_qp(wait);
545*4882a593Smuzhiyun 	unsigned long flags;
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun 	/*
548*4882a593Smuzhiyun 	 * This happens when the send engine notes
549*4882a593Smuzhiyun 	 * a QP in the error state and cannot
550*4882a593Smuzhiyun 	 * do the flush work until that QP's
551*4882a593Smuzhiyun 	 * sdma work has finished.
552*4882a593Smuzhiyun 	 */
553*4882a593Smuzhiyun 	spin_lock_irqsave(&qp->s_lock, flags);
554*4882a593Smuzhiyun 	if (qp->s_flags & RVT_S_WAIT_DMA) {
555*4882a593Smuzhiyun 		qp->s_flags &= ~RVT_S_WAIT_DMA;
556*4882a593Smuzhiyun 		hfi1_schedule_send(qp);
557*4882a593Smuzhiyun 	}
558*4882a593Smuzhiyun 	spin_unlock_irqrestore(&qp->s_lock, flags);
559*4882a593Smuzhiyun }
560*4882a593Smuzhiyun 
hfi1_init_priority(struct iowait * w)561*4882a593Smuzhiyun static void hfi1_init_priority(struct iowait *w)
562*4882a593Smuzhiyun {
563*4882a593Smuzhiyun 	struct rvt_qp *qp = iowait_to_qp(w);
564*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun 	if (qp->s_flags & RVT_S_ACK_PENDING)
567*4882a593Smuzhiyun 		w->priority++;
568*4882a593Smuzhiyun 	if (priv->s_flags & RVT_S_ACK_PENDING)
569*4882a593Smuzhiyun 		w->priority++;
570*4882a593Smuzhiyun }
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun /**
573*4882a593Smuzhiyun  * qp_to_sdma_engine - map a qp to a send engine
574*4882a593Smuzhiyun  * @qp: the QP
575*4882a593Smuzhiyun  * @sc5: the 5 bit sc
576*4882a593Smuzhiyun  *
577*4882a593Smuzhiyun  * Return:
578*4882a593Smuzhiyun  * A send engine for the qp or NULL for SMI type qp.
579*4882a593Smuzhiyun  */
qp_to_sdma_engine(struct rvt_qp * qp,u8 sc5)580*4882a593Smuzhiyun struct sdma_engine *qp_to_sdma_engine(struct rvt_qp *qp, u8 sc5)
581*4882a593Smuzhiyun {
582*4882a593Smuzhiyun 	struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
583*4882a593Smuzhiyun 	struct sdma_engine *sde;
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun 	if (!(dd->flags & HFI1_HAS_SEND_DMA))
586*4882a593Smuzhiyun 		return NULL;
587*4882a593Smuzhiyun 	switch (qp->ibqp.qp_type) {
588*4882a593Smuzhiyun 	case IB_QPT_SMI:
589*4882a593Smuzhiyun 		return NULL;
590*4882a593Smuzhiyun 	default:
591*4882a593Smuzhiyun 		break;
592*4882a593Smuzhiyun 	}
593*4882a593Smuzhiyun 	sde = sdma_select_engine_sc(dd, qp->ibqp.qp_num >> dd->qos_shift, sc5);
594*4882a593Smuzhiyun 	return sde;
595*4882a593Smuzhiyun }
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun /*
598*4882a593Smuzhiyun  * qp_to_send_context - map a qp to a send context
599*4882a593Smuzhiyun  * @qp: the QP
600*4882a593Smuzhiyun  * @sc5: the 5 bit sc
601*4882a593Smuzhiyun  *
602*4882a593Smuzhiyun  * Return:
603*4882a593Smuzhiyun  * A send context for the qp
604*4882a593Smuzhiyun  */
qp_to_send_context(struct rvt_qp * qp,u8 sc5)605*4882a593Smuzhiyun struct send_context *qp_to_send_context(struct rvt_qp *qp, u8 sc5)
606*4882a593Smuzhiyun {
607*4882a593Smuzhiyun 	struct hfi1_devdata *dd = dd_from_ibdev(qp->ibqp.device);
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	switch (qp->ibqp.qp_type) {
610*4882a593Smuzhiyun 	case IB_QPT_SMI:
611*4882a593Smuzhiyun 		/* SMA packets to VL15 */
612*4882a593Smuzhiyun 		return dd->vld[15].sc;
613*4882a593Smuzhiyun 	default:
614*4882a593Smuzhiyun 		break;
615*4882a593Smuzhiyun 	}
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun 	return pio_select_send_context_sc(dd, qp->ibqp.qp_num >> dd->qos_shift,
618*4882a593Smuzhiyun 					  sc5);
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun static const char * const qp_type_str[] = {
622*4882a593Smuzhiyun 	"SMI", "GSI", "RC", "UC", "UD",
623*4882a593Smuzhiyun };
624*4882a593Smuzhiyun 
qp_idle(struct rvt_qp * qp)625*4882a593Smuzhiyun static int qp_idle(struct rvt_qp *qp)
626*4882a593Smuzhiyun {
627*4882a593Smuzhiyun 	return
628*4882a593Smuzhiyun 		qp->s_last == qp->s_acked &&
629*4882a593Smuzhiyun 		qp->s_acked == qp->s_cur &&
630*4882a593Smuzhiyun 		qp->s_cur == qp->s_tail &&
631*4882a593Smuzhiyun 		qp->s_tail == qp->s_head;
632*4882a593Smuzhiyun }
633*4882a593Smuzhiyun 
634*4882a593Smuzhiyun /**
635*4882a593Smuzhiyun  * qp_iter_print - print the qp information to seq_file
636*4882a593Smuzhiyun  * @s: the seq_file to emit the qp information on
637*4882a593Smuzhiyun  * @iter: the iterator for the qp hash list
638*4882a593Smuzhiyun  */
qp_iter_print(struct seq_file * s,struct rvt_qp_iter * iter)639*4882a593Smuzhiyun void qp_iter_print(struct seq_file *s, struct rvt_qp_iter *iter)
640*4882a593Smuzhiyun {
641*4882a593Smuzhiyun 	struct rvt_swqe *wqe;
642*4882a593Smuzhiyun 	struct rvt_qp *qp = iter->qp;
643*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
644*4882a593Smuzhiyun 	struct sdma_engine *sde;
645*4882a593Smuzhiyun 	struct send_context *send_context;
646*4882a593Smuzhiyun 	struct rvt_ack_entry *e = NULL;
647*4882a593Smuzhiyun 	struct rvt_srq *srq = qp->ibqp.srq ?
648*4882a593Smuzhiyun 		ibsrq_to_rvtsrq(qp->ibqp.srq) : NULL;
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun 	sde = qp_to_sdma_engine(qp, priv->s_sc);
651*4882a593Smuzhiyun 	wqe = rvt_get_swqe_ptr(qp, qp->s_last);
652*4882a593Smuzhiyun 	send_context = qp_to_send_context(qp, priv->s_sc);
653*4882a593Smuzhiyun 	if (qp->s_ack_queue)
654*4882a593Smuzhiyun 		e = &qp->s_ack_queue[qp->s_tail_ack_queue];
655*4882a593Smuzhiyun 	seq_printf(s,
656*4882a593Smuzhiyun 		   "N %d %s QP %x R %u %s %u %u f=%x %u %u %u %u %u %u SPSN %x %x %x %x %x RPSN %x S(%u %u %u %u %u %u %u) R(%u %u %u) RQP %x LID %x SL %u MTU %u %u %u %u %u SDE %p,%u SC %p,%u SCQ %u %u PID %d OS %x %x E %x %x %x RNR %d %s %d\n",
657*4882a593Smuzhiyun 		   iter->n,
658*4882a593Smuzhiyun 		   qp_idle(qp) ? "I" : "B",
659*4882a593Smuzhiyun 		   qp->ibqp.qp_num,
660*4882a593Smuzhiyun 		   atomic_read(&qp->refcount),
661*4882a593Smuzhiyun 		   qp_type_str[qp->ibqp.qp_type],
662*4882a593Smuzhiyun 		   qp->state,
663*4882a593Smuzhiyun 		   wqe ? wqe->wr.opcode : 0,
664*4882a593Smuzhiyun 		   qp->s_flags,
665*4882a593Smuzhiyun 		   iowait_sdma_pending(&priv->s_iowait),
666*4882a593Smuzhiyun 		   iowait_pio_pending(&priv->s_iowait),
667*4882a593Smuzhiyun 		   !list_empty(&priv->s_iowait.list),
668*4882a593Smuzhiyun 		   qp->timeout,
669*4882a593Smuzhiyun 		   wqe ? wqe->ssn : 0,
670*4882a593Smuzhiyun 		   qp->s_lsn,
671*4882a593Smuzhiyun 		   qp->s_last_psn,
672*4882a593Smuzhiyun 		   qp->s_psn, qp->s_next_psn,
673*4882a593Smuzhiyun 		   qp->s_sending_psn, qp->s_sending_hpsn,
674*4882a593Smuzhiyun 		   qp->r_psn,
675*4882a593Smuzhiyun 		   qp->s_last, qp->s_acked, qp->s_cur,
676*4882a593Smuzhiyun 		   qp->s_tail, qp->s_head, qp->s_size,
677*4882a593Smuzhiyun 		   qp->s_avail,
678*4882a593Smuzhiyun 		   /* ack_queue ring pointers, size */
679*4882a593Smuzhiyun 		   qp->s_tail_ack_queue, qp->r_head_ack_queue,
680*4882a593Smuzhiyun 		   rvt_max_atomic(&to_idev(qp->ibqp.device)->rdi),
681*4882a593Smuzhiyun 		   /* remote QP info  */
682*4882a593Smuzhiyun 		   qp->remote_qpn,
683*4882a593Smuzhiyun 		   rdma_ah_get_dlid(&qp->remote_ah_attr),
684*4882a593Smuzhiyun 		   rdma_ah_get_sl(&qp->remote_ah_attr),
685*4882a593Smuzhiyun 		   qp->pmtu,
686*4882a593Smuzhiyun 		   qp->s_retry,
687*4882a593Smuzhiyun 		   qp->s_retry_cnt,
688*4882a593Smuzhiyun 		   qp->s_rnr_retry_cnt,
689*4882a593Smuzhiyun 		   qp->s_rnr_retry,
690*4882a593Smuzhiyun 		   sde,
691*4882a593Smuzhiyun 		   sde ? sde->this_idx : 0,
692*4882a593Smuzhiyun 		   send_context,
693*4882a593Smuzhiyun 		   send_context ? send_context->sw_index : 0,
694*4882a593Smuzhiyun 		   ib_cq_head(qp->ibqp.send_cq),
695*4882a593Smuzhiyun 		   ib_cq_tail(qp->ibqp.send_cq),
696*4882a593Smuzhiyun 		   qp->pid,
697*4882a593Smuzhiyun 		   qp->s_state,
698*4882a593Smuzhiyun 		   qp->s_ack_state,
699*4882a593Smuzhiyun 		   /* ack queue information */
700*4882a593Smuzhiyun 		   e ? e->opcode : 0,
701*4882a593Smuzhiyun 		   e ? e->psn : 0,
702*4882a593Smuzhiyun 		   e ? e->lpsn : 0,
703*4882a593Smuzhiyun 		   qp->r_min_rnr_timer,
704*4882a593Smuzhiyun 		   srq ? "SRQ" : "RQ",
705*4882a593Smuzhiyun 		   srq ? srq->rq.size : qp->r_rq.size
706*4882a593Smuzhiyun 		);
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun 
qp_priv_alloc(struct rvt_dev_info * rdi,struct rvt_qp * qp)709*4882a593Smuzhiyun void *qp_priv_alloc(struct rvt_dev_info *rdi, struct rvt_qp *qp)
710*4882a593Smuzhiyun {
711*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv;
712*4882a593Smuzhiyun 
713*4882a593Smuzhiyun 	priv = kzalloc_node(sizeof(*priv), GFP_KERNEL, rdi->dparms.node);
714*4882a593Smuzhiyun 	if (!priv)
715*4882a593Smuzhiyun 		return ERR_PTR(-ENOMEM);
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun 	priv->owner = qp;
718*4882a593Smuzhiyun 
719*4882a593Smuzhiyun 	priv->s_ahg = kzalloc_node(sizeof(*priv->s_ahg), GFP_KERNEL,
720*4882a593Smuzhiyun 				   rdi->dparms.node);
721*4882a593Smuzhiyun 	if (!priv->s_ahg) {
722*4882a593Smuzhiyun 		kfree(priv);
723*4882a593Smuzhiyun 		return ERR_PTR(-ENOMEM);
724*4882a593Smuzhiyun 	}
725*4882a593Smuzhiyun 	iowait_init(
726*4882a593Smuzhiyun 		&priv->s_iowait,
727*4882a593Smuzhiyun 		1,
728*4882a593Smuzhiyun 		_hfi1_do_send,
729*4882a593Smuzhiyun 		_hfi1_do_tid_send,
730*4882a593Smuzhiyun 		iowait_sleep,
731*4882a593Smuzhiyun 		iowait_wakeup,
732*4882a593Smuzhiyun 		iowait_sdma_drained,
733*4882a593Smuzhiyun 		hfi1_init_priority);
734*4882a593Smuzhiyun 	/* Init to a value to start the running average correctly */
735*4882a593Smuzhiyun 	priv->s_running_pkt_size = piothreshold / 2;
736*4882a593Smuzhiyun 	return priv;
737*4882a593Smuzhiyun }
738*4882a593Smuzhiyun 
qp_priv_free(struct rvt_dev_info * rdi,struct rvt_qp * qp)739*4882a593Smuzhiyun void qp_priv_free(struct rvt_dev_info *rdi, struct rvt_qp *qp)
740*4882a593Smuzhiyun {
741*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
742*4882a593Smuzhiyun 
743*4882a593Smuzhiyun 	hfi1_qp_priv_tid_free(rdi, qp);
744*4882a593Smuzhiyun 	kfree(priv->s_ahg);
745*4882a593Smuzhiyun 	kfree(priv);
746*4882a593Smuzhiyun }
747*4882a593Smuzhiyun 
free_all_qps(struct rvt_dev_info * rdi)748*4882a593Smuzhiyun unsigned free_all_qps(struct rvt_dev_info *rdi)
749*4882a593Smuzhiyun {
750*4882a593Smuzhiyun 	struct hfi1_ibdev *verbs_dev = container_of(rdi,
751*4882a593Smuzhiyun 						    struct hfi1_ibdev,
752*4882a593Smuzhiyun 						    rdi);
753*4882a593Smuzhiyun 	struct hfi1_devdata *dd = container_of(verbs_dev,
754*4882a593Smuzhiyun 					       struct hfi1_devdata,
755*4882a593Smuzhiyun 					       verbs_dev);
756*4882a593Smuzhiyun 	int n;
757*4882a593Smuzhiyun 	unsigned qp_inuse = 0;
758*4882a593Smuzhiyun 
759*4882a593Smuzhiyun 	for (n = 0; n < dd->num_pports; n++) {
760*4882a593Smuzhiyun 		struct hfi1_ibport *ibp = &dd->pport[n].ibport_data;
761*4882a593Smuzhiyun 
762*4882a593Smuzhiyun 		rcu_read_lock();
763*4882a593Smuzhiyun 		if (rcu_dereference(ibp->rvp.qp[0]))
764*4882a593Smuzhiyun 			qp_inuse++;
765*4882a593Smuzhiyun 		if (rcu_dereference(ibp->rvp.qp[1]))
766*4882a593Smuzhiyun 			qp_inuse++;
767*4882a593Smuzhiyun 		rcu_read_unlock();
768*4882a593Smuzhiyun 	}
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun 	return qp_inuse;
771*4882a593Smuzhiyun }
772*4882a593Smuzhiyun 
flush_qp_waiters(struct rvt_qp * qp)773*4882a593Smuzhiyun void flush_qp_waiters(struct rvt_qp *qp)
774*4882a593Smuzhiyun {
775*4882a593Smuzhiyun 	lockdep_assert_held(&qp->s_lock);
776*4882a593Smuzhiyun 	flush_iowait(qp);
777*4882a593Smuzhiyun 	hfi1_tid_rdma_flush_wait(qp);
778*4882a593Smuzhiyun }
779*4882a593Smuzhiyun 
stop_send_queue(struct rvt_qp * qp)780*4882a593Smuzhiyun void stop_send_queue(struct rvt_qp *qp)
781*4882a593Smuzhiyun {
782*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
783*4882a593Smuzhiyun 
784*4882a593Smuzhiyun 	iowait_cancel_work(&priv->s_iowait);
785*4882a593Smuzhiyun 	if (cancel_work_sync(&priv->tid_rdma.trigger_work))
786*4882a593Smuzhiyun 		rvt_put_qp(qp);
787*4882a593Smuzhiyun }
788*4882a593Smuzhiyun 
quiesce_qp(struct rvt_qp * qp)789*4882a593Smuzhiyun void quiesce_qp(struct rvt_qp *qp)
790*4882a593Smuzhiyun {
791*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
792*4882a593Smuzhiyun 
793*4882a593Smuzhiyun 	hfi1_del_tid_reap_timer(qp);
794*4882a593Smuzhiyun 	hfi1_del_tid_retry_timer(qp);
795*4882a593Smuzhiyun 	iowait_sdma_drain(&priv->s_iowait);
796*4882a593Smuzhiyun 	qp_pio_drain(qp);
797*4882a593Smuzhiyun 	flush_tx_list(qp);
798*4882a593Smuzhiyun }
799*4882a593Smuzhiyun 
notify_qp_reset(struct rvt_qp * qp)800*4882a593Smuzhiyun void notify_qp_reset(struct rvt_qp *qp)
801*4882a593Smuzhiyun {
802*4882a593Smuzhiyun 	hfi1_qp_kern_exp_rcv_clear_all(qp);
803*4882a593Smuzhiyun 	qp->r_adefered = 0;
804*4882a593Smuzhiyun 	clear_ahg(qp);
805*4882a593Smuzhiyun 
806*4882a593Smuzhiyun 	/* Clear any OPFN state */
807*4882a593Smuzhiyun 	if (qp->ibqp.qp_type == IB_QPT_RC)
808*4882a593Smuzhiyun 		opfn_conn_error(qp);
809*4882a593Smuzhiyun }
810*4882a593Smuzhiyun 
811*4882a593Smuzhiyun /*
812*4882a593Smuzhiyun  * Switch to alternate path.
813*4882a593Smuzhiyun  * The QP s_lock should be held and interrupts disabled.
814*4882a593Smuzhiyun  */
hfi1_migrate_qp(struct rvt_qp * qp)815*4882a593Smuzhiyun void hfi1_migrate_qp(struct rvt_qp *qp)
816*4882a593Smuzhiyun {
817*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
818*4882a593Smuzhiyun 	struct ib_event ev;
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun 	qp->s_mig_state = IB_MIG_MIGRATED;
821*4882a593Smuzhiyun 	qp->remote_ah_attr = qp->alt_ah_attr;
822*4882a593Smuzhiyun 	qp->port_num = rdma_ah_get_port_num(&qp->alt_ah_attr);
823*4882a593Smuzhiyun 	qp->s_pkey_index = qp->s_alt_pkey_index;
824*4882a593Smuzhiyun 	qp->s_flags |= HFI1_S_AHG_CLEAR;
825*4882a593Smuzhiyun 	priv->s_sc = ah_to_sc(qp->ibqp.device, &qp->remote_ah_attr);
826*4882a593Smuzhiyun 	priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc);
827*4882a593Smuzhiyun 	qp_set_16b(qp);
828*4882a593Smuzhiyun 
829*4882a593Smuzhiyun 	ev.device = qp->ibqp.device;
830*4882a593Smuzhiyun 	ev.element.qp = &qp->ibqp;
831*4882a593Smuzhiyun 	ev.event = IB_EVENT_PATH_MIG;
832*4882a593Smuzhiyun 	qp->ibqp.event_handler(&ev, qp->ibqp.qp_context);
833*4882a593Smuzhiyun }
834*4882a593Smuzhiyun 
mtu_to_path_mtu(u32 mtu)835*4882a593Smuzhiyun int mtu_to_path_mtu(u32 mtu)
836*4882a593Smuzhiyun {
837*4882a593Smuzhiyun 	return mtu_to_enum(mtu, OPA_MTU_8192);
838*4882a593Smuzhiyun }
839*4882a593Smuzhiyun 
mtu_from_qp(struct rvt_dev_info * rdi,struct rvt_qp * qp,u32 pmtu)840*4882a593Smuzhiyun u32 mtu_from_qp(struct rvt_dev_info *rdi, struct rvt_qp *qp, u32 pmtu)
841*4882a593Smuzhiyun {
842*4882a593Smuzhiyun 	u32 mtu;
843*4882a593Smuzhiyun 	struct hfi1_ibdev *verbs_dev = container_of(rdi,
844*4882a593Smuzhiyun 						    struct hfi1_ibdev,
845*4882a593Smuzhiyun 						    rdi);
846*4882a593Smuzhiyun 	struct hfi1_devdata *dd = container_of(verbs_dev,
847*4882a593Smuzhiyun 					       struct hfi1_devdata,
848*4882a593Smuzhiyun 					       verbs_dev);
849*4882a593Smuzhiyun 	struct hfi1_ibport *ibp;
850*4882a593Smuzhiyun 	u8 sc, vl;
851*4882a593Smuzhiyun 
852*4882a593Smuzhiyun 	ibp = &dd->pport[qp->port_num - 1].ibport_data;
853*4882a593Smuzhiyun 	sc = ibp->sl_to_sc[rdma_ah_get_sl(&qp->remote_ah_attr)];
854*4882a593Smuzhiyun 	vl = sc_to_vlt(dd, sc);
855*4882a593Smuzhiyun 
856*4882a593Smuzhiyun 	mtu = verbs_mtu_enum_to_int(qp->ibqp.device, pmtu);
857*4882a593Smuzhiyun 	if (vl < PER_VL_SEND_CONTEXTS)
858*4882a593Smuzhiyun 		mtu = min_t(u32, mtu, dd->vld[vl].mtu);
859*4882a593Smuzhiyun 	return mtu;
860*4882a593Smuzhiyun }
861*4882a593Smuzhiyun 
get_pmtu_from_attr(struct rvt_dev_info * rdi,struct rvt_qp * qp,struct ib_qp_attr * attr)862*4882a593Smuzhiyun int get_pmtu_from_attr(struct rvt_dev_info *rdi, struct rvt_qp *qp,
863*4882a593Smuzhiyun 		       struct ib_qp_attr *attr)
864*4882a593Smuzhiyun {
865*4882a593Smuzhiyun 	int mtu, pidx = qp->port_num - 1;
866*4882a593Smuzhiyun 	struct hfi1_ibdev *verbs_dev = container_of(rdi,
867*4882a593Smuzhiyun 						    struct hfi1_ibdev,
868*4882a593Smuzhiyun 						    rdi);
869*4882a593Smuzhiyun 	struct hfi1_devdata *dd = container_of(verbs_dev,
870*4882a593Smuzhiyun 					       struct hfi1_devdata,
871*4882a593Smuzhiyun 					       verbs_dev);
872*4882a593Smuzhiyun 	mtu = verbs_mtu_enum_to_int(qp->ibqp.device, attr->path_mtu);
873*4882a593Smuzhiyun 	if (mtu == -1)
874*4882a593Smuzhiyun 		return -1; /* values less than 0 are error */
875*4882a593Smuzhiyun 
876*4882a593Smuzhiyun 	if (mtu > dd->pport[pidx].ibmtu)
877*4882a593Smuzhiyun 		return mtu_to_enum(dd->pport[pidx].ibmtu, IB_MTU_2048);
878*4882a593Smuzhiyun 	else
879*4882a593Smuzhiyun 		return attr->path_mtu;
880*4882a593Smuzhiyun }
881*4882a593Smuzhiyun 
notify_error_qp(struct rvt_qp * qp)882*4882a593Smuzhiyun void notify_error_qp(struct rvt_qp *qp)
883*4882a593Smuzhiyun {
884*4882a593Smuzhiyun 	struct hfi1_qp_priv *priv = qp->priv;
885*4882a593Smuzhiyun 	seqlock_t *lock = priv->s_iowait.lock;
886*4882a593Smuzhiyun 
887*4882a593Smuzhiyun 	if (lock) {
888*4882a593Smuzhiyun 		write_seqlock(lock);
889*4882a593Smuzhiyun 		if (!list_empty(&priv->s_iowait.list) &&
890*4882a593Smuzhiyun 		    !(qp->s_flags & RVT_S_BUSY) &&
891*4882a593Smuzhiyun 		    !(priv->s_flags & RVT_S_BUSY)) {
892*4882a593Smuzhiyun 			qp->s_flags &= ~HFI1_S_ANY_WAIT_IO;
893*4882a593Smuzhiyun 			iowait_clear_flag(&priv->s_iowait, IOWAIT_PENDING_IB);
894*4882a593Smuzhiyun 			iowait_clear_flag(&priv->s_iowait, IOWAIT_PENDING_TID);
895*4882a593Smuzhiyun 			list_del_init(&priv->s_iowait.list);
896*4882a593Smuzhiyun 			priv->s_iowait.lock = NULL;
897*4882a593Smuzhiyun 			rvt_put_qp(qp);
898*4882a593Smuzhiyun 		}
899*4882a593Smuzhiyun 		write_sequnlock(lock);
900*4882a593Smuzhiyun 	}
901*4882a593Smuzhiyun 
902*4882a593Smuzhiyun 	if (!(qp->s_flags & RVT_S_BUSY) && !(priv->s_flags & RVT_S_BUSY)) {
903*4882a593Smuzhiyun 		qp->s_hdrwords = 0;
904*4882a593Smuzhiyun 		if (qp->s_rdma_mr) {
905*4882a593Smuzhiyun 			rvt_put_mr(qp->s_rdma_mr);
906*4882a593Smuzhiyun 			qp->s_rdma_mr = NULL;
907*4882a593Smuzhiyun 		}
908*4882a593Smuzhiyun 		flush_tx_list(qp);
909*4882a593Smuzhiyun 	}
910*4882a593Smuzhiyun }
911*4882a593Smuzhiyun 
912*4882a593Smuzhiyun /**
913*4882a593Smuzhiyun  * hfi1_qp_iter_cb - callback for iterator
914*4882a593Smuzhiyun  * @qp - the qp
915*4882a593Smuzhiyun  * @v - the sl in low bits of v
916*4882a593Smuzhiyun  *
917*4882a593Smuzhiyun  * This is called from the iterator callback to work
918*4882a593Smuzhiyun  * on an individual qp.
919*4882a593Smuzhiyun  */
hfi1_qp_iter_cb(struct rvt_qp * qp,u64 v)920*4882a593Smuzhiyun static void hfi1_qp_iter_cb(struct rvt_qp *qp, u64 v)
921*4882a593Smuzhiyun {
922*4882a593Smuzhiyun 	int lastwqe;
923*4882a593Smuzhiyun 	struct ib_event ev;
924*4882a593Smuzhiyun 	struct hfi1_ibport *ibp =
925*4882a593Smuzhiyun 		to_iport(qp->ibqp.device, qp->port_num);
926*4882a593Smuzhiyun 	struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
927*4882a593Smuzhiyun 	u8 sl = (u8)v;
928*4882a593Smuzhiyun 
929*4882a593Smuzhiyun 	if (qp->port_num != ppd->port ||
930*4882a593Smuzhiyun 	    (qp->ibqp.qp_type != IB_QPT_UC &&
931*4882a593Smuzhiyun 	     qp->ibqp.qp_type != IB_QPT_RC) ||
932*4882a593Smuzhiyun 	    rdma_ah_get_sl(&qp->remote_ah_attr) != sl ||
933*4882a593Smuzhiyun 	    !(ib_rvt_state_ops[qp->state] & RVT_POST_SEND_OK))
934*4882a593Smuzhiyun 		return;
935*4882a593Smuzhiyun 
936*4882a593Smuzhiyun 	spin_lock_irq(&qp->r_lock);
937*4882a593Smuzhiyun 	spin_lock(&qp->s_hlock);
938*4882a593Smuzhiyun 	spin_lock(&qp->s_lock);
939*4882a593Smuzhiyun 	lastwqe = rvt_error_qp(qp, IB_WC_WR_FLUSH_ERR);
940*4882a593Smuzhiyun 	spin_unlock(&qp->s_lock);
941*4882a593Smuzhiyun 	spin_unlock(&qp->s_hlock);
942*4882a593Smuzhiyun 	spin_unlock_irq(&qp->r_lock);
943*4882a593Smuzhiyun 	if (lastwqe) {
944*4882a593Smuzhiyun 		ev.device = qp->ibqp.device;
945*4882a593Smuzhiyun 		ev.element.qp = &qp->ibqp;
946*4882a593Smuzhiyun 		ev.event = IB_EVENT_QP_LAST_WQE_REACHED;
947*4882a593Smuzhiyun 		qp->ibqp.event_handler(&ev, qp->ibqp.qp_context);
948*4882a593Smuzhiyun 	}
949*4882a593Smuzhiyun }
950*4882a593Smuzhiyun 
951*4882a593Smuzhiyun /**
952*4882a593Smuzhiyun  * hfi1_error_port_qps - put a port's RC/UC qps into error state
953*4882a593Smuzhiyun  * @ibp: the ibport.
954*4882a593Smuzhiyun  * @sl: the service level.
955*4882a593Smuzhiyun  *
956*4882a593Smuzhiyun  * This function places all RC/UC qps with a given service level into error
957*4882a593Smuzhiyun  * state. It is generally called to force upper lay apps to abandon stale qps
958*4882a593Smuzhiyun  * after an sl->sc mapping change.
959*4882a593Smuzhiyun  */
hfi1_error_port_qps(struct hfi1_ibport * ibp,u8 sl)960*4882a593Smuzhiyun void hfi1_error_port_qps(struct hfi1_ibport *ibp, u8 sl)
961*4882a593Smuzhiyun {
962*4882a593Smuzhiyun 	struct hfi1_pportdata *ppd = ppd_from_ibp(ibp);
963*4882a593Smuzhiyun 	struct hfi1_ibdev *dev = &ppd->dd->verbs_dev;
964*4882a593Smuzhiyun 
965*4882a593Smuzhiyun 	rvt_qp_iter(&dev->rdi, sl, hfi1_qp_iter_cb);
966*4882a593Smuzhiyun }
967