1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright(c) 2015 - 2017 Intel Corporation.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is provided under a dual BSD/GPLv2 license. When using or
5*4882a593Smuzhiyun * redistributing this file, you may do so under either license.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * GPL LICENSE SUMMARY
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
10*4882a593Smuzhiyun * it under the terms of version 2 of the GNU General Public License as
11*4882a593Smuzhiyun * published by the Free Software Foundation.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but
14*4882a593Smuzhiyun * WITHOUT ANY WARRANTY; without even the implied warranty of
15*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16*4882a593Smuzhiyun * General Public License for more details.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * BSD LICENSE
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without
21*4882a593Smuzhiyun * modification, are permitted provided that the following conditions
22*4882a593Smuzhiyun * are met:
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * - Redistributions of source code must retain the above copyright
25*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer.
26*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above copyright
27*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in
28*4882a593Smuzhiyun * the documentation and/or other materials provided with the
29*4882a593Smuzhiyun * distribution.
30*4882a593Smuzhiyun * - Neither the name of Intel Corporation nor the names of its
31*4882a593Smuzhiyun * contributors may be used to endorse or promote products derived
32*4882a593Smuzhiyun * from this software without specific prior written permission.
33*4882a593Smuzhiyun *
34*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35*4882a593Smuzhiyun * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36*4882a593Smuzhiyun * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37*4882a593Smuzhiyun * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38*4882a593Smuzhiyun * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39*4882a593Smuzhiyun * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40*4882a593Smuzhiyun * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41*4882a593Smuzhiyun * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42*4882a593Smuzhiyun * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44*4882a593Smuzhiyun * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45*4882a593Smuzhiyun *
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun #ifndef _HFI1_MAD_H
48*4882a593Smuzhiyun #define _HFI1_MAD_H
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #include <rdma/ib_pma.h>
51*4882a593Smuzhiyun #include <rdma/opa_smi.h>
52*4882a593Smuzhiyun #include <rdma/opa_port_info.h>
53*4882a593Smuzhiyun #include "opa_compat.h"
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /*
56*4882a593Smuzhiyun * OPA Traps
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun #define OPA_TRAP_GID_NOW_IN_SERVICE cpu_to_be16(64)
59*4882a593Smuzhiyun #define OPA_TRAP_GID_OUT_OF_SERVICE cpu_to_be16(65)
60*4882a593Smuzhiyun #define OPA_TRAP_ADD_MULTICAST_GROUP cpu_to_be16(66)
61*4882a593Smuzhiyun #define OPA_TRAL_DEL_MULTICAST_GROUP cpu_to_be16(67)
62*4882a593Smuzhiyun #define OPA_TRAP_UNPATH cpu_to_be16(68)
63*4882a593Smuzhiyun #define OPA_TRAP_REPATH cpu_to_be16(69)
64*4882a593Smuzhiyun #define OPA_TRAP_PORT_CHANGE_STATE cpu_to_be16(128)
65*4882a593Smuzhiyun #define OPA_TRAP_LINK_INTEGRITY cpu_to_be16(129)
66*4882a593Smuzhiyun #define OPA_TRAP_EXCESSIVE_BUFFER_OVERRUN cpu_to_be16(130)
67*4882a593Smuzhiyun #define OPA_TRAP_FLOW_WATCHDOG cpu_to_be16(131)
68*4882a593Smuzhiyun #define OPA_TRAP_CHANGE_CAPABILITY cpu_to_be16(144)
69*4882a593Smuzhiyun #define OPA_TRAP_CHANGE_SYSGUID cpu_to_be16(145)
70*4882a593Smuzhiyun #define OPA_TRAP_BAD_M_KEY cpu_to_be16(256)
71*4882a593Smuzhiyun #define OPA_TRAP_BAD_P_KEY cpu_to_be16(257)
72*4882a593Smuzhiyun #define OPA_TRAP_BAD_Q_KEY cpu_to_be16(258)
73*4882a593Smuzhiyun #define OPA_TRAP_SWITCH_BAD_PKEY cpu_to_be16(259)
74*4882a593Smuzhiyun #define OPA_SMA_TRAP_DATA_LINK_WIDTH cpu_to_be16(2048)
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /*
77*4882a593Smuzhiyun * Generic trap/notice other local changes flags (trap 144).
78*4882a593Smuzhiyun */
79*4882a593Smuzhiyun #define OPA_NOTICE_TRAP_LWDE_CHG 0x08 /* Link Width Downgrade Enable
80*4882a593Smuzhiyun * changed
81*4882a593Smuzhiyun */
82*4882a593Smuzhiyun #define OPA_NOTICE_TRAP_LSE_CHG 0x04 /* Link Speed Enable changed */
83*4882a593Smuzhiyun #define OPA_NOTICE_TRAP_LWE_CHG 0x02 /* Link Width Enable changed */
84*4882a593Smuzhiyun #define OPA_NOTICE_TRAP_NODE_DESC_CHG 0x01
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun struct opa_mad_notice_attr {
87*4882a593Smuzhiyun u8 generic_type;
88*4882a593Smuzhiyun u8 prod_type_msb;
89*4882a593Smuzhiyun __be16 prod_type_lsb;
90*4882a593Smuzhiyun __be16 trap_num;
91*4882a593Smuzhiyun __be16 toggle_count;
92*4882a593Smuzhiyun __be32 issuer_lid;
93*4882a593Smuzhiyun __be32 reserved1;
94*4882a593Smuzhiyun union ib_gid issuer_gid;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun union {
97*4882a593Smuzhiyun struct {
98*4882a593Smuzhiyun u8 details[64];
99*4882a593Smuzhiyun } raw_data;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun struct {
102*4882a593Smuzhiyun union ib_gid gid;
103*4882a593Smuzhiyun } __packed ntc_64_65_66_67;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun struct {
106*4882a593Smuzhiyun __be32 lid;
107*4882a593Smuzhiyun } __packed ntc_128;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun struct {
110*4882a593Smuzhiyun __be32 lid; /* where violation happened */
111*4882a593Smuzhiyun u8 port_num; /* where violation happened */
112*4882a593Smuzhiyun } __packed ntc_129_130_131;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun struct {
115*4882a593Smuzhiyun __be32 lid; /* LID where change occurred */
116*4882a593Smuzhiyun __be32 new_cap_mask; /* new capability mask */
117*4882a593Smuzhiyun __be16 reserved2;
118*4882a593Smuzhiyun __be16 cap_mask3;
119*4882a593Smuzhiyun __be16 change_flags; /* low 4 bits only */
120*4882a593Smuzhiyun } __packed ntc_144;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun struct {
123*4882a593Smuzhiyun __be64 new_sys_guid;
124*4882a593Smuzhiyun __be32 lid; /* lid where sys guid changed */
125*4882a593Smuzhiyun } __packed ntc_145;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun struct {
128*4882a593Smuzhiyun __be32 lid;
129*4882a593Smuzhiyun __be32 dr_slid;
130*4882a593Smuzhiyun u8 method;
131*4882a593Smuzhiyun u8 dr_trunc_hop;
132*4882a593Smuzhiyun __be16 attr_id;
133*4882a593Smuzhiyun __be32 attr_mod;
134*4882a593Smuzhiyun __be64 mkey;
135*4882a593Smuzhiyun u8 dr_rtn_path[30];
136*4882a593Smuzhiyun } __packed ntc_256;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun struct {
139*4882a593Smuzhiyun __be32 lid1;
140*4882a593Smuzhiyun __be32 lid2;
141*4882a593Smuzhiyun __be32 key;
142*4882a593Smuzhiyun u8 sl; /* SL: high 5 bits */
143*4882a593Smuzhiyun u8 reserved3[3];
144*4882a593Smuzhiyun union ib_gid gid1;
145*4882a593Smuzhiyun union ib_gid gid2;
146*4882a593Smuzhiyun __be32 qp1; /* high 8 bits reserved */
147*4882a593Smuzhiyun __be32 qp2; /* high 8 bits reserved */
148*4882a593Smuzhiyun } __packed ntc_257_258;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun struct {
151*4882a593Smuzhiyun __be16 flags; /* low 8 bits reserved */
152*4882a593Smuzhiyun __be16 pkey;
153*4882a593Smuzhiyun __be32 lid1;
154*4882a593Smuzhiyun __be32 lid2;
155*4882a593Smuzhiyun u8 sl; /* SL: high 5 bits */
156*4882a593Smuzhiyun u8 reserved4[3];
157*4882a593Smuzhiyun union ib_gid gid1;
158*4882a593Smuzhiyun union ib_gid gid2;
159*4882a593Smuzhiyun __be32 qp1; /* high 8 bits reserved */
160*4882a593Smuzhiyun __be32 qp2; /* high 8 bits reserved */
161*4882a593Smuzhiyun } __packed ntc_259;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun struct {
164*4882a593Smuzhiyun __be32 lid;
165*4882a593Smuzhiyun } __packed ntc_2048;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun u8 class_data[];
169*4882a593Smuzhiyun };
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun #define IB_VLARB_LOWPRI_0_31 1
172*4882a593Smuzhiyun #define IB_VLARB_LOWPRI_32_63 2
173*4882a593Smuzhiyun #define IB_VLARB_HIGHPRI_0_31 3
174*4882a593Smuzhiyun #define IB_VLARB_HIGHPRI_32_63 4
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun #define OPA_MAX_PREEMPT_CAP 32
177*4882a593Smuzhiyun #define OPA_VLARB_LOW_ELEMENTS 0
178*4882a593Smuzhiyun #define OPA_VLARB_HIGH_ELEMENTS 1
179*4882a593Smuzhiyun #define OPA_VLARB_PREEMPT_ELEMENTS 2
180*4882a593Smuzhiyun #define OPA_VLARB_PREEMPT_MATRIX 3
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun #define IB_PMA_PORT_COUNTERS_CONG cpu_to_be16(0xFF00)
183*4882a593Smuzhiyun #define LINK_SPEED_25G 1
184*4882a593Smuzhiyun #define LINK_SPEED_12_5G 2
185*4882a593Smuzhiyun #define LINK_WIDTH_DEFAULT 4
186*4882a593Smuzhiyun #define DECIMAL_FACTORING 1000
187*4882a593Smuzhiyun /*
188*4882a593Smuzhiyun * The default link width is multiplied by 1000
189*4882a593Smuzhiyun * to get accurate value after division.
190*4882a593Smuzhiyun */
191*4882a593Smuzhiyun #define FACTOR_LINK_WIDTH (LINK_WIDTH_DEFAULT * DECIMAL_FACTORING)
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun struct ib_pma_portcounters_cong {
194*4882a593Smuzhiyun u8 reserved;
195*4882a593Smuzhiyun u8 reserved1;
196*4882a593Smuzhiyun __be16 port_check_rate;
197*4882a593Smuzhiyun __be16 symbol_error_counter;
198*4882a593Smuzhiyun u8 link_error_recovery_counter;
199*4882a593Smuzhiyun u8 link_downed_counter;
200*4882a593Smuzhiyun __be16 port_rcv_errors;
201*4882a593Smuzhiyun __be16 port_rcv_remphys_errors;
202*4882a593Smuzhiyun __be16 port_rcv_switch_relay_errors;
203*4882a593Smuzhiyun __be16 port_xmit_discards;
204*4882a593Smuzhiyun u8 port_xmit_constraint_errors;
205*4882a593Smuzhiyun u8 port_rcv_constraint_errors;
206*4882a593Smuzhiyun u8 reserved2;
207*4882a593Smuzhiyun u8 link_overrun_errors; /* LocalLink: 7:4, BufferOverrun: 3:0 */
208*4882a593Smuzhiyun __be16 reserved3;
209*4882a593Smuzhiyun __be16 vl15_dropped;
210*4882a593Smuzhiyun __be64 port_xmit_data;
211*4882a593Smuzhiyun __be64 port_rcv_data;
212*4882a593Smuzhiyun __be64 port_xmit_packets;
213*4882a593Smuzhiyun __be64 port_rcv_packets;
214*4882a593Smuzhiyun __be64 port_xmit_wait;
215*4882a593Smuzhiyun __be64 port_adr_events;
216*4882a593Smuzhiyun } __packed;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun #define IB_SMP_UNSUP_VERSION cpu_to_be16(0x0004)
219*4882a593Smuzhiyun #define IB_SMP_UNSUP_METHOD cpu_to_be16(0x0008)
220*4882a593Smuzhiyun #define IB_SMP_UNSUP_METH_ATTR cpu_to_be16(0x000C)
221*4882a593Smuzhiyun #define IB_SMP_INVALID_FIELD cpu_to_be16(0x001C)
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun #define OPA_MAX_PREEMPT_CAP 32
224*4882a593Smuzhiyun #define OPA_VLARB_LOW_ELEMENTS 0
225*4882a593Smuzhiyun #define OPA_VLARB_HIGH_ELEMENTS 1
226*4882a593Smuzhiyun #define OPA_VLARB_PREEMPT_ELEMENTS 2
227*4882a593Smuzhiyun #define OPA_VLARB_PREEMPT_MATRIX 3
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun #define HFI1_XMIT_RATE_UNSUPPORTED 0x0
230*4882a593Smuzhiyun #define HFI1_XMIT_RATE_PICO 0x7
231*4882a593Smuzhiyun /* number of 4nsec cycles equaling 2secs */
232*4882a593Smuzhiyun #define HFI1_CONG_TIMER_PSINTERVAL 0x1DCD64EC
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun #define IB_CC_SVCTYPE_RC 0x0
235*4882a593Smuzhiyun #define IB_CC_SVCTYPE_UC 0x1
236*4882a593Smuzhiyun #define IB_CC_SVCTYPE_RD 0x2
237*4882a593Smuzhiyun #define IB_CC_SVCTYPE_UD 0x3
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun /*
240*4882a593Smuzhiyun * There should be an equivalent IB #define for the following, but
241*4882a593Smuzhiyun * I cannot find it.
242*4882a593Smuzhiyun */
243*4882a593Smuzhiyun #define OPA_CC_LOG_TYPE_HFI 2
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun struct opa_hfi1_cong_log_event_internal {
246*4882a593Smuzhiyun u32 lqpn;
247*4882a593Smuzhiyun u32 rqpn;
248*4882a593Smuzhiyun u8 sl;
249*4882a593Smuzhiyun u8 svc_type;
250*4882a593Smuzhiyun u32 rlid;
251*4882a593Smuzhiyun u64 timestamp; /* wider than 32 bits to detect 32 bit rollover */
252*4882a593Smuzhiyun };
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun struct opa_hfi1_cong_log_event {
255*4882a593Smuzhiyun u8 local_qp_cn_entry[3];
256*4882a593Smuzhiyun u8 remote_qp_number_cn_entry[3];
257*4882a593Smuzhiyun u8 sl_svc_type_cn_entry; /* 5 bits SL, 3 bits svc type */
258*4882a593Smuzhiyun u8 reserved;
259*4882a593Smuzhiyun __be32 remote_lid_cn_entry;
260*4882a593Smuzhiyun __be32 timestamp_cn_entry;
261*4882a593Smuzhiyun } __packed;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun #define OPA_CONG_LOG_ELEMS 96
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun struct opa_hfi1_cong_log {
266*4882a593Smuzhiyun u8 log_type;
267*4882a593Smuzhiyun u8 congestion_flags;
268*4882a593Smuzhiyun __be16 threshold_event_counter;
269*4882a593Smuzhiyun __be32 current_time_stamp;
270*4882a593Smuzhiyun u8 threshold_cong_event_map[OPA_MAX_SLS / 8];
271*4882a593Smuzhiyun struct opa_hfi1_cong_log_event events[OPA_CONG_LOG_ELEMS];
272*4882a593Smuzhiyun } __packed;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun #define IB_CC_TABLE_CAP_DEFAULT 31
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun /* Port control flags */
277*4882a593Smuzhiyun #define IB_CC_CCS_PC_SL_BASED 0x01
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun struct opa_congestion_setting_entry {
280*4882a593Smuzhiyun u8 ccti_increase;
281*4882a593Smuzhiyun u8 reserved;
282*4882a593Smuzhiyun __be16 ccti_timer;
283*4882a593Smuzhiyun u8 trigger_threshold;
284*4882a593Smuzhiyun u8 ccti_min; /* min CCTI for cc table */
285*4882a593Smuzhiyun } __packed;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun struct opa_congestion_setting_entry_shadow {
288*4882a593Smuzhiyun u8 ccti_increase;
289*4882a593Smuzhiyun u8 reserved;
290*4882a593Smuzhiyun u16 ccti_timer;
291*4882a593Smuzhiyun u8 trigger_threshold;
292*4882a593Smuzhiyun u8 ccti_min; /* min CCTI for cc table */
293*4882a593Smuzhiyun } __packed;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun struct opa_congestion_setting_attr {
296*4882a593Smuzhiyun __be32 control_map;
297*4882a593Smuzhiyun __be16 port_control;
298*4882a593Smuzhiyun struct opa_congestion_setting_entry entries[OPA_MAX_SLS];
299*4882a593Smuzhiyun } __packed;
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun struct opa_congestion_setting_attr_shadow {
302*4882a593Smuzhiyun u32 control_map;
303*4882a593Smuzhiyun u16 port_control;
304*4882a593Smuzhiyun struct opa_congestion_setting_entry_shadow entries[OPA_MAX_SLS];
305*4882a593Smuzhiyun } __packed;
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun #define IB_CC_TABLE_ENTRY_INCREASE_DEFAULT 1
308*4882a593Smuzhiyun #define IB_CC_TABLE_ENTRY_TIMER_DEFAULT 1
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun /* 64 Congestion Control table entries in a single MAD */
311*4882a593Smuzhiyun #define IB_CCT_ENTRIES 64
312*4882a593Smuzhiyun #define IB_CCT_MIN_ENTRIES (IB_CCT_ENTRIES * 2)
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun struct ib_cc_table_entry {
315*4882a593Smuzhiyun __be16 entry; /* shift:2, multiplier:14 */
316*4882a593Smuzhiyun };
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun struct ib_cc_table_entry_shadow {
319*4882a593Smuzhiyun u16 entry; /* shift:2, multiplier:14 */
320*4882a593Smuzhiyun };
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun struct ib_cc_table_attr {
323*4882a593Smuzhiyun __be16 ccti_limit; /* max CCTI for cc table */
324*4882a593Smuzhiyun struct ib_cc_table_entry ccti_entries[IB_CCT_ENTRIES];
325*4882a593Smuzhiyun } __packed;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun struct ib_cc_table_attr_shadow {
328*4882a593Smuzhiyun u16 ccti_limit; /* max CCTI for cc table */
329*4882a593Smuzhiyun struct ib_cc_table_entry_shadow ccti_entries[IB_CCT_ENTRIES];
330*4882a593Smuzhiyun } __packed;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun #define CC_TABLE_SHADOW_MAX \
333*4882a593Smuzhiyun (IB_CC_TABLE_CAP_DEFAULT * IB_CCT_ENTRIES)
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun struct cc_table_shadow {
336*4882a593Smuzhiyun u16 ccti_limit; /* max CCTI for cc table */
337*4882a593Smuzhiyun struct ib_cc_table_entry_shadow entries[CC_TABLE_SHADOW_MAX];
338*4882a593Smuzhiyun } __packed;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun /*
341*4882a593Smuzhiyun * struct cc_state combines the (active) per-port congestion control
342*4882a593Smuzhiyun * table, and the (active) per-SL congestion settings. cc_state data
343*4882a593Smuzhiyun * may need to be read in code paths that we want to be fast, so it
344*4882a593Smuzhiyun * is an RCU protected structure.
345*4882a593Smuzhiyun */
346*4882a593Smuzhiyun struct cc_state {
347*4882a593Smuzhiyun struct rcu_head rcu;
348*4882a593Smuzhiyun struct cc_table_shadow cct;
349*4882a593Smuzhiyun struct opa_congestion_setting_attr_shadow cong_setting;
350*4882a593Smuzhiyun };
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun /*
353*4882a593Smuzhiyun * OPA BufferControl MAD
354*4882a593Smuzhiyun */
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun /* attribute modifier macros */
357*4882a593Smuzhiyun #define OPA_AM_NPORT_SHIFT 24
358*4882a593Smuzhiyun #define OPA_AM_NPORT_MASK 0xff
359*4882a593Smuzhiyun #define OPA_AM_NPORT_SMASK (OPA_AM_NPORT_MASK << OPA_AM_NPORT_SHIFT)
360*4882a593Smuzhiyun #define OPA_AM_NPORT(am) (((am) >> OPA_AM_NPORT_SHIFT) & \
361*4882a593Smuzhiyun OPA_AM_NPORT_MASK)
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun #define OPA_AM_NBLK_SHIFT 24
364*4882a593Smuzhiyun #define OPA_AM_NBLK_MASK 0xff
365*4882a593Smuzhiyun #define OPA_AM_NBLK_SMASK (OPA_AM_NBLK_MASK << OPA_AM_NBLK_SHIFT)
366*4882a593Smuzhiyun #define OPA_AM_NBLK(am) (((am) >> OPA_AM_NBLK_SHIFT) & \
367*4882a593Smuzhiyun OPA_AM_NBLK_MASK)
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun #define OPA_AM_START_BLK_SHIFT 0
370*4882a593Smuzhiyun #define OPA_AM_START_BLK_MASK 0xff
371*4882a593Smuzhiyun #define OPA_AM_START_BLK_SMASK (OPA_AM_START_BLK_MASK << \
372*4882a593Smuzhiyun OPA_AM_START_BLK_SHIFT)
373*4882a593Smuzhiyun #define OPA_AM_START_BLK(am) (((am) >> OPA_AM_START_BLK_SHIFT) & \
374*4882a593Smuzhiyun OPA_AM_START_BLK_MASK)
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun #define OPA_AM_PORTNUM_SHIFT 0
377*4882a593Smuzhiyun #define OPA_AM_PORTNUM_MASK 0xff
378*4882a593Smuzhiyun #define OPA_AM_PORTNUM_SMASK (OPA_AM_PORTNUM_MASK << OPA_AM_PORTNUM_SHIFT)
379*4882a593Smuzhiyun #define OPA_AM_PORTNUM(am) (((am) >> OPA_AM_PORTNUM_SHIFT) & \
380*4882a593Smuzhiyun OPA_AM_PORTNUM_MASK)
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun #define OPA_AM_ASYNC_SHIFT 12
383*4882a593Smuzhiyun #define OPA_AM_ASYNC_MASK 0x1
384*4882a593Smuzhiyun #define OPA_AM_ASYNC_SMASK (OPA_AM_ASYNC_MASK << OPA_AM_ASYNC_SHIFT)
385*4882a593Smuzhiyun #define OPA_AM_ASYNC(am) (((am) >> OPA_AM_ASYNC_SHIFT) & \
386*4882a593Smuzhiyun OPA_AM_ASYNC_MASK)
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun #define OPA_AM_START_SM_CFG_SHIFT 9
389*4882a593Smuzhiyun #define OPA_AM_START_SM_CFG_MASK 0x1
390*4882a593Smuzhiyun #define OPA_AM_START_SM_CFG_SMASK (OPA_AM_START_SM_CFG_MASK << \
391*4882a593Smuzhiyun OPA_AM_START_SM_CFG_SHIFT)
392*4882a593Smuzhiyun #define OPA_AM_START_SM_CFG(am) (((am) >> OPA_AM_START_SM_CFG_SHIFT) \
393*4882a593Smuzhiyun & OPA_AM_START_SM_CFG_MASK)
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun #define OPA_AM_CI_ADDR_SHIFT 19
396*4882a593Smuzhiyun #define OPA_AM_CI_ADDR_MASK 0xfff
397*4882a593Smuzhiyun #define OPA_AM_CI_ADDR_SMASK (OPA_AM_CI_ADDR_MASK << OPA_CI_ADDR_SHIFT)
398*4882a593Smuzhiyun #define OPA_AM_CI_ADDR(am) (((am) >> OPA_AM_CI_ADDR_SHIFT) & \
399*4882a593Smuzhiyun OPA_AM_CI_ADDR_MASK)
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun #define OPA_AM_CI_LEN_SHIFT 13
402*4882a593Smuzhiyun #define OPA_AM_CI_LEN_MASK 0x3f
403*4882a593Smuzhiyun #define OPA_AM_CI_LEN_SMASK (OPA_AM_CI_LEN_MASK << OPA_CI_LEN_SHIFT)
404*4882a593Smuzhiyun #define OPA_AM_CI_LEN(am) (((am) >> OPA_AM_CI_LEN_SHIFT) & \
405*4882a593Smuzhiyun OPA_AM_CI_LEN_MASK)
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun /* error info macros */
408*4882a593Smuzhiyun #define OPA_EI_STATUS_SMASK 0x80
409*4882a593Smuzhiyun #define OPA_EI_CODE_SMASK 0x0f
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun struct vl_limit {
412*4882a593Smuzhiyun __be16 dedicated;
413*4882a593Smuzhiyun __be16 shared;
414*4882a593Smuzhiyun };
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun struct buffer_control {
417*4882a593Smuzhiyun __be16 reserved;
418*4882a593Smuzhiyun __be16 overall_shared_limit;
419*4882a593Smuzhiyun struct vl_limit vl[OPA_MAX_VLS];
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun struct sc2vlnt {
423*4882a593Smuzhiyun u8 vlnt[32]; /* 5 bit VL, 3 bits reserved */
424*4882a593Smuzhiyun };
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun /*
427*4882a593Smuzhiyun * The PortSamplesControl.CounterMasks field is an array of 3 bit fields
428*4882a593Smuzhiyun * which specify the N'th counter's capabilities. See ch. 16.1.3.2.
429*4882a593Smuzhiyun * We support 5 counters which only count the mandatory quantities.
430*4882a593Smuzhiyun */
431*4882a593Smuzhiyun #define COUNTER_MASK(q, n) (q << ((9 - n) * 3))
432*4882a593Smuzhiyun #define COUNTER_MASK0_9 \
433*4882a593Smuzhiyun cpu_to_be32(COUNTER_MASK(1, 0) | \
434*4882a593Smuzhiyun COUNTER_MASK(1, 1) | \
435*4882a593Smuzhiyun COUNTER_MASK(1, 2) | \
436*4882a593Smuzhiyun COUNTER_MASK(1, 3) | \
437*4882a593Smuzhiyun COUNTER_MASK(1, 4))
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun void hfi1_event_pkey_change(struct hfi1_devdata *dd, u8 port);
440*4882a593Smuzhiyun void hfi1_handle_trap_timer(struct timer_list *t);
441*4882a593Smuzhiyun u16 tx_link_width(u16 link_width);
442*4882a593Smuzhiyun u64 get_xmit_wait_counters(struct hfi1_pportdata *ppd, u16 link_width,
443*4882a593Smuzhiyun u16 link_speed, int vl);
444*4882a593Smuzhiyun /**
445*4882a593Smuzhiyun * get_link_speed - determine whether 12.5G or 25G speed
446*4882a593Smuzhiyun * @link_speed: the speed of active link
447*4882a593Smuzhiyun * @return: Return 2 if link speed identified as 12.5G
448*4882a593Smuzhiyun * or return 1 if link speed is 25G.
449*4882a593Smuzhiyun *
450*4882a593Smuzhiyun * The function indirectly calculate required link speed
451*4882a593Smuzhiyun * value for convert_xmit_counter function. If the link
452*4882a593Smuzhiyun * speed is 25G, the function return as 1 as it is required
453*4882a593Smuzhiyun * by xmit counter conversion formula :-( 25G / link_speed).
454*4882a593Smuzhiyun * This conversion will provide value 1 if current
455*4882a593Smuzhiyun * link speed is 25G or 2 if 12.5G.This is done to avoid
456*4882a593Smuzhiyun * 12.5 float number conversion.
457*4882a593Smuzhiyun */
get_link_speed(u16 link_speed)458*4882a593Smuzhiyun static inline u16 get_link_speed(u16 link_speed)
459*4882a593Smuzhiyun {
460*4882a593Smuzhiyun return (link_speed == 1) ?
461*4882a593Smuzhiyun LINK_SPEED_12_5G : LINK_SPEED_25G;
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun /**
465*4882a593Smuzhiyun * convert_xmit_counter - calculate flit times for given xmit counter
466*4882a593Smuzhiyun * value
467*4882a593Smuzhiyun * @xmit_wait_val: current xmit counter value
468*4882a593Smuzhiyun * @link_width: width of active link
469*4882a593Smuzhiyun * @link_speed: speed of active link
470*4882a593Smuzhiyun * @return: return xmit counter value in flit times.
471*4882a593Smuzhiyun */
convert_xmit_counter(u64 xmit_wait_val,u16 link_width,u16 link_speed)472*4882a593Smuzhiyun static inline u64 convert_xmit_counter(u64 xmit_wait_val, u16 link_width,
473*4882a593Smuzhiyun u16 link_speed)
474*4882a593Smuzhiyun {
475*4882a593Smuzhiyun return (xmit_wait_val * 2 * (FACTOR_LINK_WIDTH / link_width)
476*4882a593Smuzhiyun * link_speed) / DECIMAL_FACTORING;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun #endif /* _HFI1_MAD_H */
479