1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright(c) 2015 - 2020 Intel Corporation.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This file is provided under a dual BSD/GPLv2 license. When using or
5*4882a593Smuzhiyun * redistributing this file, you may do so under either license.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * GPL LICENSE SUMMARY
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
10*4882a593Smuzhiyun * it under the terms of version 2 of the GNU General Public License as
11*4882a593Smuzhiyun * published by the Free Software Foundation.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * This program is distributed in the hope that it will be useful, but
14*4882a593Smuzhiyun * WITHOUT ANY WARRANTY; without even the implied warranty of
15*4882a593Smuzhiyun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16*4882a593Smuzhiyun * General Public License for more details.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * BSD LICENSE
19*4882a593Smuzhiyun *
20*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without
21*4882a593Smuzhiyun * modification, are permitted provided that the following conditions
22*4882a593Smuzhiyun * are met:
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * - Redistributions of source code must retain the above copyright
25*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer.
26*4882a593Smuzhiyun * - Redistributions in binary form must reproduce the above copyright
27*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in
28*4882a593Smuzhiyun * the documentation and/or other materials provided with the
29*4882a593Smuzhiyun * distribution.
30*4882a593Smuzhiyun * - Neither the name of Intel Corporation nor the names of its
31*4882a593Smuzhiyun * contributors may be used to endorse or promote products derived
32*4882a593Smuzhiyun * from this software without specific prior written permission.
33*4882a593Smuzhiyun *
34*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
35*4882a593Smuzhiyun * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
36*4882a593Smuzhiyun * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
37*4882a593Smuzhiyun * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
38*4882a593Smuzhiyun * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
39*4882a593Smuzhiyun * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
40*4882a593Smuzhiyun * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
41*4882a593Smuzhiyun * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
42*4882a593Smuzhiyun * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43*4882a593Smuzhiyun * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
44*4882a593Smuzhiyun * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45*4882a593Smuzhiyun *
46*4882a593Smuzhiyun */
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #ifndef _COMMON_H
49*4882a593Smuzhiyun #define _COMMON_H
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #include <rdma/hfi/hfi1_user.h>
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun * This file contains defines, structures, etc. that are used
55*4882a593Smuzhiyun * to communicate between kernel and user code.
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* version of protocol header (known to chip also). In the long run,
59*4882a593Smuzhiyun * we should be able to generate and accept a range of version numbers;
60*4882a593Smuzhiyun * for now we only accept one, and it's compiled in.
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun #define IPS_PROTO_VERSION 2
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /*
65*4882a593Smuzhiyun * These are compile time constants that you may want to enable or disable
66*4882a593Smuzhiyun * if you are trying to debug problems with code or performance.
67*4882a593Smuzhiyun * HFI1_VERBOSE_TRACING define as 1 if you want additional tracing in
68*4882a593Smuzhiyun * fast path code
69*4882a593Smuzhiyun * HFI1_TRACE_REGWRITES define as 1 if you want register writes to be
70*4882a593Smuzhiyun * traced in fast path code
71*4882a593Smuzhiyun * _HFI1_TRACING define as 0 if you want to remove all tracing in a
72*4882a593Smuzhiyun * compilation unit
73*4882a593Smuzhiyun */
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* driver/hw feature set bitmask */
76*4882a593Smuzhiyun #define HFI1_CAP_USER_SHIFT 24
77*4882a593Smuzhiyun #define HFI1_CAP_MASK ((1UL << HFI1_CAP_USER_SHIFT) - 1)
78*4882a593Smuzhiyun /* locked flag - if set, only HFI1_CAP_WRITABLE_MASK bits can be set */
79*4882a593Smuzhiyun #define HFI1_CAP_LOCKED_SHIFT 63
80*4882a593Smuzhiyun #define HFI1_CAP_LOCKED_MASK 0x1ULL
81*4882a593Smuzhiyun #define HFI1_CAP_LOCKED_SMASK (HFI1_CAP_LOCKED_MASK << HFI1_CAP_LOCKED_SHIFT)
82*4882a593Smuzhiyun /* extra bits used between kernel and user processes */
83*4882a593Smuzhiyun #define HFI1_CAP_MISC_SHIFT (HFI1_CAP_USER_SHIFT * 2)
84*4882a593Smuzhiyun #define HFI1_CAP_MISC_MASK ((1ULL << (HFI1_CAP_LOCKED_SHIFT - \
85*4882a593Smuzhiyun HFI1_CAP_MISC_SHIFT)) - 1)
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #define HFI1_CAP_KSET(cap) ({ hfi1_cap_mask |= HFI1_CAP_##cap; hfi1_cap_mask; })
88*4882a593Smuzhiyun #define HFI1_CAP_KCLEAR(cap) \
89*4882a593Smuzhiyun ({ \
90*4882a593Smuzhiyun hfi1_cap_mask &= ~HFI1_CAP_##cap; \
91*4882a593Smuzhiyun hfi1_cap_mask; \
92*4882a593Smuzhiyun })
93*4882a593Smuzhiyun #define HFI1_CAP_USET(cap) \
94*4882a593Smuzhiyun ({ \
95*4882a593Smuzhiyun hfi1_cap_mask |= (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
96*4882a593Smuzhiyun hfi1_cap_mask; \
97*4882a593Smuzhiyun })
98*4882a593Smuzhiyun #define HFI1_CAP_UCLEAR(cap) \
99*4882a593Smuzhiyun ({ \
100*4882a593Smuzhiyun hfi1_cap_mask &= ~(HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT); \
101*4882a593Smuzhiyun hfi1_cap_mask; \
102*4882a593Smuzhiyun })
103*4882a593Smuzhiyun #define HFI1_CAP_SET(cap) \
104*4882a593Smuzhiyun ({ \
105*4882a593Smuzhiyun hfi1_cap_mask |= (HFI1_CAP_##cap | (HFI1_CAP_##cap << \
106*4882a593Smuzhiyun HFI1_CAP_USER_SHIFT)); \
107*4882a593Smuzhiyun hfi1_cap_mask; \
108*4882a593Smuzhiyun })
109*4882a593Smuzhiyun #define HFI1_CAP_CLEAR(cap) \
110*4882a593Smuzhiyun ({ \
111*4882a593Smuzhiyun hfi1_cap_mask &= ~(HFI1_CAP_##cap | \
112*4882a593Smuzhiyun (HFI1_CAP_##cap << HFI1_CAP_USER_SHIFT)); \
113*4882a593Smuzhiyun hfi1_cap_mask; \
114*4882a593Smuzhiyun })
115*4882a593Smuzhiyun #define HFI1_CAP_LOCK() \
116*4882a593Smuzhiyun ({ hfi1_cap_mask |= HFI1_CAP_LOCKED_SMASK; hfi1_cap_mask; })
117*4882a593Smuzhiyun #define HFI1_CAP_LOCKED() (!!(hfi1_cap_mask & HFI1_CAP_LOCKED_SMASK))
118*4882a593Smuzhiyun /*
119*4882a593Smuzhiyun * The set of capability bits that can be changed after initial load
120*4882a593Smuzhiyun * This set is the same for kernel and user contexts. However, for
121*4882a593Smuzhiyun * user contexts, the set can be further filtered by using the
122*4882a593Smuzhiyun * HFI1_CAP_RESERVED_MASK bits.
123*4882a593Smuzhiyun */
124*4882a593Smuzhiyun #define HFI1_CAP_WRITABLE_MASK (HFI1_CAP_SDMA_AHG | \
125*4882a593Smuzhiyun HFI1_CAP_HDRSUPP | \
126*4882a593Smuzhiyun HFI1_CAP_MULTI_PKT_EGR | \
127*4882a593Smuzhiyun HFI1_CAP_NODROP_RHQ_FULL | \
128*4882a593Smuzhiyun HFI1_CAP_NODROP_EGR_FULL | \
129*4882a593Smuzhiyun HFI1_CAP_ALLOW_PERM_JKEY | \
130*4882a593Smuzhiyun HFI1_CAP_STATIC_RATE_CTRL | \
131*4882a593Smuzhiyun HFI1_CAP_PRINT_UNIMPL | \
132*4882a593Smuzhiyun HFI1_CAP_TID_UNMAP | \
133*4882a593Smuzhiyun HFI1_CAP_OPFN)
134*4882a593Smuzhiyun /*
135*4882a593Smuzhiyun * A set of capability bits that are "global" and are not allowed to be
136*4882a593Smuzhiyun * set in the user bitmask.
137*4882a593Smuzhiyun */
138*4882a593Smuzhiyun #define HFI1_CAP_RESERVED_MASK ((HFI1_CAP_SDMA | \
139*4882a593Smuzhiyun HFI1_CAP_USE_SDMA_HEAD | \
140*4882a593Smuzhiyun HFI1_CAP_EXTENDED_PSN | \
141*4882a593Smuzhiyun HFI1_CAP_PRINT_UNIMPL | \
142*4882a593Smuzhiyun HFI1_CAP_NO_INTEGRITY | \
143*4882a593Smuzhiyun HFI1_CAP_PKEY_CHECK | \
144*4882a593Smuzhiyun HFI1_CAP_TID_RDMA | \
145*4882a593Smuzhiyun HFI1_CAP_OPFN | \
146*4882a593Smuzhiyun HFI1_CAP_AIP) << \
147*4882a593Smuzhiyun HFI1_CAP_USER_SHIFT)
148*4882a593Smuzhiyun /*
149*4882a593Smuzhiyun * Set of capabilities that need to be enabled for kernel context in
150*4882a593Smuzhiyun * order to be allowed for user contexts, as well.
151*4882a593Smuzhiyun */
152*4882a593Smuzhiyun #define HFI1_CAP_MUST_HAVE_KERN (HFI1_CAP_STATIC_RATE_CTRL)
153*4882a593Smuzhiyun /* Default enabled capabilities (both kernel and user) */
154*4882a593Smuzhiyun #define HFI1_CAP_MASK_DEFAULT (HFI1_CAP_HDRSUPP | \
155*4882a593Smuzhiyun HFI1_CAP_NODROP_RHQ_FULL | \
156*4882a593Smuzhiyun HFI1_CAP_NODROP_EGR_FULL | \
157*4882a593Smuzhiyun HFI1_CAP_SDMA | \
158*4882a593Smuzhiyun HFI1_CAP_PRINT_UNIMPL | \
159*4882a593Smuzhiyun HFI1_CAP_STATIC_RATE_CTRL | \
160*4882a593Smuzhiyun HFI1_CAP_PKEY_CHECK | \
161*4882a593Smuzhiyun HFI1_CAP_MULTI_PKT_EGR | \
162*4882a593Smuzhiyun HFI1_CAP_EXTENDED_PSN | \
163*4882a593Smuzhiyun HFI1_CAP_AIP | \
164*4882a593Smuzhiyun ((HFI1_CAP_HDRSUPP | \
165*4882a593Smuzhiyun HFI1_CAP_MULTI_PKT_EGR | \
166*4882a593Smuzhiyun HFI1_CAP_STATIC_RATE_CTRL | \
167*4882a593Smuzhiyun HFI1_CAP_PKEY_CHECK | \
168*4882a593Smuzhiyun HFI1_CAP_EARLY_CREDIT_RETURN) << \
169*4882a593Smuzhiyun HFI1_CAP_USER_SHIFT))
170*4882a593Smuzhiyun /*
171*4882a593Smuzhiyun * A bitmask of kernel/global capabilities that should be communicated
172*4882a593Smuzhiyun * to user level processes.
173*4882a593Smuzhiyun */
174*4882a593Smuzhiyun #define HFI1_CAP_K2U (HFI1_CAP_SDMA | \
175*4882a593Smuzhiyun HFI1_CAP_EXTENDED_PSN | \
176*4882a593Smuzhiyun HFI1_CAP_PKEY_CHECK | \
177*4882a593Smuzhiyun HFI1_CAP_NO_INTEGRITY)
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun #define HFI1_USER_SWVERSION ((HFI1_USER_SWMAJOR << HFI1_SWMAJOR_SHIFT) | \
180*4882a593Smuzhiyun HFI1_USER_SWMINOR)
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun #ifndef HFI1_KERN_TYPE
183*4882a593Smuzhiyun #define HFI1_KERN_TYPE 0
184*4882a593Smuzhiyun #endif
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun /*
187*4882a593Smuzhiyun * Similarly, this is the kernel version going back to the user. It's
188*4882a593Smuzhiyun * slightly different, in that we want to tell if the driver was built as
189*4882a593Smuzhiyun * part of a Intel release, or from the driver from openfabrics.org,
190*4882a593Smuzhiyun * kernel.org, or a standard distribution, for support reasons.
191*4882a593Smuzhiyun * The high bit is 0 for non-Intel and 1 for Intel-built/supplied.
192*4882a593Smuzhiyun *
193*4882a593Smuzhiyun * It's returned by the driver to the user code during initialization in the
194*4882a593Smuzhiyun * spi_sw_version field of hfi1_base_info, so the user code can in turn
195*4882a593Smuzhiyun * check for compatibility with the kernel.
196*4882a593Smuzhiyun */
197*4882a593Smuzhiyun #define HFI1_KERN_SWVERSION ((HFI1_KERN_TYPE << 31) | HFI1_USER_SWVERSION)
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun /*
200*4882a593Smuzhiyun * Define the driver version number. This is something that refers only
201*4882a593Smuzhiyun * to the driver itself, not the software interfaces it supports.
202*4882a593Smuzhiyun */
203*4882a593Smuzhiyun #ifndef HFI1_DRIVER_VERSION_BASE
204*4882a593Smuzhiyun #define HFI1_DRIVER_VERSION_BASE "0.9-294"
205*4882a593Smuzhiyun #endif
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun /* create the final driver version string */
208*4882a593Smuzhiyun #ifdef HFI1_IDSTR
209*4882a593Smuzhiyun #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE " " HFI1_IDSTR
210*4882a593Smuzhiyun #else
211*4882a593Smuzhiyun #define HFI1_DRIVER_VERSION HFI1_DRIVER_VERSION_BASE
212*4882a593Smuzhiyun #endif
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun /*
215*4882a593Smuzhiyun * Diagnostics can send a packet by writing the following
216*4882a593Smuzhiyun * struct to the diag packet special file.
217*4882a593Smuzhiyun *
218*4882a593Smuzhiyun * This allows a custom PBC qword, so that special modes and deliberate
219*4882a593Smuzhiyun * changes to CRCs can be used.
220*4882a593Smuzhiyun */
221*4882a593Smuzhiyun #define _DIAG_PKT_VERS 1
222*4882a593Smuzhiyun struct diag_pkt {
223*4882a593Smuzhiyun __u16 version; /* structure version */
224*4882a593Smuzhiyun __u16 unit; /* which device */
225*4882a593Smuzhiyun __u16 sw_index; /* send sw index to use */
226*4882a593Smuzhiyun __u16 len; /* data length, in bytes */
227*4882a593Smuzhiyun __u16 port; /* port number */
228*4882a593Smuzhiyun __u16 unused;
229*4882a593Smuzhiyun __u32 flags; /* call flags */
230*4882a593Smuzhiyun __u64 data; /* user data pointer */
231*4882a593Smuzhiyun __u64 pbc; /* PBC for the packet */
232*4882a593Smuzhiyun };
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /* diag_pkt flags */
235*4882a593Smuzhiyun #define F_DIAGPKT_WAIT 0x1 /* wait until packet is sent */
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun /*
238*4882a593Smuzhiyun * The next set of defines are for packet headers, and chip register
239*4882a593Smuzhiyun * and memory bits that are visible to and/or used by user-mode software.
240*4882a593Smuzhiyun */
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun /*
243*4882a593Smuzhiyun * Receive Header Flags
244*4882a593Smuzhiyun */
245*4882a593Smuzhiyun #define RHF_PKT_LEN_SHIFT 0
246*4882a593Smuzhiyun #define RHF_PKT_LEN_MASK 0xfffull
247*4882a593Smuzhiyun #define RHF_PKT_LEN_SMASK (RHF_PKT_LEN_MASK << RHF_PKT_LEN_SHIFT)
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun #define RHF_RCV_TYPE_SHIFT 12
250*4882a593Smuzhiyun #define RHF_RCV_TYPE_MASK 0x7ull
251*4882a593Smuzhiyun #define RHF_RCV_TYPE_SMASK (RHF_RCV_TYPE_MASK << RHF_RCV_TYPE_SHIFT)
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun #define RHF_USE_EGR_BFR_SHIFT 15
254*4882a593Smuzhiyun #define RHF_USE_EGR_BFR_MASK 0x1ull
255*4882a593Smuzhiyun #define RHF_USE_EGR_BFR_SMASK (RHF_USE_EGR_BFR_MASK << RHF_USE_EGR_BFR_SHIFT)
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun #define RHF_EGR_INDEX_SHIFT 16
258*4882a593Smuzhiyun #define RHF_EGR_INDEX_MASK 0x7ffull
259*4882a593Smuzhiyun #define RHF_EGR_INDEX_SMASK (RHF_EGR_INDEX_MASK << RHF_EGR_INDEX_SHIFT)
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun #define RHF_DC_INFO_SHIFT 27
262*4882a593Smuzhiyun #define RHF_DC_INFO_MASK 0x1ull
263*4882a593Smuzhiyun #define RHF_DC_INFO_SMASK (RHF_DC_INFO_MASK << RHF_DC_INFO_SHIFT)
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun #define RHF_RCV_SEQ_SHIFT 28
266*4882a593Smuzhiyun #define RHF_RCV_SEQ_MASK 0xfull
267*4882a593Smuzhiyun #define RHF_RCV_SEQ_SMASK (RHF_RCV_SEQ_MASK << RHF_RCV_SEQ_SHIFT)
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun #define RHF_EGR_OFFSET_SHIFT 32
270*4882a593Smuzhiyun #define RHF_EGR_OFFSET_MASK 0xfffull
271*4882a593Smuzhiyun #define RHF_EGR_OFFSET_SMASK (RHF_EGR_OFFSET_MASK << RHF_EGR_OFFSET_SHIFT)
272*4882a593Smuzhiyun #define RHF_HDRQ_OFFSET_SHIFT 44
273*4882a593Smuzhiyun #define RHF_HDRQ_OFFSET_MASK 0x1ffull
274*4882a593Smuzhiyun #define RHF_HDRQ_OFFSET_SMASK (RHF_HDRQ_OFFSET_MASK << RHF_HDRQ_OFFSET_SHIFT)
275*4882a593Smuzhiyun #define RHF_K_HDR_LEN_ERR (0x1ull << 53)
276*4882a593Smuzhiyun #define RHF_DC_UNC_ERR (0x1ull << 54)
277*4882a593Smuzhiyun #define RHF_DC_ERR (0x1ull << 55)
278*4882a593Smuzhiyun #define RHF_RCV_TYPE_ERR_SHIFT 56
279*4882a593Smuzhiyun #define RHF_RCV_TYPE_ERR_MASK 0x7ul
280*4882a593Smuzhiyun #define RHF_RCV_TYPE_ERR_SMASK (RHF_RCV_TYPE_ERR_MASK << RHF_RCV_TYPE_ERR_SHIFT)
281*4882a593Smuzhiyun #define RHF_TID_ERR (0x1ull << 59)
282*4882a593Smuzhiyun #define RHF_LEN_ERR (0x1ull << 60)
283*4882a593Smuzhiyun #define RHF_ECC_ERR (0x1ull << 61)
284*4882a593Smuzhiyun #define RHF_RESERVED (0x1ull << 62)
285*4882a593Smuzhiyun #define RHF_ICRC_ERR (0x1ull << 63)
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun #define RHF_ERROR_SMASK 0xffe0000000000000ull /* bits 63:53 */
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun /* RHF receive types */
290*4882a593Smuzhiyun #define RHF_RCV_TYPE_EXPECTED 0
291*4882a593Smuzhiyun #define RHF_RCV_TYPE_EAGER 1
292*4882a593Smuzhiyun #define RHF_RCV_TYPE_IB 2 /* normal IB, IB Raw, or IPv6 */
293*4882a593Smuzhiyun #define RHF_RCV_TYPE_ERROR 3
294*4882a593Smuzhiyun #define RHF_RCV_TYPE_BYPASS 4
295*4882a593Smuzhiyun #define RHF_RCV_TYPE_INVALID5 5
296*4882a593Smuzhiyun #define RHF_RCV_TYPE_INVALID6 6
297*4882a593Smuzhiyun #define RHF_RCV_TYPE_INVALID7 7
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun /* RHF receive type error - expected packet errors */
300*4882a593Smuzhiyun #define RHF_RTE_EXPECTED_FLOW_SEQ_ERR 0x2
301*4882a593Smuzhiyun #define RHF_RTE_EXPECTED_FLOW_GEN_ERR 0x4
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun /* RHF receive type error - eager packet errors */
304*4882a593Smuzhiyun #define RHF_RTE_EAGER_NO_ERR 0x0
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun /* RHF receive type error - IB packet errors */
307*4882a593Smuzhiyun #define RHF_RTE_IB_NO_ERR 0x0
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun /* RHF receive type error - error packet errors */
310*4882a593Smuzhiyun #define RHF_RTE_ERROR_NO_ERR 0x0
311*4882a593Smuzhiyun #define RHF_RTE_ERROR_OP_CODE_ERR 0x1
312*4882a593Smuzhiyun #define RHF_RTE_ERROR_KHDR_MIN_LEN_ERR 0x2
313*4882a593Smuzhiyun #define RHF_RTE_ERROR_KHDR_HCRC_ERR 0x3
314*4882a593Smuzhiyun #define RHF_RTE_ERROR_KHDR_KVER_ERR 0x4
315*4882a593Smuzhiyun #define RHF_RTE_ERROR_CONTEXT_ERR 0x5
316*4882a593Smuzhiyun #define RHF_RTE_ERROR_KHDR_TID_ERR 0x6
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun /* RHF receive type error - bypass packet errors */
319*4882a593Smuzhiyun #define RHF_RTE_BYPASS_NO_ERR 0x0
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun /* MAX RcvSEQ */
322*4882a593Smuzhiyun #define RHF_MAX_SEQ 13
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun /* IB - LRH header constants */
325*4882a593Smuzhiyun #define HFI1_LRH_GRH 0x0003 /* 1. word of IB LRH - next header: GRH */
326*4882a593Smuzhiyun #define HFI1_LRH_BTH 0x0002 /* 1. word of IB LRH - next header: BTH */
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun /* misc. */
329*4882a593Smuzhiyun #define SC15_PACKET 0xF
330*4882a593Smuzhiyun #define SIZE_OF_CRC 1
331*4882a593Smuzhiyun #define SIZE_OF_LT 1
332*4882a593Smuzhiyun #define MAX_16B_PADDING 12 /* CRC = 4, LT = 1, Pad = 0 to 7 bytes */
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun #define LIM_MGMT_P_KEY 0x7FFF
335*4882a593Smuzhiyun #define FULL_MGMT_P_KEY 0xFFFF
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun #define DEFAULT_P_KEY LIM_MGMT_P_KEY
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun #define HFI1_PSM_IOC_BASE_SEQ 0x0
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun /* Number of BTH.PSN bits used for sequence number in expected rcvs */
342*4882a593Smuzhiyun #define HFI1_KDETH_BTH_SEQ_SHIFT 11
343*4882a593Smuzhiyun #define HFI1_KDETH_BTH_SEQ_MASK (BIT(HFI1_KDETH_BTH_SEQ_SHIFT) - 1)
344*4882a593Smuzhiyun
rhf_to_cpu(const __le32 * rbuf)345*4882a593Smuzhiyun static inline __u64 rhf_to_cpu(const __le32 *rbuf)
346*4882a593Smuzhiyun {
347*4882a593Smuzhiyun return __le64_to_cpu(*((__le64 *)rbuf));
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun
rhf_err_flags(u64 rhf)350*4882a593Smuzhiyun static inline u64 rhf_err_flags(u64 rhf)
351*4882a593Smuzhiyun {
352*4882a593Smuzhiyun return rhf & RHF_ERROR_SMASK;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun
rhf_rcv_type(u64 rhf)355*4882a593Smuzhiyun static inline u32 rhf_rcv_type(u64 rhf)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun return (rhf >> RHF_RCV_TYPE_SHIFT) & RHF_RCV_TYPE_MASK;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
rhf_rcv_type_err(u64 rhf)360*4882a593Smuzhiyun static inline u32 rhf_rcv_type_err(u64 rhf)
361*4882a593Smuzhiyun {
362*4882a593Smuzhiyun return (rhf >> RHF_RCV_TYPE_ERR_SHIFT) & RHF_RCV_TYPE_ERR_MASK;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun /* return size is in bytes, not DWORDs */
rhf_pkt_len(u64 rhf)366*4882a593Smuzhiyun static inline u32 rhf_pkt_len(u64 rhf)
367*4882a593Smuzhiyun {
368*4882a593Smuzhiyun return ((rhf & RHF_PKT_LEN_SMASK) >> RHF_PKT_LEN_SHIFT) << 2;
369*4882a593Smuzhiyun }
370*4882a593Smuzhiyun
rhf_egr_index(u64 rhf)371*4882a593Smuzhiyun static inline u32 rhf_egr_index(u64 rhf)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun return (rhf >> RHF_EGR_INDEX_SHIFT) & RHF_EGR_INDEX_MASK;
374*4882a593Smuzhiyun }
375*4882a593Smuzhiyun
rhf_rcv_seq(u64 rhf)376*4882a593Smuzhiyun static inline u32 rhf_rcv_seq(u64 rhf)
377*4882a593Smuzhiyun {
378*4882a593Smuzhiyun return (rhf >> RHF_RCV_SEQ_SHIFT) & RHF_RCV_SEQ_MASK;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun
381*4882a593Smuzhiyun /* returned offset is in DWORDS */
rhf_hdrq_offset(u64 rhf)382*4882a593Smuzhiyun static inline u32 rhf_hdrq_offset(u64 rhf)
383*4882a593Smuzhiyun {
384*4882a593Smuzhiyun return (rhf >> RHF_HDRQ_OFFSET_SHIFT) & RHF_HDRQ_OFFSET_MASK;
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun
rhf_use_egr_bfr(u64 rhf)387*4882a593Smuzhiyun static inline u64 rhf_use_egr_bfr(u64 rhf)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun return rhf & RHF_USE_EGR_BFR_SMASK;
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun
rhf_dc_info(u64 rhf)392*4882a593Smuzhiyun static inline u64 rhf_dc_info(u64 rhf)
393*4882a593Smuzhiyun {
394*4882a593Smuzhiyun return rhf & RHF_DC_INFO_SMASK;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
rhf_egr_buf_offset(u64 rhf)397*4882a593Smuzhiyun static inline u32 rhf_egr_buf_offset(u64 rhf)
398*4882a593Smuzhiyun {
399*4882a593Smuzhiyun return (rhf >> RHF_EGR_OFFSET_SHIFT) & RHF_EGR_OFFSET_MASK;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun #endif /* _COMMON_H */
402