1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2018-2020 Amazon.com, Inc. or its affiliates. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _EFA_REGS_H_ 7*4882a593Smuzhiyun #define _EFA_REGS_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun enum efa_regs_reset_reason_types { 10*4882a593Smuzhiyun EFA_REGS_RESET_NORMAL = 0, 11*4882a593Smuzhiyun /* Keep alive timeout */ 12*4882a593Smuzhiyun EFA_REGS_RESET_KEEP_ALIVE_TO = 1, 13*4882a593Smuzhiyun EFA_REGS_RESET_ADMIN_TO = 2, 14*4882a593Smuzhiyun EFA_REGS_RESET_INIT_ERR = 3, 15*4882a593Smuzhiyun EFA_REGS_RESET_DRIVER_INVALID_STATE = 4, 16*4882a593Smuzhiyun EFA_REGS_RESET_OS_TRIGGER = 5, 17*4882a593Smuzhiyun EFA_REGS_RESET_SHUTDOWN = 6, 18*4882a593Smuzhiyun EFA_REGS_RESET_USER_TRIGGER = 7, 19*4882a593Smuzhiyun EFA_REGS_RESET_GENERIC = 8, 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* efa_registers offsets */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 0 base */ 25*4882a593Smuzhiyun #define EFA_REGS_VERSION_OFF 0x0 26*4882a593Smuzhiyun #define EFA_REGS_CONTROLLER_VERSION_OFF 0x4 27*4882a593Smuzhiyun #define EFA_REGS_CAPS_OFF 0x8 28*4882a593Smuzhiyun #define EFA_REGS_AQ_BASE_LO_OFF 0x10 29*4882a593Smuzhiyun #define EFA_REGS_AQ_BASE_HI_OFF 0x14 30*4882a593Smuzhiyun #define EFA_REGS_AQ_CAPS_OFF 0x18 31*4882a593Smuzhiyun #define EFA_REGS_ACQ_BASE_LO_OFF 0x20 32*4882a593Smuzhiyun #define EFA_REGS_ACQ_BASE_HI_OFF 0x24 33*4882a593Smuzhiyun #define EFA_REGS_ACQ_CAPS_OFF 0x28 34*4882a593Smuzhiyun #define EFA_REGS_AQ_PROD_DB_OFF 0x2c 35*4882a593Smuzhiyun #define EFA_REGS_AENQ_CAPS_OFF 0x34 36*4882a593Smuzhiyun #define EFA_REGS_AENQ_BASE_LO_OFF 0x38 37*4882a593Smuzhiyun #define EFA_REGS_AENQ_BASE_HI_OFF 0x3c 38*4882a593Smuzhiyun #define EFA_REGS_AENQ_CONS_DB_OFF 0x40 39*4882a593Smuzhiyun #define EFA_REGS_INTR_MASK_OFF 0x4c 40*4882a593Smuzhiyun #define EFA_REGS_DEV_CTL_OFF 0x54 41*4882a593Smuzhiyun #define EFA_REGS_DEV_STS_OFF 0x58 42*4882a593Smuzhiyun #define EFA_REGS_MMIO_REG_READ_OFF 0x5c 43*4882a593Smuzhiyun #define EFA_REGS_MMIO_RESP_LO_OFF 0x60 44*4882a593Smuzhiyun #define EFA_REGS_MMIO_RESP_HI_OFF 0x64 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* version register */ 47*4882a593Smuzhiyun #define EFA_REGS_VERSION_MINOR_VERSION_MASK 0xff 48*4882a593Smuzhiyun #define EFA_REGS_VERSION_MAJOR_VERSION_MASK 0xff00 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* controller_version register */ 51*4882a593Smuzhiyun #define EFA_REGS_CONTROLLER_VERSION_SUBMINOR_VERSION_MASK 0xff 52*4882a593Smuzhiyun #define EFA_REGS_CONTROLLER_VERSION_MINOR_VERSION_MASK 0xff00 53*4882a593Smuzhiyun #define EFA_REGS_CONTROLLER_VERSION_MAJOR_VERSION_MASK 0xff0000 54*4882a593Smuzhiyun #define EFA_REGS_CONTROLLER_VERSION_IMPL_ID_MASK 0xff000000 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* caps register */ 57*4882a593Smuzhiyun #define EFA_REGS_CAPS_CONTIGUOUS_QUEUE_REQUIRED_MASK 0x1 58*4882a593Smuzhiyun #define EFA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e 59*4882a593Smuzhiyun #define EFA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff00 60*4882a593Smuzhiyun #define EFA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf0000 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* aq_caps register */ 63*4882a593Smuzhiyun #define EFA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff 64*4882a593Smuzhiyun #define EFA_REGS_AQ_CAPS_AQ_ENTRY_SIZE_MASK 0xffff0000 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* acq_caps register */ 67*4882a593Smuzhiyun #define EFA_REGS_ACQ_CAPS_ACQ_DEPTH_MASK 0xffff 68*4882a593Smuzhiyun #define EFA_REGS_ACQ_CAPS_ACQ_ENTRY_SIZE_MASK 0xff0000 69*4882a593Smuzhiyun #define EFA_REGS_ACQ_CAPS_ACQ_MSIX_VECTOR_MASK 0xff000000 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* aenq_caps register */ 72*4882a593Smuzhiyun #define EFA_REGS_AENQ_CAPS_AENQ_DEPTH_MASK 0xffff 73*4882a593Smuzhiyun #define EFA_REGS_AENQ_CAPS_AENQ_ENTRY_SIZE_MASK 0xff0000 74*4882a593Smuzhiyun #define EFA_REGS_AENQ_CAPS_AENQ_MSIX_VECTOR_MASK 0xff000000 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* intr_mask register */ 77*4882a593Smuzhiyun #define EFA_REGS_INTR_MASK_EN_MASK 0x1 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* dev_ctl register */ 80*4882a593Smuzhiyun #define EFA_REGS_DEV_CTL_DEV_RESET_MASK 0x1 81*4882a593Smuzhiyun #define EFA_REGS_DEV_CTL_AQ_RESTART_MASK 0x2 82*4882a593Smuzhiyun #define EFA_REGS_DEV_CTL_RESET_REASON_MASK 0xf0000000 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* dev_sts register */ 85*4882a593Smuzhiyun #define EFA_REGS_DEV_STS_READY_MASK 0x1 86*4882a593Smuzhiyun #define EFA_REGS_DEV_STS_AQ_RESTART_IN_PROGRESS_MASK 0x2 87*4882a593Smuzhiyun #define EFA_REGS_DEV_STS_AQ_RESTART_FINISHED_MASK 0x4 88*4882a593Smuzhiyun #define EFA_REGS_DEV_STS_RESET_IN_PROGRESS_MASK 0x8 89*4882a593Smuzhiyun #define EFA_REGS_DEV_STS_RESET_FINISHED_MASK 0x10 90*4882a593Smuzhiyun #define EFA_REGS_DEV_STS_FATAL_ERROR_MASK 0x20 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* mmio_reg_read register */ 93*4882a593Smuzhiyun #define EFA_REGS_MMIO_REG_READ_REQ_ID_MASK 0xffff 94*4882a593Smuzhiyun #define EFA_REGS_MMIO_REG_READ_REG_OFF_MASK 0xffff0000 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #endif /* _EFA_REGS_H_ */ 97