1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2018-2020 Amazon.com, Inc. or its affiliates. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _EFA_COM_CMD_H_ 7*4882a593Smuzhiyun #define _EFA_COM_CMD_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "efa_com.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define EFA_GID_SIZE 16 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct efa_com_create_qp_params { 14*4882a593Smuzhiyun u64 rq_base_addr; 15*4882a593Smuzhiyun u32 send_cq_idx; 16*4882a593Smuzhiyun u32 recv_cq_idx; 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * Send descriptor ring size in bytes, 19*4882a593Smuzhiyun * sufficient for user-provided number of WQEs and SGL size 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun u32 sq_ring_size_in_bytes; 22*4882a593Smuzhiyun /* Max number of WQEs that will be posted on send queue */ 23*4882a593Smuzhiyun u32 sq_depth; 24*4882a593Smuzhiyun /* Recv descriptor ring size in bytes */ 25*4882a593Smuzhiyun u32 rq_ring_size_in_bytes; 26*4882a593Smuzhiyun u32 rq_depth; 27*4882a593Smuzhiyun u16 pd; 28*4882a593Smuzhiyun u16 uarn; 29*4882a593Smuzhiyun u8 qp_type; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun struct efa_com_create_qp_result { 33*4882a593Smuzhiyun u32 qp_handle; 34*4882a593Smuzhiyun u32 qp_num; 35*4882a593Smuzhiyun u32 sq_db_offset; 36*4882a593Smuzhiyun u32 rq_db_offset; 37*4882a593Smuzhiyun u32 llq_descriptors_offset; 38*4882a593Smuzhiyun u16 send_sub_cq_idx; 39*4882a593Smuzhiyun u16 recv_sub_cq_idx; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct efa_com_modify_qp_params { 43*4882a593Smuzhiyun u32 modify_mask; 44*4882a593Smuzhiyun u32 qp_handle; 45*4882a593Smuzhiyun u32 qp_state; 46*4882a593Smuzhiyun u32 cur_qp_state; 47*4882a593Smuzhiyun u32 qkey; 48*4882a593Smuzhiyun u32 sq_psn; 49*4882a593Smuzhiyun u8 sq_drained_async_notify; 50*4882a593Smuzhiyun u8 rnr_retry; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct efa_com_query_qp_params { 54*4882a593Smuzhiyun u32 qp_handle; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct efa_com_query_qp_result { 58*4882a593Smuzhiyun u32 qp_state; 59*4882a593Smuzhiyun u32 qkey; 60*4882a593Smuzhiyun u32 sq_draining; 61*4882a593Smuzhiyun u32 sq_psn; 62*4882a593Smuzhiyun u8 rnr_retry; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct efa_com_destroy_qp_params { 66*4882a593Smuzhiyun u32 qp_handle; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun struct efa_com_create_cq_params { 70*4882a593Smuzhiyun /* cq physical base address in OS memory */ 71*4882a593Smuzhiyun dma_addr_t dma_addr; 72*4882a593Smuzhiyun /* completion queue depth in # of entries */ 73*4882a593Smuzhiyun u16 cq_depth; 74*4882a593Smuzhiyun u16 num_sub_cqs; 75*4882a593Smuzhiyun u16 uarn; 76*4882a593Smuzhiyun u8 entry_size_in_bytes; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun struct efa_com_create_cq_result { 80*4882a593Smuzhiyun /* cq identifier */ 81*4882a593Smuzhiyun u16 cq_idx; 82*4882a593Smuzhiyun /* actual cq depth in # of entries */ 83*4882a593Smuzhiyun u16 actual_depth; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun struct efa_com_destroy_cq_params { 87*4882a593Smuzhiyun u16 cq_idx; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun struct efa_com_create_ah_params { 91*4882a593Smuzhiyun u16 pdn; 92*4882a593Smuzhiyun /* Destination address in network byte order */ 93*4882a593Smuzhiyun u8 dest_addr[EFA_GID_SIZE]; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun struct efa_com_create_ah_result { 97*4882a593Smuzhiyun u16 ah; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun struct efa_com_destroy_ah_params { 101*4882a593Smuzhiyun u16 ah; 102*4882a593Smuzhiyun u16 pdn; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun struct efa_com_get_device_attr_result { 106*4882a593Smuzhiyun u8 addr[EFA_GID_SIZE]; 107*4882a593Smuzhiyun u64 page_size_cap; 108*4882a593Smuzhiyun u64 max_mr_pages; 109*4882a593Smuzhiyun u32 mtu; 110*4882a593Smuzhiyun u32 fw_version; 111*4882a593Smuzhiyun u32 admin_api_version; 112*4882a593Smuzhiyun u32 device_version; 113*4882a593Smuzhiyun u32 supported_features; 114*4882a593Smuzhiyun u32 phys_addr_width; 115*4882a593Smuzhiyun u32 virt_addr_width; 116*4882a593Smuzhiyun u32 max_qp; 117*4882a593Smuzhiyun u32 max_sq_depth; /* wqes */ 118*4882a593Smuzhiyun u32 max_rq_depth; /* wqes */ 119*4882a593Smuzhiyun u32 max_cq; 120*4882a593Smuzhiyun u32 max_cq_depth; /* cqes */ 121*4882a593Smuzhiyun u32 inline_buf_size; 122*4882a593Smuzhiyun u32 max_mr; 123*4882a593Smuzhiyun u32 max_pd; 124*4882a593Smuzhiyun u32 max_ah; 125*4882a593Smuzhiyun u32 max_llq_size; 126*4882a593Smuzhiyun u32 max_rdma_size; 127*4882a593Smuzhiyun u32 device_caps; 128*4882a593Smuzhiyun u16 sub_cqs_per_cq; 129*4882a593Smuzhiyun u16 max_sq_sge; 130*4882a593Smuzhiyun u16 max_rq_sge; 131*4882a593Smuzhiyun u16 max_wr_rdma_sge; 132*4882a593Smuzhiyun u16 max_tx_batch; 133*4882a593Smuzhiyun u16 min_sq_depth; 134*4882a593Smuzhiyun u8 db_bar; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun struct efa_com_get_hw_hints_result { 138*4882a593Smuzhiyun u16 mmio_read_timeout; 139*4882a593Smuzhiyun u16 driver_watchdog_timeout; 140*4882a593Smuzhiyun u16 admin_completion_timeout; 141*4882a593Smuzhiyun u16 poll_interval; 142*4882a593Smuzhiyun u32 reserved[4]; 143*4882a593Smuzhiyun }; 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun struct efa_com_mem_addr { 146*4882a593Smuzhiyun u32 mem_addr_low; 147*4882a593Smuzhiyun u32 mem_addr_high; 148*4882a593Smuzhiyun }; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* Used at indirect mode page list chunks for chaining */ 151*4882a593Smuzhiyun struct efa_com_ctrl_buff_info { 152*4882a593Smuzhiyun /* indicates length of the buffer pointed by control_buffer_address. */ 153*4882a593Smuzhiyun u32 length; 154*4882a593Smuzhiyun /* points to control buffer (direct or indirect) */ 155*4882a593Smuzhiyun struct efa_com_mem_addr address; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun struct efa_com_reg_mr_params { 159*4882a593Smuzhiyun /* Memory region length, in bytes. */ 160*4882a593Smuzhiyun u64 mr_length_in_bytes; 161*4882a593Smuzhiyun /* IO Virtual Address associated with this MR. */ 162*4882a593Smuzhiyun u64 iova; 163*4882a593Smuzhiyun /* words 8:15: Physical Buffer List, each element is page-aligned. */ 164*4882a593Smuzhiyun union { 165*4882a593Smuzhiyun /* 166*4882a593Smuzhiyun * Inline array of physical addresses of app pages 167*4882a593Smuzhiyun * (optimization for short region reservations) 168*4882a593Smuzhiyun */ 169*4882a593Smuzhiyun u64 inline_pbl_array[4]; 170*4882a593Smuzhiyun /* 171*4882a593Smuzhiyun * Describes the next physically contiguous chunk of indirect 172*4882a593Smuzhiyun * page list. A page list contains physical addresses of command 173*4882a593Smuzhiyun * data pages. Data pages are 4KB; page list chunks are 174*4882a593Smuzhiyun * variable-sized. 175*4882a593Smuzhiyun */ 176*4882a593Smuzhiyun struct efa_com_ctrl_buff_info pbl; 177*4882a593Smuzhiyun } pbl; 178*4882a593Smuzhiyun /* number of pages in PBL (redundant, could be calculated) */ 179*4882a593Smuzhiyun u32 page_num; 180*4882a593Smuzhiyun /* Protection Domain */ 181*4882a593Smuzhiyun u16 pd; 182*4882a593Smuzhiyun /* 183*4882a593Smuzhiyun * phys_page_size_shift - page size is (1 << phys_page_size_shift) 184*4882a593Smuzhiyun * Page size is used for building the Virtual to Physical 185*4882a593Smuzhiyun * address mapping 186*4882a593Smuzhiyun */ 187*4882a593Smuzhiyun u8 page_shift; 188*4882a593Smuzhiyun /* see permissions field of struct efa_admin_reg_mr_cmd */ 189*4882a593Smuzhiyun u8 permissions; 190*4882a593Smuzhiyun u8 inline_pbl; 191*4882a593Smuzhiyun u8 indirect; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun struct efa_com_reg_mr_result { 195*4882a593Smuzhiyun /* 196*4882a593Smuzhiyun * To be used in conjunction with local buffers references in SQ and 197*4882a593Smuzhiyun * RQ WQE 198*4882a593Smuzhiyun */ 199*4882a593Smuzhiyun u32 l_key; 200*4882a593Smuzhiyun /* 201*4882a593Smuzhiyun * To be used in incoming RDMA semantics messages to refer to remotely 202*4882a593Smuzhiyun * accessed memory region 203*4882a593Smuzhiyun */ 204*4882a593Smuzhiyun u32 r_key; 205*4882a593Smuzhiyun }; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun struct efa_com_dereg_mr_params { 208*4882a593Smuzhiyun u32 l_key; 209*4882a593Smuzhiyun }; 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun struct efa_com_alloc_pd_result { 212*4882a593Smuzhiyun u16 pdn; 213*4882a593Smuzhiyun }; 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun struct efa_com_dealloc_pd_params { 216*4882a593Smuzhiyun u16 pdn; 217*4882a593Smuzhiyun }; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun struct efa_com_alloc_uar_result { 220*4882a593Smuzhiyun u16 uarn; 221*4882a593Smuzhiyun }; 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun struct efa_com_dealloc_uar_params { 224*4882a593Smuzhiyun u16 uarn; 225*4882a593Smuzhiyun }; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun struct efa_com_get_stats_params { 228*4882a593Smuzhiyun /* see enum efa_admin_get_stats_type */ 229*4882a593Smuzhiyun u8 type; 230*4882a593Smuzhiyun /* see enum efa_admin_get_stats_scope */ 231*4882a593Smuzhiyun u8 scope; 232*4882a593Smuzhiyun u16 scope_modifier; 233*4882a593Smuzhiyun }; 234*4882a593Smuzhiyun 235*4882a593Smuzhiyun struct efa_com_basic_stats { 236*4882a593Smuzhiyun u64 tx_bytes; 237*4882a593Smuzhiyun u64 tx_pkts; 238*4882a593Smuzhiyun u64 rx_bytes; 239*4882a593Smuzhiyun u64 rx_pkts; 240*4882a593Smuzhiyun u64 rx_drops; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun struct efa_com_messages_stats { 244*4882a593Smuzhiyun u64 send_bytes; 245*4882a593Smuzhiyun u64 send_wrs; 246*4882a593Smuzhiyun u64 recv_bytes; 247*4882a593Smuzhiyun u64 recv_wrs; 248*4882a593Smuzhiyun }; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun struct efa_com_rdma_read_stats { 251*4882a593Smuzhiyun u64 read_wrs; 252*4882a593Smuzhiyun u64 read_bytes; 253*4882a593Smuzhiyun u64 read_wr_err; 254*4882a593Smuzhiyun u64 read_resp_bytes; 255*4882a593Smuzhiyun }; 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun union efa_com_get_stats_result { 258*4882a593Smuzhiyun struct efa_com_basic_stats basic_stats; 259*4882a593Smuzhiyun struct efa_com_messages_stats messages_stats; 260*4882a593Smuzhiyun struct efa_com_rdma_read_stats rdma_read_stats; 261*4882a593Smuzhiyun }; 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun void efa_com_set_dma_addr(dma_addr_t addr, u32 *addr_high, u32 *addr_low); 264*4882a593Smuzhiyun int efa_com_create_qp(struct efa_com_dev *edev, 265*4882a593Smuzhiyun struct efa_com_create_qp_params *params, 266*4882a593Smuzhiyun struct efa_com_create_qp_result *res); 267*4882a593Smuzhiyun int efa_com_modify_qp(struct efa_com_dev *edev, 268*4882a593Smuzhiyun struct efa_com_modify_qp_params *params); 269*4882a593Smuzhiyun int efa_com_query_qp(struct efa_com_dev *edev, 270*4882a593Smuzhiyun struct efa_com_query_qp_params *params, 271*4882a593Smuzhiyun struct efa_com_query_qp_result *result); 272*4882a593Smuzhiyun int efa_com_destroy_qp(struct efa_com_dev *edev, 273*4882a593Smuzhiyun struct efa_com_destroy_qp_params *params); 274*4882a593Smuzhiyun int efa_com_create_cq(struct efa_com_dev *edev, 275*4882a593Smuzhiyun struct efa_com_create_cq_params *params, 276*4882a593Smuzhiyun struct efa_com_create_cq_result *result); 277*4882a593Smuzhiyun int efa_com_destroy_cq(struct efa_com_dev *edev, 278*4882a593Smuzhiyun struct efa_com_destroy_cq_params *params); 279*4882a593Smuzhiyun int efa_com_register_mr(struct efa_com_dev *edev, 280*4882a593Smuzhiyun struct efa_com_reg_mr_params *params, 281*4882a593Smuzhiyun struct efa_com_reg_mr_result *result); 282*4882a593Smuzhiyun int efa_com_dereg_mr(struct efa_com_dev *edev, 283*4882a593Smuzhiyun struct efa_com_dereg_mr_params *params); 284*4882a593Smuzhiyun int efa_com_create_ah(struct efa_com_dev *edev, 285*4882a593Smuzhiyun struct efa_com_create_ah_params *params, 286*4882a593Smuzhiyun struct efa_com_create_ah_result *result); 287*4882a593Smuzhiyun int efa_com_destroy_ah(struct efa_com_dev *edev, 288*4882a593Smuzhiyun struct efa_com_destroy_ah_params *params); 289*4882a593Smuzhiyun int efa_com_get_device_attr(struct efa_com_dev *edev, 290*4882a593Smuzhiyun struct efa_com_get_device_attr_result *result); 291*4882a593Smuzhiyun int efa_com_get_hw_hints(struct efa_com_dev *edev, 292*4882a593Smuzhiyun struct efa_com_get_hw_hints_result *result); 293*4882a593Smuzhiyun bool 294*4882a593Smuzhiyun efa_com_check_supported_feature_id(struct efa_com_dev *edev, 295*4882a593Smuzhiyun enum efa_admin_aq_feature_id feature_id); 296*4882a593Smuzhiyun int efa_com_set_feature_ex(struct efa_com_dev *edev, 297*4882a593Smuzhiyun struct efa_admin_set_feature_resp *set_resp, 298*4882a593Smuzhiyun struct efa_admin_set_feature_cmd *set_cmd, 299*4882a593Smuzhiyun enum efa_admin_aq_feature_id feature_id, 300*4882a593Smuzhiyun dma_addr_t control_buf_dma_addr, 301*4882a593Smuzhiyun u32 control_buff_size); 302*4882a593Smuzhiyun int efa_com_set_aenq_config(struct efa_com_dev *edev, u32 groups); 303*4882a593Smuzhiyun int efa_com_alloc_pd(struct efa_com_dev *edev, 304*4882a593Smuzhiyun struct efa_com_alloc_pd_result *result); 305*4882a593Smuzhiyun int efa_com_dealloc_pd(struct efa_com_dev *edev, 306*4882a593Smuzhiyun struct efa_com_dealloc_pd_params *params); 307*4882a593Smuzhiyun int efa_com_alloc_uar(struct efa_com_dev *edev, 308*4882a593Smuzhiyun struct efa_com_alloc_uar_result *result); 309*4882a593Smuzhiyun int efa_com_dealloc_uar(struct efa_com_dev *edev, 310*4882a593Smuzhiyun struct efa_com_dealloc_uar_params *params); 311*4882a593Smuzhiyun int efa_com_get_stats(struct efa_com_dev *edev, 312*4882a593Smuzhiyun struct efa_com_get_stats_params *params, 313*4882a593Smuzhiyun union efa_com_get_stats_result *result); 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun #endif /* _EFA_COM_CMD_H_ */ 316