1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2018-2020 Amazon.com, Inc. or its affiliates. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _EFA_COM_H_ 7*4882a593Smuzhiyun #define _EFA_COM_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/delay.h> 10*4882a593Smuzhiyun #include <linux/device.h> 11*4882a593Smuzhiyun #include <linux/dma-mapping.h> 12*4882a593Smuzhiyun #include <linux/semaphore.h> 13*4882a593Smuzhiyun #include <linux/sched.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include <rdma/ib_verbs.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include "efa_common_defs.h" 18*4882a593Smuzhiyun #include "efa_admin_defs.h" 19*4882a593Smuzhiyun #include "efa_admin_cmds_defs.h" 20*4882a593Smuzhiyun #include "efa_regs_defs.h" 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define EFA_MAX_HANDLERS 256 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct efa_com_admin_cq { 25*4882a593Smuzhiyun struct efa_admin_acq_entry *entries; 26*4882a593Smuzhiyun dma_addr_t dma_addr; 27*4882a593Smuzhiyun spinlock_t lock; /* Protects ACQ */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun u16 cc; /* consumer counter */ 30*4882a593Smuzhiyun u8 phase; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct efa_com_admin_sq { 34*4882a593Smuzhiyun struct efa_admin_aq_entry *entries; 35*4882a593Smuzhiyun dma_addr_t dma_addr; 36*4882a593Smuzhiyun spinlock_t lock; /* Protects ASQ */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun u32 __iomem *db_addr; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun u16 cc; /* consumer counter */ 41*4882a593Smuzhiyun u16 pc; /* producer counter */ 42*4882a593Smuzhiyun u8 phase; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Don't use anything other than atomic64 */ 47*4882a593Smuzhiyun struct efa_com_stats_admin { 48*4882a593Smuzhiyun atomic64_t submitted_cmd; 49*4882a593Smuzhiyun atomic64_t completed_cmd; 50*4882a593Smuzhiyun atomic64_t cmd_err; 51*4882a593Smuzhiyun atomic64_t no_completion; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun enum { 55*4882a593Smuzhiyun EFA_AQ_STATE_RUNNING_BIT = 0, 56*4882a593Smuzhiyun EFA_AQ_STATE_POLLING_BIT = 1, 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun struct efa_com_admin_queue { 60*4882a593Smuzhiyun void *dmadev; 61*4882a593Smuzhiyun void *efa_dev; 62*4882a593Smuzhiyun struct efa_comp_ctx *comp_ctx; 63*4882a593Smuzhiyun u32 completion_timeout; /* usecs */ 64*4882a593Smuzhiyun u16 poll_interval; /* msecs */ 65*4882a593Smuzhiyun u16 depth; 66*4882a593Smuzhiyun struct efa_com_admin_cq cq; 67*4882a593Smuzhiyun struct efa_com_admin_sq sq; 68*4882a593Smuzhiyun u16 msix_vector_idx; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun unsigned long state; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Count the number of available admin commands */ 73*4882a593Smuzhiyun struct semaphore avail_cmds; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun struct efa_com_stats_admin stats; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun spinlock_t comp_ctx_lock; /* Protects completion context pool */ 78*4882a593Smuzhiyun u32 *comp_ctx_pool; 79*4882a593Smuzhiyun u16 comp_ctx_pool_next; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun struct efa_aenq_handlers; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun struct efa_com_aenq { 85*4882a593Smuzhiyun struct efa_admin_aenq_entry *entries; 86*4882a593Smuzhiyun struct efa_aenq_handlers *aenq_handlers; 87*4882a593Smuzhiyun dma_addr_t dma_addr; 88*4882a593Smuzhiyun u32 cc; /* consumer counter */ 89*4882a593Smuzhiyun u16 msix_vector_idx; 90*4882a593Smuzhiyun u16 depth; 91*4882a593Smuzhiyun u8 phase; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun struct efa_com_mmio_read { 95*4882a593Smuzhiyun struct efa_admin_mmio_req_read_less_resp *read_resp; 96*4882a593Smuzhiyun dma_addr_t read_resp_dma_addr; 97*4882a593Smuzhiyun u16 seq_num; 98*4882a593Smuzhiyun u16 mmio_read_timeout; /* usecs */ 99*4882a593Smuzhiyun /* serializes mmio reads */ 100*4882a593Smuzhiyun spinlock_t lock; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun struct efa_com_dev { 104*4882a593Smuzhiyun struct efa_com_admin_queue aq; 105*4882a593Smuzhiyun struct efa_com_aenq aenq; 106*4882a593Smuzhiyun u8 __iomem *reg_bar; 107*4882a593Smuzhiyun void *dmadev; 108*4882a593Smuzhiyun void *efa_dev; 109*4882a593Smuzhiyun u32 supported_features; 110*4882a593Smuzhiyun u32 dma_addr_bits; 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun struct efa_com_mmio_read mmio_read; 113*4882a593Smuzhiyun }; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun typedef void (*efa_aenq_handler)(void *data, 116*4882a593Smuzhiyun struct efa_admin_aenq_entry *aenq_e); 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* Holds aenq handlers. Indexed by AENQ event group */ 119*4882a593Smuzhiyun struct efa_aenq_handlers { 120*4882a593Smuzhiyun efa_aenq_handler handlers[EFA_MAX_HANDLERS]; 121*4882a593Smuzhiyun efa_aenq_handler unimplemented_handler; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun int efa_com_admin_init(struct efa_com_dev *edev, 125*4882a593Smuzhiyun struct efa_aenq_handlers *aenq_handlers); 126*4882a593Smuzhiyun void efa_com_admin_destroy(struct efa_com_dev *edev); 127*4882a593Smuzhiyun int efa_com_dev_reset(struct efa_com_dev *edev, 128*4882a593Smuzhiyun enum efa_regs_reset_reason_types reset_reason); 129*4882a593Smuzhiyun void efa_com_set_admin_polling_mode(struct efa_com_dev *edev, bool polling); 130*4882a593Smuzhiyun void efa_com_admin_q_comp_intr_handler(struct efa_com_dev *edev); 131*4882a593Smuzhiyun int efa_com_mmio_reg_read_init(struct efa_com_dev *edev); 132*4882a593Smuzhiyun void efa_com_mmio_reg_read_destroy(struct efa_com_dev *edev); 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun int efa_com_validate_version(struct efa_com_dev *edev); 135*4882a593Smuzhiyun int efa_com_get_dma_width(struct efa_com_dev *edev); 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun int efa_com_cmd_exec(struct efa_com_admin_queue *aq, 138*4882a593Smuzhiyun struct efa_admin_aq_entry *cmd, 139*4882a593Smuzhiyun size_t cmd_size, 140*4882a593Smuzhiyun struct efa_admin_acq_entry *comp, 141*4882a593Smuzhiyun size_t comp_size); 142*4882a593Smuzhiyun void efa_com_aenq_intr_handler(struct efa_com_dev *edev, void *data); 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #endif /* _EFA_COM_H_ */ 145