1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2018-2020 Amazon.com, Inc. or its affiliates. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef _EFA_ADMIN_H_ 7*4882a593Smuzhiyun #define _EFA_ADMIN_H_ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun enum efa_admin_aq_completion_status { 10*4882a593Smuzhiyun EFA_ADMIN_SUCCESS = 0, 11*4882a593Smuzhiyun EFA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, 12*4882a593Smuzhiyun EFA_ADMIN_BAD_OPCODE = 2, 13*4882a593Smuzhiyun EFA_ADMIN_UNSUPPORTED_OPCODE = 3, 14*4882a593Smuzhiyun EFA_ADMIN_MALFORMED_REQUEST = 4, 15*4882a593Smuzhiyun /* Additional status is provided in ACQ entry extended_status */ 16*4882a593Smuzhiyun EFA_ADMIN_ILLEGAL_PARAMETER = 5, 17*4882a593Smuzhiyun EFA_ADMIN_UNKNOWN_ERROR = 6, 18*4882a593Smuzhiyun EFA_ADMIN_RESOURCE_BUSY = 7, 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun struct efa_admin_aq_common_desc { 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * 11:0 : command_id 24*4882a593Smuzhiyun * 15:12 : reserved12 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun u16 command_id; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* as appears in efa_admin_aq_opcode */ 29*4882a593Smuzhiyun u8 opcode; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * 0 : phase 33*4882a593Smuzhiyun * 1 : ctrl_data - control buffer address valid 34*4882a593Smuzhiyun * 2 : ctrl_data_indirect - control buffer address 35*4882a593Smuzhiyun * points to list of pages with addresses of control 36*4882a593Smuzhiyun * buffers 37*4882a593Smuzhiyun * 7:3 : reserved3 38*4882a593Smuzhiyun */ 39*4882a593Smuzhiyun u8 flags; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* 43*4882a593Smuzhiyun * used in efa_admin_aq_entry. Can point directly to control data, or to a 44*4882a593Smuzhiyun * page list chunk. Used also at the end of indirect mode page list chunks, 45*4882a593Smuzhiyun * for chaining. 46*4882a593Smuzhiyun */ 47*4882a593Smuzhiyun struct efa_admin_ctrl_buff_info { 48*4882a593Smuzhiyun u32 length; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun struct efa_common_mem_addr address; 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct efa_admin_aq_entry { 54*4882a593Smuzhiyun struct efa_admin_aq_common_desc aq_common_descriptor; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun union { 57*4882a593Smuzhiyun u32 inline_data_w1[3]; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun struct efa_admin_ctrl_buff_info control_buffer; 60*4882a593Smuzhiyun } u; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun u32 inline_data_w4[12]; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct efa_admin_acq_common_desc { 66*4882a593Smuzhiyun /* 67*4882a593Smuzhiyun * command identifier to associate it with the aq descriptor 68*4882a593Smuzhiyun * 11:0 : command_id 69*4882a593Smuzhiyun * 15:12 : reserved12 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun u16 command; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun u8 status; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* 76*4882a593Smuzhiyun * 0 : phase 77*4882a593Smuzhiyun * 7:1 : reserved1 78*4882a593Smuzhiyun */ 79*4882a593Smuzhiyun u8 flags; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun u16 extended_status; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* 84*4882a593Smuzhiyun * indicates to the driver which AQ entry has been consumed by the 85*4882a593Smuzhiyun * device and could be reused 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun u16 sq_head_indx; 88*4882a593Smuzhiyun }; 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun struct efa_admin_acq_entry { 91*4882a593Smuzhiyun struct efa_admin_acq_common_desc acq_common_descriptor; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun u32 response_specific_data[14]; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun struct efa_admin_aenq_common_desc { 97*4882a593Smuzhiyun u16 group; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun u16 syndrom; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* 102*4882a593Smuzhiyun * 0 : phase 103*4882a593Smuzhiyun * 7:1 : reserved - MBZ 104*4882a593Smuzhiyun */ 105*4882a593Smuzhiyun u8 flags; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun u8 reserved1[3]; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun u32 timestamp_low; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun u32 timestamp_high; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun struct efa_admin_aenq_entry { 115*4882a593Smuzhiyun struct efa_admin_aenq_common_desc aenq_common_desc; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* command specific inline data */ 118*4882a593Smuzhiyun u32 inline_data_w4[12]; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun /* aq_common_desc */ 122*4882a593Smuzhiyun #define EFA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 123*4882a593Smuzhiyun #define EFA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 124*4882a593Smuzhiyun #define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 125*4882a593Smuzhiyun #define EFA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun /* acq_common_desc */ 128*4882a593Smuzhiyun #define EFA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 129*4882a593Smuzhiyun #define EFA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* aenq_common_desc */ 132*4882a593Smuzhiyun #define EFA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #endif /* _EFA_ADMIN_H_ */ 135