1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Broadcom NetXtreme-E RoCE driver.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
5*4882a593Smuzhiyun * Broadcom refers to Broadcom Limited and/or its subsidiaries.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * This software is available to you under a choice of one of two
8*4882a593Smuzhiyun * licenses. You may choose to be licensed under the terms of the GNU
9*4882a593Smuzhiyun * General Public License (GPL) Version 2, available from the file
10*4882a593Smuzhiyun * COPYING in the main directory of this source tree, or the
11*4882a593Smuzhiyun * BSD license below:
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * Redistribution and use in source and binary forms, with or without
14*4882a593Smuzhiyun * modification, are permitted provided that the following conditions
15*4882a593Smuzhiyun * are met:
16*4882a593Smuzhiyun *
17*4882a593Smuzhiyun * 1. Redistributions of source code must retain the above copyright
18*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer.
19*4882a593Smuzhiyun * 2. Redistributions in binary form must reproduce the above copyright
20*4882a593Smuzhiyun * notice, this list of conditions and the following disclaimer in
21*4882a593Smuzhiyun * the documentation and/or other materials provided with the
22*4882a593Smuzhiyun * distribution.
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
25*4882a593Smuzhiyun * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26*4882a593Smuzhiyun * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27*4882a593Smuzhiyun * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
28*4882a593Smuzhiyun * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29*4882a593Smuzhiyun * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30*4882a593Smuzhiyun * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
31*4882a593Smuzhiyun * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32*4882a593Smuzhiyun * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
33*4882a593Smuzhiyun * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
34*4882a593Smuzhiyun * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35*4882a593Smuzhiyun *
36*4882a593Smuzhiyun * Description: Slow Path Operators (header)
37*4882a593Smuzhiyun *
38*4882a593Smuzhiyun */
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #ifndef __BNXT_RE_H__
41*4882a593Smuzhiyun #define __BNXT_RE_H__
42*4882a593Smuzhiyun #define ROCE_DRV_MODULE_NAME "bnxt_re"
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define BNXT_RE_DESC "Broadcom NetXtreme-C/E RoCE Driver"
45*4882a593Smuzhiyun #define BNXT_RE_PAGE_SHIFT_4K (12)
46*4882a593Smuzhiyun #define BNXT_RE_PAGE_SHIFT_8K (13)
47*4882a593Smuzhiyun #define BNXT_RE_PAGE_SHIFT_64K (16)
48*4882a593Smuzhiyun #define BNXT_RE_PAGE_SHIFT_2M (21)
49*4882a593Smuzhiyun #define BNXT_RE_PAGE_SHIFT_8M (23)
50*4882a593Smuzhiyun #define BNXT_RE_PAGE_SHIFT_1G (30)
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define BNXT_RE_PAGE_SIZE_4K BIT(BNXT_RE_PAGE_SHIFT_4K)
53*4882a593Smuzhiyun #define BNXT_RE_PAGE_SIZE_8K BIT(BNXT_RE_PAGE_SHIFT_8K)
54*4882a593Smuzhiyun #define BNXT_RE_PAGE_SIZE_64K BIT(BNXT_RE_PAGE_SHIFT_64K)
55*4882a593Smuzhiyun #define BNXT_RE_PAGE_SIZE_2M BIT(BNXT_RE_PAGE_SHIFT_2M)
56*4882a593Smuzhiyun #define BNXT_RE_PAGE_SIZE_8M BIT(BNXT_RE_PAGE_SHIFT_8M)
57*4882a593Smuzhiyun #define BNXT_RE_PAGE_SIZE_1G BIT(BNXT_RE_PAGE_SHIFT_1G)
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define BNXT_RE_MAX_MR_SIZE_LOW BIT_ULL(BNXT_RE_PAGE_SHIFT_1G)
60*4882a593Smuzhiyun #define BNXT_RE_MAX_MR_SIZE_HIGH BIT_ULL(39)
61*4882a593Smuzhiyun #define BNXT_RE_MAX_MR_SIZE BNXT_RE_MAX_MR_SIZE_HIGH
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #define BNXT_RE_MAX_QPC_COUNT (64 * 1024)
64*4882a593Smuzhiyun #define BNXT_RE_MAX_MRW_COUNT (64 * 1024)
65*4882a593Smuzhiyun #define BNXT_RE_MAX_SRQC_COUNT (64 * 1024)
66*4882a593Smuzhiyun #define BNXT_RE_MAX_CQ_COUNT (64 * 1024)
67*4882a593Smuzhiyun #define BNXT_RE_MAX_MRW_COUNT_64K (64 * 1024)
68*4882a593Smuzhiyun #define BNXT_RE_MAX_MRW_COUNT_256K (256 * 1024)
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* Number of MRs to reserve for PF, leaving remainder for VFs */
71*4882a593Smuzhiyun #define BNXT_RE_RESVD_MR_FOR_PF (32 * 1024)
72*4882a593Smuzhiyun #define BNXT_RE_MAX_GID_PER_VF 128
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /*
75*4882a593Smuzhiyun * Percentage of resources of each type reserved for PF.
76*4882a593Smuzhiyun * Remaining resources are divided equally among VFs.
77*4882a593Smuzhiyun * [0, 100]
78*4882a593Smuzhiyun */
79*4882a593Smuzhiyun #define BNXT_RE_PCT_RSVD_FOR_PF 50
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define BNXT_RE_UD_QP_HW_STALL 0x400000
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun #define BNXT_RE_RQ_WQE_THRESHOLD 32
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun /*
86*4882a593Smuzhiyun * Setting the default ack delay value to 16, which means
87*4882a593Smuzhiyun * the default timeout is approx. 260ms(4 usec * 2 ^(timeout))
88*4882a593Smuzhiyun */
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun #define BNXT_RE_DEFAULT_ACK_DELAY 16
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun struct bnxt_re_ring_attr {
93*4882a593Smuzhiyun dma_addr_t *dma_arr;
94*4882a593Smuzhiyun int pages;
95*4882a593Smuzhiyun int type;
96*4882a593Smuzhiyun u32 depth;
97*4882a593Smuzhiyun u32 lrid; /* Logical ring id */
98*4882a593Smuzhiyun u8 mode;
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun struct bnxt_re_work {
102*4882a593Smuzhiyun struct work_struct work;
103*4882a593Smuzhiyun unsigned long event;
104*4882a593Smuzhiyun struct bnxt_re_dev *rdev;
105*4882a593Smuzhiyun struct net_device *vlan_dev;
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun struct bnxt_re_sqp_entries {
109*4882a593Smuzhiyun struct bnxt_qplib_sge sge;
110*4882a593Smuzhiyun u64 wrid;
111*4882a593Smuzhiyun /* For storing the actual qp1 cqe */
112*4882a593Smuzhiyun struct bnxt_qplib_cqe cqe;
113*4882a593Smuzhiyun struct bnxt_re_qp *qp1_qp;
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun #define BNXT_RE_MAX_GSI_SQP_ENTRIES 1024
117*4882a593Smuzhiyun struct bnxt_re_gsi_context {
118*4882a593Smuzhiyun struct bnxt_re_qp *gsi_qp;
119*4882a593Smuzhiyun struct bnxt_re_qp *gsi_sqp;
120*4882a593Smuzhiyun struct bnxt_re_ah *gsi_sah;
121*4882a593Smuzhiyun struct bnxt_re_sqp_entries *sqp_tbl;
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun #define BNXT_RE_MIN_MSIX 2
125*4882a593Smuzhiyun #define BNXT_RE_MAX_MSIX 9
126*4882a593Smuzhiyun #define BNXT_RE_AEQ_IDX 0
127*4882a593Smuzhiyun #define BNXT_RE_NQ_IDX 1
128*4882a593Smuzhiyun #define BNXT_RE_GEN_P5_MAX_VF 64
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun struct bnxt_re_dev {
131*4882a593Smuzhiyun struct ib_device ibdev;
132*4882a593Smuzhiyun struct list_head list;
133*4882a593Smuzhiyun unsigned long flags;
134*4882a593Smuzhiyun #define BNXT_RE_FLAG_NETDEV_REGISTERED 0
135*4882a593Smuzhiyun #define BNXT_RE_FLAG_GOT_MSIX 2
136*4882a593Smuzhiyun #define BNXT_RE_FLAG_HAVE_L2_REF 3
137*4882a593Smuzhiyun #define BNXT_RE_FLAG_RCFW_CHANNEL_EN 4
138*4882a593Smuzhiyun #define BNXT_RE_FLAG_QOS_WORK_REG 5
139*4882a593Smuzhiyun #define BNXT_RE_FLAG_RESOURCES_ALLOCATED 7
140*4882a593Smuzhiyun #define BNXT_RE_FLAG_RESOURCES_INITIALIZED 8
141*4882a593Smuzhiyun #define BNXT_RE_FLAG_ISSUE_ROCE_STATS 29
142*4882a593Smuzhiyun struct net_device *netdev;
143*4882a593Smuzhiyun unsigned int version, major, minor;
144*4882a593Smuzhiyun struct bnxt_qplib_chip_ctx *chip_ctx;
145*4882a593Smuzhiyun struct bnxt_en_dev *en_dev;
146*4882a593Smuzhiyun struct bnxt_msix_entry msix_entries[BNXT_RE_MAX_MSIX];
147*4882a593Smuzhiyun int num_msix;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun int id;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun struct delayed_work worker;
152*4882a593Smuzhiyun u8 cur_prio_map;
153*4882a593Smuzhiyun u16 active_speed;
154*4882a593Smuzhiyun u8 active_width;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun /* FP Notification Queue (CQ & SRQ) */
157*4882a593Smuzhiyun struct tasklet_struct nq_task;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /* RCFW Channel */
160*4882a593Smuzhiyun struct bnxt_qplib_rcfw rcfw;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /* NQ */
163*4882a593Smuzhiyun struct bnxt_qplib_nq nq[BNXT_RE_MAX_MSIX];
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /* Device Resources */
166*4882a593Smuzhiyun struct bnxt_qplib_dev_attr dev_attr;
167*4882a593Smuzhiyun struct bnxt_qplib_ctx qplib_ctx;
168*4882a593Smuzhiyun struct bnxt_qplib_res qplib_res;
169*4882a593Smuzhiyun struct bnxt_qplib_dpi dpi_privileged;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun atomic_t qp_count;
172*4882a593Smuzhiyun struct mutex qp_lock; /* protect qp list */
173*4882a593Smuzhiyun struct list_head qp_list;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun atomic_t cq_count;
176*4882a593Smuzhiyun atomic_t srq_count;
177*4882a593Smuzhiyun atomic_t mr_count;
178*4882a593Smuzhiyun atomic_t mw_count;
179*4882a593Smuzhiyun /* Max of 2 lossless traffic class supported per port */
180*4882a593Smuzhiyun u16 cosq[2];
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun /* QP for for handling QP1 packets */
183*4882a593Smuzhiyun struct bnxt_re_gsi_context gsi_ctx;
184*4882a593Smuzhiyun atomic_t nq_alloc_cnt;
185*4882a593Smuzhiyun u32 is_virtfn;
186*4882a593Smuzhiyun u32 num_vfs;
187*4882a593Smuzhiyun struct bnxt_qplib_roce_stats stats;
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun #define to_bnxt_re_dev(ptr, member) \
191*4882a593Smuzhiyun container_of((ptr), struct bnxt_re_dev, member)
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun #define BNXT_RE_ROCE_V1_PACKET 0
194*4882a593Smuzhiyun #define BNXT_RE_ROCEV2_IPV4_PACKET 2
195*4882a593Smuzhiyun #define BNXT_RE_ROCEV2_IPV6_PACKET 3
196*4882a593Smuzhiyun
rdev_to_dev(struct bnxt_re_dev * rdev)197*4882a593Smuzhiyun static inline struct device *rdev_to_dev(struct bnxt_re_dev *rdev)
198*4882a593Smuzhiyun {
199*4882a593Smuzhiyun if (rdev)
200*4882a593Smuzhiyun return &rdev->ibdev.dev;
201*4882a593Smuzhiyun return NULL;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun #endif
205