1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /* max31856.c
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Maxim MAX31856 thermocouple sensor driver
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2018-2019 Rockwell Collins
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/ctype.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/spi/spi.h>
14*4882a593Smuzhiyun #include <linux/iio/iio.h>
15*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
16*4882a593Smuzhiyun #include <linux/util_macros.h>
17*4882a593Smuzhiyun #include <asm/unaligned.h>
18*4882a593Smuzhiyun #include <dt-bindings/iio/temperature/thermocouple.h>
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * The MSB of the register value determines whether the following byte will
21*4882a593Smuzhiyun * be written or read. If it is 0, one or more byte reads will follow.
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun #define MAX31856_RD_WR_BIT BIT(7)
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #define MAX31856_CR0_AUTOCONVERT BIT(7)
26*4882a593Smuzhiyun #define MAX31856_CR0_1SHOT BIT(6)
27*4882a593Smuzhiyun #define MAX31856_CR0_OCFAULT BIT(4)
28*4882a593Smuzhiyun #define MAX31856_CR0_OCFAULT_MASK GENMASK(5, 4)
29*4882a593Smuzhiyun #define MAX31856_CR0_FILTER_50HZ BIT(0)
30*4882a593Smuzhiyun #define MAX31856_AVERAGING_MASK GENMASK(6, 4)
31*4882a593Smuzhiyun #define MAX31856_AVERAGING_SHIFT 4
32*4882a593Smuzhiyun #define MAX31856_TC_TYPE_MASK GENMASK(3, 0)
33*4882a593Smuzhiyun #define MAX31856_FAULT_OVUV BIT(1)
34*4882a593Smuzhiyun #define MAX31856_FAULT_OPEN BIT(0)
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /* The MAX31856 registers */
37*4882a593Smuzhiyun #define MAX31856_CR0_REG 0x00
38*4882a593Smuzhiyun #define MAX31856_CR1_REG 0x01
39*4882a593Smuzhiyun #define MAX31856_MASK_REG 0x02
40*4882a593Smuzhiyun #define MAX31856_CJHF_REG 0x03
41*4882a593Smuzhiyun #define MAX31856_CJLF_REG 0x04
42*4882a593Smuzhiyun #define MAX31856_LTHFTH_REG 0x05
43*4882a593Smuzhiyun #define MAX31856_LTHFTL_REG 0x06
44*4882a593Smuzhiyun #define MAX31856_LTLFTH_REG 0x07
45*4882a593Smuzhiyun #define MAX31856_LTLFTL_REG 0x08
46*4882a593Smuzhiyun #define MAX31856_CJTO_REG 0x09
47*4882a593Smuzhiyun #define MAX31856_CJTH_REG 0x0A
48*4882a593Smuzhiyun #define MAX31856_CJTL_REG 0x0B
49*4882a593Smuzhiyun #define MAX31856_LTCBH_REG 0x0C
50*4882a593Smuzhiyun #define MAX31856_LTCBM_REG 0x0D
51*4882a593Smuzhiyun #define MAX31856_LTCBL_REG 0x0E
52*4882a593Smuzhiyun #define MAX31856_SR_REG 0x0F
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun static const struct iio_chan_spec max31856_channels[] = {
55*4882a593Smuzhiyun { /* Thermocouple Temperature */
56*4882a593Smuzhiyun .type = IIO_TEMP,
57*4882a593Smuzhiyun .info_mask_separate =
58*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE) |
59*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_THERMOCOUPLE_TYPE),
60*4882a593Smuzhiyun .info_mask_shared_by_type =
61*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)
62*4882a593Smuzhiyun },
63*4882a593Smuzhiyun { /* Cold Junction Temperature */
64*4882a593Smuzhiyun .type = IIO_TEMP,
65*4882a593Smuzhiyun .channel2 = IIO_MOD_TEMP_AMBIENT,
66*4882a593Smuzhiyun .modified = 1,
67*4882a593Smuzhiyun .info_mask_separate =
68*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
69*4882a593Smuzhiyun .info_mask_shared_by_type =
70*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO)
71*4882a593Smuzhiyun },
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun struct max31856_data {
75*4882a593Smuzhiyun struct spi_device *spi;
76*4882a593Smuzhiyun u32 thermocouple_type;
77*4882a593Smuzhiyun bool filter_50hz;
78*4882a593Smuzhiyun int averaging;
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static const char max31856_tc_types[] = {
82*4882a593Smuzhiyun 'B', 'E', 'J', 'K', 'N', 'R', 'S', 'T'
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun
max31856_read(struct max31856_data * data,u8 reg,u8 val[],unsigned int read_size)85*4882a593Smuzhiyun static int max31856_read(struct max31856_data *data, u8 reg,
86*4882a593Smuzhiyun u8 val[], unsigned int read_size)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun return spi_write_then_read(data->spi, ®, 1, val, read_size);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
max31856_write(struct max31856_data * data,u8 reg,unsigned int val)91*4882a593Smuzhiyun static int max31856_write(struct max31856_data *data, u8 reg,
92*4882a593Smuzhiyun unsigned int val)
93*4882a593Smuzhiyun {
94*4882a593Smuzhiyun u8 buf[2];
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun buf[0] = reg | (MAX31856_RD_WR_BIT);
97*4882a593Smuzhiyun buf[1] = val;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun return spi_write(data->spi, buf, 2);
100*4882a593Smuzhiyun }
101*4882a593Smuzhiyun
max31856_init(struct max31856_data * data)102*4882a593Smuzhiyun static int max31856_init(struct max31856_data *data)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun int ret;
105*4882a593Smuzhiyun u8 reg_cr0_val, reg_cr1_val;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* Start by changing to Off mode before making changes as
108*4882a593Smuzhiyun * some settings are recommended to be set only when the device
109*4882a593Smuzhiyun * is off
110*4882a593Smuzhiyun */
111*4882a593Smuzhiyun ret = max31856_read(data, MAX31856_CR0_REG, ®_cr0_val, 1);
112*4882a593Smuzhiyun if (ret)
113*4882a593Smuzhiyun return ret;
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun reg_cr0_val &= ~MAX31856_CR0_AUTOCONVERT;
116*4882a593Smuzhiyun ret = max31856_write(data, MAX31856_CR0_REG, reg_cr0_val);
117*4882a593Smuzhiyun if (ret)
118*4882a593Smuzhiyun return ret;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* Set thermocouple type based on dts property */
121*4882a593Smuzhiyun ret = max31856_read(data, MAX31856_CR1_REG, ®_cr1_val, 1);
122*4882a593Smuzhiyun if (ret)
123*4882a593Smuzhiyun return ret;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun reg_cr1_val &= ~MAX31856_TC_TYPE_MASK;
126*4882a593Smuzhiyun reg_cr1_val |= data->thermocouple_type;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun reg_cr1_val &= ~MAX31856_AVERAGING_MASK;
129*4882a593Smuzhiyun reg_cr1_val |= data->averaging << MAX31856_AVERAGING_SHIFT;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun ret = max31856_write(data, MAX31856_CR1_REG, reg_cr1_val);
132*4882a593Smuzhiyun if (ret)
133*4882a593Smuzhiyun return ret;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun /*
136*4882a593Smuzhiyun * Enable Open circuit fault detection
137*4882a593Smuzhiyun * Read datasheet for more information: Table 4.
138*4882a593Smuzhiyun * Value 01 means : Enabled (Once every 16 conversions)
139*4882a593Smuzhiyun */
140*4882a593Smuzhiyun reg_cr0_val &= ~MAX31856_CR0_OCFAULT_MASK;
141*4882a593Smuzhiyun reg_cr0_val |= MAX31856_CR0_OCFAULT;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* Set Auto Conversion Mode */
144*4882a593Smuzhiyun reg_cr0_val &= ~MAX31856_CR0_1SHOT;
145*4882a593Smuzhiyun reg_cr0_val |= MAX31856_CR0_AUTOCONVERT;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun if (data->filter_50hz)
148*4882a593Smuzhiyun reg_cr0_val |= MAX31856_CR0_FILTER_50HZ;
149*4882a593Smuzhiyun else
150*4882a593Smuzhiyun reg_cr0_val &= ~MAX31856_CR0_FILTER_50HZ;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun return max31856_write(data, MAX31856_CR0_REG, reg_cr0_val);
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
max31856_thermocouple_read(struct max31856_data * data,struct iio_chan_spec const * chan,int * val)155*4882a593Smuzhiyun static int max31856_thermocouple_read(struct max31856_data *data,
156*4882a593Smuzhiyun struct iio_chan_spec const *chan,
157*4882a593Smuzhiyun int *val)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun int ret, offset_cjto;
160*4882a593Smuzhiyun u8 reg_val[3];
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun switch (chan->channel2) {
163*4882a593Smuzhiyun case IIO_NO_MOD:
164*4882a593Smuzhiyun /*
165*4882a593Smuzhiyun * Multibyte Read
166*4882a593Smuzhiyun * MAX31856_LTCBH_REG, MAX31856_LTCBM_REG, MAX31856_LTCBL_REG
167*4882a593Smuzhiyun */
168*4882a593Smuzhiyun ret = max31856_read(data, MAX31856_LTCBH_REG, reg_val, 3);
169*4882a593Smuzhiyun if (ret)
170*4882a593Smuzhiyun return ret;
171*4882a593Smuzhiyun /* Skip last 5 dead bits of LTCBL */
172*4882a593Smuzhiyun *val = get_unaligned_be24(®_val[0]) >> 5;
173*4882a593Smuzhiyun /* Check 7th bit of LTCBH reg. value for sign*/
174*4882a593Smuzhiyun if (reg_val[0] & 0x80)
175*4882a593Smuzhiyun *val -= 0x80000;
176*4882a593Smuzhiyun break;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun case IIO_MOD_TEMP_AMBIENT:
179*4882a593Smuzhiyun /*
180*4882a593Smuzhiyun * Multibyte Read
181*4882a593Smuzhiyun * MAX31856_CJTO_REG, MAX31856_CJTH_REG, MAX31856_CJTL_REG
182*4882a593Smuzhiyun */
183*4882a593Smuzhiyun ret = max31856_read(data, MAX31856_CJTO_REG, reg_val, 3);
184*4882a593Smuzhiyun if (ret)
185*4882a593Smuzhiyun return ret;
186*4882a593Smuzhiyun /* Get Cold Junction Temp. offset register value */
187*4882a593Smuzhiyun offset_cjto = reg_val[0];
188*4882a593Smuzhiyun /* Get CJTH and CJTL value and skip last 2 dead bits of CJTL */
189*4882a593Smuzhiyun *val = get_unaligned_be16(®_val[1]) >> 2;
190*4882a593Smuzhiyun /* As per datasheet add offset into CJTH and CJTL */
191*4882a593Smuzhiyun *val += offset_cjto;
192*4882a593Smuzhiyun /* Check 7th bit of CJTH reg. value for sign */
193*4882a593Smuzhiyun if (reg_val[1] & 0x80)
194*4882a593Smuzhiyun *val -= 0x4000;
195*4882a593Smuzhiyun break;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun default:
198*4882a593Smuzhiyun return -EINVAL;
199*4882a593Smuzhiyun }
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun ret = max31856_read(data, MAX31856_SR_REG, reg_val, 1);
202*4882a593Smuzhiyun if (ret)
203*4882a593Smuzhiyun return ret;
204*4882a593Smuzhiyun /* Check for over/under voltage or open circuit fault */
205*4882a593Smuzhiyun if (reg_val[0] & (MAX31856_FAULT_OVUV | MAX31856_FAULT_OPEN))
206*4882a593Smuzhiyun return -EIO;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun return ret;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
max31856_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)211*4882a593Smuzhiyun static int max31856_read_raw(struct iio_dev *indio_dev,
212*4882a593Smuzhiyun struct iio_chan_spec const *chan,
213*4882a593Smuzhiyun int *val, int *val2, long mask)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun struct max31856_data *data = iio_priv(indio_dev);
216*4882a593Smuzhiyun int ret;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun switch (mask) {
219*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
220*4882a593Smuzhiyun ret = max31856_thermocouple_read(data, chan, val);
221*4882a593Smuzhiyun if (ret)
222*4882a593Smuzhiyun return ret;
223*4882a593Smuzhiyun return IIO_VAL_INT;
224*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
225*4882a593Smuzhiyun switch (chan->channel2) {
226*4882a593Smuzhiyun case IIO_MOD_TEMP_AMBIENT:
227*4882a593Smuzhiyun /* Cold junction Temp. Data resolution is 0.015625 */
228*4882a593Smuzhiyun *val = 15;
229*4882a593Smuzhiyun *val2 = 625000; /* 1000 * 0.015625 */
230*4882a593Smuzhiyun ret = IIO_VAL_INT_PLUS_MICRO;
231*4882a593Smuzhiyun break;
232*4882a593Smuzhiyun default:
233*4882a593Smuzhiyun /* Thermocouple Temp. Data resolution is 0.0078125 */
234*4882a593Smuzhiyun *val = 7;
235*4882a593Smuzhiyun *val2 = 812500; /* 1000 * 0.0078125) */
236*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
237*4882a593Smuzhiyun }
238*4882a593Smuzhiyun break;
239*4882a593Smuzhiyun case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
240*4882a593Smuzhiyun *val = 1 << data->averaging;
241*4882a593Smuzhiyun return IIO_VAL_INT;
242*4882a593Smuzhiyun case IIO_CHAN_INFO_THERMOCOUPLE_TYPE:
243*4882a593Smuzhiyun *val = max31856_tc_types[data->thermocouple_type];
244*4882a593Smuzhiyun return IIO_VAL_CHAR;
245*4882a593Smuzhiyun default:
246*4882a593Smuzhiyun ret = -EINVAL;
247*4882a593Smuzhiyun break;
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun return ret;
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
max31856_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)253*4882a593Smuzhiyun static int max31856_write_raw_get_fmt(struct iio_dev *indio_dev,
254*4882a593Smuzhiyun struct iio_chan_spec const *chan,
255*4882a593Smuzhiyun long mask)
256*4882a593Smuzhiyun {
257*4882a593Smuzhiyun switch (mask) {
258*4882a593Smuzhiyun case IIO_CHAN_INFO_THERMOCOUPLE_TYPE:
259*4882a593Smuzhiyun return IIO_VAL_CHAR;
260*4882a593Smuzhiyun default:
261*4882a593Smuzhiyun return IIO_VAL_INT;
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun }
264*4882a593Smuzhiyun
max31856_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)265*4882a593Smuzhiyun static int max31856_write_raw(struct iio_dev *indio_dev,
266*4882a593Smuzhiyun struct iio_chan_spec const *chan,
267*4882a593Smuzhiyun int val, int val2, long mask)
268*4882a593Smuzhiyun {
269*4882a593Smuzhiyun struct max31856_data *data = iio_priv(indio_dev);
270*4882a593Smuzhiyun int msb;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun switch (mask) {
273*4882a593Smuzhiyun case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
274*4882a593Smuzhiyun if (val > 16 || val < 1)
275*4882a593Smuzhiyun return -EINVAL;
276*4882a593Smuzhiyun msb = fls(val) - 1;
277*4882a593Smuzhiyun /* Round up to next 2pow if needed */
278*4882a593Smuzhiyun if (BIT(msb) < val)
279*4882a593Smuzhiyun msb++;
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun data->averaging = msb;
282*4882a593Smuzhiyun max31856_init(data);
283*4882a593Smuzhiyun break;
284*4882a593Smuzhiyun case IIO_CHAN_INFO_THERMOCOUPLE_TYPE:
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun int tc_type = -1;
287*4882a593Smuzhiyun int i;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(max31856_tc_types); i++) {
290*4882a593Smuzhiyun if (max31856_tc_types[i] == toupper(val)) {
291*4882a593Smuzhiyun tc_type = i;
292*4882a593Smuzhiyun break;
293*4882a593Smuzhiyun }
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun if (tc_type < 0)
296*4882a593Smuzhiyun return -EINVAL;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun data->thermocouple_type = tc_type;
299*4882a593Smuzhiyun max31856_init(data);
300*4882a593Smuzhiyun break;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun default:
303*4882a593Smuzhiyun return -EINVAL;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun return 0;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun
show_fault(struct device * dev,u8 faultbit,char * buf)309*4882a593Smuzhiyun static ssize_t show_fault(struct device *dev, u8 faultbit, char *buf)
310*4882a593Smuzhiyun {
311*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_to_iio_dev(dev);
312*4882a593Smuzhiyun struct max31856_data *data = iio_priv(indio_dev);
313*4882a593Smuzhiyun u8 reg_val;
314*4882a593Smuzhiyun int ret;
315*4882a593Smuzhiyun bool fault;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun ret = max31856_read(data, MAX31856_SR_REG, ®_val, 1);
318*4882a593Smuzhiyun if (ret)
319*4882a593Smuzhiyun return ret;
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun fault = reg_val & faultbit;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun return sprintf(buf, "%d\n", fault);
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
show_fault_ovuv(struct device * dev,struct device_attribute * attr,char * buf)326*4882a593Smuzhiyun static ssize_t show_fault_ovuv(struct device *dev,
327*4882a593Smuzhiyun struct device_attribute *attr,
328*4882a593Smuzhiyun char *buf)
329*4882a593Smuzhiyun {
330*4882a593Smuzhiyun return show_fault(dev, MAX31856_FAULT_OVUV, buf);
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun
show_fault_oc(struct device * dev,struct device_attribute * attr,char * buf)333*4882a593Smuzhiyun static ssize_t show_fault_oc(struct device *dev,
334*4882a593Smuzhiyun struct device_attribute *attr,
335*4882a593Smuzhiyun char *buf)
336*4882a593Smuzhiyun {
337*4882a593Smuzhiyun return show_fault(dev, MAX31856_FAULT_OPEN, buf);
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun
show_filter(struct device * dev,struct device_attribute * attr,char * buf)340*4882a593Smuzhiyun static ssize_t show_filter(struct device *dev,
341*4882a593Smuzhiyun struct device_attribute *attr,
342*4882a593Smuzhiyun char *buf)
343*4882a593Smuzhiyun {
344*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_to_iio_dev(dev);
345*4882a593Smuzhiyun struct max31856_data *data = iio_priv(indio_dev);
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun return sprintf(buf, "%d\n", data->filter_50hz ? 50 : 60);
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun
set_filter(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)350*4882a593Smuzhiyun static ssize_t set_filter(struct device *dev,
351*4882a593Smuzhiyun struct device_attribute *attr,
352*4882a593Smuzhiyun const char *buf,
353*4882a593Smuzhiyun size_t len)
354*4882a593Smuzhiyun {
355*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_to_iio_dev(dev);
356*4882a593Smuzhiyun struct max31856_data *data = iio_priv(indio_dev);
357*4882a593Smuzhiyun unsigned int freq;
358*4882a593Smuzhiyun int ret;
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun ret = kstrtouint(buf, 10, &freq);
361*4882a593Smuzhiyun if (ret)
362*4882a593Smuzhiyun return ret;
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun switch (freq) {
365*4882a593Smuzhiyun case 50:
366*4882a593Smuzhiyun data->filter_50hz = true;
367*4882a593Smuzhiyun break;
368*4882a593Smuzhiyun case 60:
369*4882a593Smuzhiyun data->filter_50hz = false;
370*4882a593Smuzhiyun break;
371*4882a593Smuzhiyun default:
372*4882a593Smuzhiyun return -EINVAL;
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun max31856_init(data);
376*4882a593Smuzhiyun return len;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun static IIO_DEVICE_ATTR(fault_ovuv, 0444, show_fault_ovuv, NULL, 0);
380*4882a593Smuzhiyun static IIO_DEVICE_ATTR(fault_oc, 0444, show_fault_oc, NULL, 0);
381*4882a593Smuzhiyun static IIO_DEVICE_ATTR(in_temp_filter_notch_center_frequency, 0644,
382*4882a593Smuzhiyun show_filter, set_filter, 0);
383*4882a593Smuzhiyun
384*4882a593Smuzhiyun static struct attribute *max31856_attributes[] = {
385*4882a593Smuzhiyun &iio_dev_attr_fault_ovuv.dev_attr.attr,
386*4882a593Smuzhiyun &iio_dev_attr_fault_oc.dev_attr.attr,
387*4882a593Smuzhiyun &iio_dev_attr_in_temp_filter_notch_center_frequency.dev_attr.attr,
388*4882a593Smuzhiyun NULL,
389*4882a593Smuzhiyun };
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun static const struct attribute_group max31856_group = {
392*4882a593Smuzhiyun .attrs = max31856_attributes,
393*4882a593Smuzhiyun };
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun static const struct iio_info max31856_info = {
396*4882a593Smuzhiyun .read_raw = max31856_read_raw,
397*4882a593Smuzhiyun .write_raw = max31856_write_raw,
398*4882a593Smuzhiyun .write_raw_get_fmt = max31856_write_raw_get_fmt,
399*4882a593Smuzhiyun .attrs = &max31856_group,
400*4882a593Smuzhiyun };
401*4882a593Smuzhiyun
max31856_probe(struct spi_device * spi)402*4882a593Smuzhiyun static int max31856_probe(struct spi_device *spi)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun const struct spi_device_id *id = spi_get_device_id(spi);
405*4882a593Smuzhiyun struct iio_dev *indio_dev;
406*4882a593Smuzhiyun struct max31856_data *data;
407*4882a593Smuzhiyun int ret;
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*data));
410*4882a593Smuzhiyun if (!indio_dev)
411*4882a593Smuzhiyun return -ENOMEM;
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun data = iio_priv(indio_dev);
414*4882a593Smuzhiyun data->spi = spi;
415*4882a593Smuzhiyun data->filter_50hz = false;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun spi_set_drvdata(spi, indio_dev);
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun indio_dev->info = &max31856_info;
420*4882a593Smuzhiyun indio_dev->name = id->name;
421*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
422*4882a593Smuzhiyun indio_dev->channels = max31856_channels;
423*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(max31856_channels);
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun ret = of_property_read_u32(spi->dev.of_node, "thermocouple-type",
426*4882a593Smuzhiyun &data->thermocouple_type);
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun if (ret) {
429*4882a593Smuzhiyun dev_info(&spi->dev,
430*4882a593Smuzhiyun "Could not read thermocouple type DT property, configuring as a K-Type\n");
431*4882a593Smuzhiyun data->thermocouple_type = THERMOCOUPLE_TYPE_K;
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun /*
435*4882a593Smuzhiyun * no need to translate values as the supported types
436*4882a593Smuzhiyun * have the same value as the #defines
437*4882a593Smuzhiyun */
438*4882a593Smuzhiyun switch (data->thermocouple_type) {
439*4882a593Smuzhiyun case THERMOCOUPLE_TYPE_B:
440*4882a593Smuzhiyun case THERMOCOUPLE_TYPE_E:
441*4882a593Smuzhiyun case THERMOCOUPLE_TYPE_J:
442*4882a593Smuzhiyun case THERMOCOUPLE_TYPE_K:
443*4882a593Smuzhiyun case THERMOCOUPLE_TYPE_N:
444*4882a593Smuzhiyun case THERMOCOUPLE_TYPE_R:
445*4882a593Smuzhiyun case THERMOCOUPLE_TYPE_S:
446*4882a593Smuzhiyun case THERMOCOUPLE_TYPE_T:
447*4882a593Smuzhiyun break;
448*4882a593Smuzhiyun default:
449*4882a593Smuzhiyun dev_err(&spi->dev,
450*4882a593Smuzhiyun "error: thermocouple-type %u not supported by max31856\n"
451*4882a593Smuzhiyun , data->thermocouple_type);
452*4882a593Smuzhiyun return -EINVAL;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun ret = max31856_init(data);
456*4882a593Smuzhiyun if (ret) {
457*4882a593Smuzhiyun dev_err(&spi->dev, "error: Failed to configure max31856\n");
458*4882a593Smuzhiyun return ret;
459*4882a593Smuzhiyun }
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun return devm_iio_device_register(&spi->dev, indio_dev);
462*4882a593Smuzhiyun }
463*4882a593Smuzhiyun
464*4882a593Smuzhiyun static const struct spi_device_id max31856_id[] = {
465*4882a593Smuzhiyun { "max31856", 0 },
466*4882a593Smuzhiyun { }
467*4882a593Smuzhiyun };
468*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, max31856_id);
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun static const struct of_device_id max31856_of_match[] = {
471*4882a593Smuzhiyun { .compatible = "maxim,max31856" },
472*4882a593Smuzhiyun { }
473*4882a593Smuzhiyun };
474*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, max31856_of_match);
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun static struct spi_driver max31856_driver = {
477*4882a593Smuzhiyun .driver = {
478*4882a593Smuzhiyun .name = "max31856",
479*4882a593Smuzhiyun .of_match_table = max31856_of_match,
480*4882a593Smuzhiyun },
481*4882a593Smuzhiyun .probe = max31856_probe,
482*4882a593Smuzhiyun .id_table = max31856_id,
483*4882a593Smuzhiyun };
484*4882a593Smuzhiyun module_spi_driver(max31856_driver);
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun MODULE_AUTHOR("Paresh Chaudhary <paresh.chaudhary@rockwellcollins.com>");
487*4882a593Smuzhiyun MODULE_AUTHOR("Patrick Havelange <patrick.havelange@essensium.com>");
488*4882a593Smuzhiyun MODULE_DESCRIPTION("Maxim MAX31856 thermocouple sensor driver");
489*4882a593Smuzhiyun MODULE_LICENSE("GPL");
490