1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ad2s90.c simple support for the ADI Resolver to Digital Converters: AD2S90
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2010-2010 Analog Devices Inc.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/types.h>
8*4882a593Smuzhiyun #include <linux/mutex.h>
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/spi/spi.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <linux/sysfs.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/iio/iio.h>
16*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /*
19*4882a593Smuzhiyun * Although chip's max frequency is 2Mhz, it needs 600ns between CS and the
20*4882a593Smuzhiyun * first falling edge of SCLK, so frequency should be at most 1 / (2 * 6e-7)
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun #define AD2S90_MAX_SPI_FREQ_HZ 830000
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct ad2s90_state {
25*4882a593Smuzhiyun struct mutex lock; /* lock to protect rx buffer */
26*4882a593Smuzhiyun struct spi_device *sdev;
27*4882a593Smuzhiyun u8 rx[2] ____cacheline_aligned;
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
ad2s90_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)30*4882a593Smuzhiyun static int ad2s90_read_raw(struct iio_dev *indio_dev,
31*4882a593Smuzhiyun struct iio_chan_spec const *chan,
32*4882a593Smuzhiyun int *val,
33*4882a593Smuzhiyun int *val2,
34*4882a593Smuzhiyun long m)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun int ret;
37*4882a593Smuzhiyun struct ad2s90_state *st = iio_priv(indio_dev);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun if (chan->type != IIO_ANGL)
40*4882a593Smuzhiyun return -EINVAL;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun switch (m) {
43*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
44*4882a593Smuzhiyun /* 2 * Pi / 2^12 */
45*4882a593Smuzhiyun *val = 6283; /* mV */
46*4882a593Smuzhiyun *val2 = 12;
47*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL_LOG2;
48*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
49*4882a593Smuzhiyun mutex_lock(&st->lock);
50*4882a593Smuzhiyun ret = spi_read(st->sdev, st->rx, 2);
51*4882a593Smuzhiyun if (ret < 0) {
52*4882a593Smuzhiyun mutex_unlock(&st->lock);
53*4882a593Smuzhiyun return ret;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun *val = (((u16)(st->rx[0])) << 4) | ((st->rx[1] & 0xF0) >> 4);
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun mutex_unlock(&st->lock);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun return IIO_VAL_INT;
60*4882a593Smuzhiyun default:
61*4882a593Smuzhiyun break;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return -EINVAL;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static const struct iio_info ad2s90_info = {
68*4882a593Smuzhiyun .read_raw = ad2s90_read_raw,
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun static const struct iio_chan_spec ad2s90_chan = {
72*4882a593Smuzhiyun .type = IIO_ANGL,
73*4882a593Smuzhiyun .indexed = 1,
74*4882a593Smuzhiyun .channel = 0,
75*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
ad2s90_probe(struct spi_device * spi)78*4882a593Smuzhiyun static int ad2s90_probe(struct spi_device *spi)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun struct iio_dev *indio_dev;
81*4882a593Smuzhiyun struct ad2s90_state *st;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun if (spi->max_speed_hz > AD2S90_MAX_SPI_FREQ_HZ) {
84*4882a593Smuzhiyun dev_err(&spi->dev, "SPI CLK, %d Hz exceeds %d Hz\n",
85*4882a593Smuzhiyun spi->max_speed_hz, AD2S90_MAX_SPI_FREQ_HZ);
86*4882a593Smuzhiyun return -EINVAL;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
90*4882a593Smuzhiyun if (!indio_dev)
91*4882a593Smuzhiyun return -ENOMEM;
92*4882a593Smuzhiyun st = iio_priv(indio_dev);
93*4882a593Smuzhiyun spi_set_drvdata(spi, indio_dev);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun mutex_init(&st->lock);
96*4882a593Smuzhiyun st->sdev = spi;
97*4882a593Smuzhiyun indio_dev->info = &ad2s90_info;
98*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
99*4882a593Smuzhiyun indio_dev->channels = &ad2s90_chan;
100*4882a593Smuzhiyun indio_dev->num_channels = 1;
101*4882a593Smuzhiyun indio_dev->name = spi_get_device_id(spi)->name;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun return devm_iio_device_register(indio_dev->dev.parent, indio_dev);
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun static const struct of_device_id ad2s90_of_match[] = {
107*4882a593Smuzhiyun { .compatible = "adi,ad2s90", },
108*4882a593Smuzhiyun {}
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ad2s90_of_match);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun static const struct spi_device_id ad2s90_id[] = {
113*4882a593Smuzhiyun { "ad2s90" },
114*4882a593Smuzhiyun {}
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ad2s90_id);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun static struct spi_driver ad2s90_driver = {
119*4882a593Smuzhiyun .driver = {
120*4882a593Smuzhiyun .name = "ad2s90",
121*4882a593Smuzhiyun .of_match_table = ad2s90_of_match,
122*4882a593Smuzhiyun },
123*4882a593Smuzhiyun .probe = ad2s90_probe,
124*4882a593Smuzhiyun .id_table = ad2s90_id,
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun module_spi_driver(ad2s90_driver);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun MODULE_AUTHOR("Graff Yang <graff.yang@gmail.com>");
129*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD2S90 Resolver to Digital SPI driver");
130*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
131