1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ad2s1200.c simple support for the ADI Resolver to Digital Converters:
4*4882a593Smuzhiyun * AD2S1200/1205
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (c) 2018-2018 David Veenstra <davidjulianveenstra@gmail.com>
7*4882a593Smuzhiyun * Copyright (c) 2010-2010 Analog Devices Inc.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/bitops.h>
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/device.h>
13*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
16*4882a593Smuzhiyun #include <linux/mutex.h>
17*4882a593Smuzhiyun #include <linux/spi/spi.h>
18*4882a593Smuzhiyun #include <linux/sysfs.h>
19*4882a593Smuzhiyun #include <linux/types.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <linux/iio/iio.h>
22*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define DRV_NAME "ad2s1200"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* input clock on serial interface */
27*4882a593Smuzhiyun #define AD2S1200_HZ 8192000
28*4882a593Smuzhiyun /* clock period in nano second */
29*4882a593Smuzhiyun #define AD2S1200_TSCLK (1000000000 / AD2S1200_HZ)
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /**
32*4882a593Smuzhiyun * struct ad2s1200_state - driver instance specific data.
33*4882a593Smuzhiyun * @lock: protects both the GPIO pins and the rx buffer.
34*4882a593Smuzhiyun * @sdev: spi device.
35*4882a593Smuzhiyun * @sample: GPIO pin SAMPLE.
36*4882a593Smuzhiyun * @rdvel: GPIO pin RDVEL.
37*4882a593Smuzhiyun * @rx: buffer for spi transfers.
38*4882a593Smuzhiyun */
39*4882a593Smuzhiyun struct ad2s1200_state {
40*4882a593Smuzhiyun struct mutex lock;
41*4882a593Smuzhiyun struct spi_device *sdev;
42*4882a593Smuzhiyun struct gpio_desc *sample;
43*4882a593Smuzhiyun struct gpio_desc *rdvel;
44*4882a593Smuzhiyun __be16 rx ____cacheline_aligned;
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
ad2s1200_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)47*4882a593Smuzhiyun static int ad2s1200_read_raw(struct iio_dev *indio_dev,
48*4882a593Smuzhiyun struct iio_chan_spec const *chan,
49*4882a593Smuzhiyun int *val,
50*4882a593Smuzhiyun int *val2,
51*4882a593Smuzhiyun long m)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun struct ad2s1200_state *st = iio_priv(indio_dev);
54*4882a593Smuzhiyun int ret;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun switch (m) {
57*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
58*4882a593Smuzhiyun switch (chan->type) {
59*4882a593Smuzhiyun case IIO_ANGL:
60*4882a593Smuzhiyun /* 2 * Pi / (2^12 - 1) ~= 0.001534355 */
61*4882a593Smuzhiyun *val = 0;
62*4882a593Smuzhiyun *val2 = 1534355;
63*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_NANO;
64*4882a593Smuzhiyun case IIO_ANGL_VEL:
65*4882a593Smuzhiyun /* 2 * Pi ~= 6.283185 */
66*4882a593Smuzhiyun *val = 6;
67*4882a593Smuzhiyun *val2 = 283185;
68*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
69*4882a593Smuzhiyun default:
70*4882a593Smuzhiyun return -EINVAL;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun break;
73*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
74*4882a593Smuzhiyun mutex_lock(&st->lock);
75*4882a593Smuzhiyun gpiod_set_value(st->sample, 0);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* delay (6 * AD2S1200_TSCLK + 20) nano seconds */
78*4882a593Smuzhiyun udelay(1);
79*4882a593Smuzhiyun gpiod_set_value(st->sample, 1);
80*4882a593Smuzhiyun gpiod_set_value(st->rdvel, !!(chan->type == IIO_ANGL));
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun ret = spi_read(st->sdev, &st->rx, 2);
83*4882a593Smuzhiyun if (ret < 0) {
84*4882a593Smuzhiyun mutex_unlock(&st->lock);
85*4882a593Smuzhiyun return ret;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun switch (chan->type) {
89*4882a593Smuzhiyun case IIO_ANGL:
90*4882a593Smuzhiyun *val = be16_to_cpup(&st->rx) >> 4;
91*4882a593Smuzhiyun break;
92*4882a593Smuzhiyun case IIO_ANGL_VEL:
93*4882a593Smuzhiyun *val = sign_extend32(be16_to_cpup(&st->rx) >> 4, 11);
94*4882a593Smuzhiyun break;
95*4882a593Smuzhiyun default:
96*4882a593Smuzhiyun mutex_unlock(&st->lock);
97*4882a593Smuzhiyun return -EINVAL;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* delay (2 * AD2S1200_TSCLK + 20) ns for sample pulse */
101*4882a593Smuzhiyun udelay(1);
102*4882a593Smuzhiyun mutex_unlock(&st->lock);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun return IIO_VAL_INT;
105*4882a593Smuzhiyun default:
106*4882a593Smuzhiyun break;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun return -EINVAL;
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun static const struct iio_chan_spec ad2s1200_channels[] = {
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun .type = IIO_ANGL,
115*4882a593Smuzhiyun .indexed = 1,
116*4882a593Smuzhiyun .channel = 0,
117*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
118*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
119*4882a593Smuzhiyun }, {
120*4882a593Smuzhiyun .type = IIO_ANGL_VEL,
121*4882a593Smuzhiyun .indexed = 1,
122*4882a593Smuzhiyun .channel = 0,
123*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
124*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun static const struct iio_info ad2s1200_info = {
129*4882a593Smuzhiyun .read_raw = ad2s1200_read_raw,
130*4882a593Smuzhiyun };
131*4882a593Smuzhiyun
ad2s1200_probe(struct spi_device * spi)132*4882a593Smuzhiyun static int ad2s1200_probe(struct spi_device *spi)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun struct ad2s1200_state *st;
135*4882a593Smuzhiyun struct iio_dev *indio_dev;
136*4882a593Smuzhiyun int ret;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
139*4882a593Smuzhiyun if (!indio_dev)
140*4882a593Smuzhiyun return -ENOMEM;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun spi_set_drvdata(spi, indio_dev);
143*4882a593Smuzhiyun st = iio_priv(indio_dev);
144*4882a593Smuzhiyun mutex_init(&st->lock);
145*4882a593Smuzhiyun st->sdev = spi;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun st->sample = devm_gpiod_get(&spi->dev, "adi,sample", GPIOD_OUT_LOW);
148*4882a593Smuzhiyun if (IS_ERR(st->sample)) {
149*4882a593Smuzhiyun dev_err(&spi->dev, "Failed to claim SAMPLE gpio: err=%ld\n",
150*4882a593Smuzhiyun PTR_ERR(st->sample));
151*4882a593Smuzhiyun return PTR_ERR(st->sample);
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun st->rdvel = devm_gpiod_get(&spi->dev, "adi,rdvel", GPIOD_OUT_LOW);
155*4882a593Smuzhiyun if (IS_ERR(st->rdvel)) {
156*4882a593Smuzhiyun dev_err(&spi->dev, "Failed to claim RDVEL gpio: err=%ld\n",
157*4882a593Smuzhiyun PTR_ERR(st->rdvel));
158*4882a593Smuzhiyun return PTR_ERR(st->rdvel);
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun indio_dev->info = &ad2s1200_info;
162*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
163*4882a593Smuzhiyun indio_dev->channels = ad2s1200_channels;
164*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(ad2s1200_channels);
165*4882a593Smuzhiyun indio_dev->name = spi_get_device_id(spi)->name;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun spi->max_speed_hz = AD2S1200_HZ;
168*4882a593Smuzhiyun spi->mode = SPI_MODE_3;
169*4882a593Smuzhiyun ret = spi_setup(spi);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun if (ret < 0) {
172*4882a593Smuzhiyun dev_err(&spi->dev, "spi_setup failed!\n");
173*4882a593Smuzhiyun return ret;
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun return devm_iio_device_register(&spi->dev, indio_dev);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun static const struct of_device_id ad2s1200_of_match[] = {
180*4882a593Smuzhiyun { .compatible = "adi,ad2s1200", },
181*4882a593Smuzhiyun { .compatible = "adi,ad2s1205", },
182*4882a593Smuzhiyun { }
183*4882a593Smuzhiyun };
184*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ad2s1200_of_match);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun static const struct spi_device_id ad2s1200_id[] = {
187*4882a593Smuzhiyun { "ad2s1200" },
188*4882a593Smuzhiyun { "ad2s1205" },
189*4882a593Smuzhiyun {}
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, ad2s1200_id);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun static struct spi_driver ad2s1200_driver = {
194*4882a593Smuzhiyun .driver = {
195*4882a593Smuzhiyun .name = DRV_NAME,
196*4882a593Smuzhiyun .of_match_table = ad2s1200_of_match,
197*4882a593Smuzhiyun },
198*4882a593Smuzhiyun .probe = ad2s1200_probe,
199*4882a593Smuzhiyun .id_table = ad2s1200_id,
200*4882a593Smuzhiyun };
201*4882a593Smuzhiyun module_spi_driver(ad2s1200_driver);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun MODULE_AUTHOR("David Veenstra <davidjulianveenstra@gmail.com>");
204*4882a593Smuzhiyun MODULE_AUTHOR("Graff Yang <graff.yang@gmail.com>");
205*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices AD2S1200/1205 Resolver to Digital SPI driver");
206*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
207