1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2014 Intel Corporation
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Driver for Semtech's SX9500 capacitive proximity/button solution.
6*4882a593Smuzhiyun * Datasheet available at
7*4882a593Smuzhiyun * <http://www.semtech.com/images/datasheet/sx9500.pdf>.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/slab.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/irq.h>
15*4882a593Smuzhiyun #include <linux/acpi.h>
16*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
17*4882a593Smuzhiyun #include <linux/regmap.h>
18*4882a593Smuzhiyun #include <linux/pm.h>
19*4882a593Smuzhiyun #include <linux/delay.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #include <linux/iio/iio.h>
22*4882a593Smuzhiyun #include <linux/iio/buffer.h>
23*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
24*4882a593Smuzhiyun #include <linux/iio/events.h>
25*4882a593Smuzhiyun #include <linux/iio/trigger.h>
26*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
27*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define SX9500_DRIVER_NAME "sx9500"
30*4882a593Smuzhiyun #define SX9500_IRQ_NAME "sx9500_event"
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* Register definitions. */
33*4882a593Smuzhiyun #define SX9500_REG_IRQ_SRC 0x00
34*4882a593Smuzhiyun #define SX9500_REG_STAT 0x01
35*4882a593Smuzhiyun #define SX9500_REG_IRQ_MSK 0x03
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define SX9500_REG_PROX_CTRL0 0x06
38*4882a593Smuzhiyun #define SX9500_REG_PROX_CTRL1 0x07
39*4882a593Smuzhiyun #define SX9500_REG_PROX_CTRL2 0x08
40*4882a593Smuzhiyun #define SX9500_REG_PROX_CTRL3 0x09
41*4882a593Smuzhiyun #define SX9500_REG_PROX_CTRL4 0x0a
42*4882a593Smuzhiyun #define SX9500_REG_PROX_CTRL5 0x0b
43*4882a593Smuzhiyun #define SX9500_REG_PROX_CTRL6 0x0c
44*4882a593Smuzhiyun #define SX9500_REG_PROX_CTRL7 0x0d
45*4882a593Smuzhiyun #define SX9500_REG_PROX_CTRL8 0x0e
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun #define SX9500_REG_SENSOR_SEL 0x20
48*4882a593Smuzhiyun #define SX9500_REG_USE_MSB 0x21
49*4882a593Smuzhiyun #define SX9500_REG_USE_LSB 0x22
50*4882a593Smuzhiyun #define SX9500_REG_AVG_MSB 0x23
51*4882a593Smuzhiyun #define SX9500_REG_AVG_LSB 0x24
52*4882a593Smuzhiyun #define SX9500_REG_DIFF_MSB 0x25
53*4882a593Smuzhiyun #define SX9500_REG_DIFF_LSB 0x26
54*4882a593Smuzhiyun #define SX9500_REG_OFFSET_MSB 0x27
55*4882a593Smuzhiyun #define SX9500_REG_OFFSET_LSB 0x28
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun #define SX9500_REG_RESET 0x7f
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Write this to REG_RESET to do a soft reset. */
60*4882a593Smuzhiyun #define SX9500_SOFT_RESET 0xde
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #define SX9500_SCAN_PERIOD_MASK GENMASK(6, 4)
63*4882a593Smuzhiyun #define SX9500_SCAN_PERIOD_SHIFT 4
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /*
66*4882a593Smuzhiyun * These serve for identifying IRQ source in the IRQ_SRC register, and
67*4882a593Smuzhiyun * also for masking the IRQs in the IRQ_MSK register.
68*4882a593Smuzhiyun */
69*4882a593Smuzhiyun #define SX9500_CLOSE_IRQ BIT(6)
70*4882a593Smuzhiyun #define SX9500_FAR_IRQ BIT(5)
71*4882a593Smuzhiyun #define SX9500_CONVDONE_IRQ BIT(3)
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #define SX9500_PROXSTAT_SHIFT 4
74*4882a593Smuzhiyun #define SX9500_COMPSTAT_MASK GENMASK(3, 0)
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define SX9500_NUM_CHANNELS 4
77*4882a593Smuzhiyun #define SX9500_CHAN_MASK GENMASK(SX9500_NUM_CHANNELS - 1, 0)
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun struct sx9500_data {
80*4882a593Smuzhiyun struct mutex mutex;
81*4882a593Smuzhiyun struct i2c_client *client;
82*4882a593Smuzhiyun struct iio_trigger *trig;
83*4882a593Smuzhiyun struct regmap *regmap;
84*4882a593Smuzhiyun struct gpio_desc *gpiod_rst;
85*4882a593Smuzhiyun /*
86*4882a593Smuzhiyun * Last reading of the proximity status for each channel. We
87*4882a593Smuzhiyun * only send an event to user space when this changes.
88*4882a593Smuzhiyun */
89*4882a593Smuzhiyun bool prox_stat[SX9500_NUM_CHANNELS];
90*4882a593Smuzhiyun bool event_enabled[SX9500_NUM_CHANNELS];
91*4882a593Smuzhiyun bool trigger_enabled;
92*4882a593Smuzhiyun u16 *buffer;
93*4882a593Smuzhiyun /* Remember enabled channels and sample rate during suspend. */
94*4882a593Smuzhiyun unsigned int suspend_ctrl0;
95*4882a593Smuzhiyun struct completion completion;
96*4882a593Smuzhiyun int data_rdy_users, close_far_users;
97*4882a593Smuzhiyun int channel_users[SX9500_NUM_CHANNELS];
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static const struct iio_event_spec sx9500_events[] = {
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
103*4882a593Smuzhiyun .dir = IIO_EV_DIR_EITHER,
104*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_ENABLE),
105*4882a593Smuzhiyun },
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun #define SX9500_CHANNEL(idx) \
109*4882a593Smuzhiyun { \
110*4882a593Smuzhiyun .type = IIO_PROXIMITY, \
111*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
112*4882a593Smuzhiyun .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
113*4882a593Smuzhiyun .indexed = 1, \
114*4882a593Smuzhiyun .channel = idx, \
115*4882a593Smuzhiyun .event_spec = sx9500_events, \
116*4882a593Smuzhiyun .num_event_specs = ARRAY_SIZE(sx9500_events), \
117*4882a593Smuzhiyun .scan_index = idx, \
118*4882a593Smuzhiyun .scan_type = { \
119*4882a593Smuzhiyun .sign = 'u', \
120*4882a593Smuzhiyun .realbits = 16, \
121*4882a593Smuzhiyun .storagebits = 16, \
122*4882a593Smuzhiyun .shift = 0, \
123*4882a593Smuzhiyun }, \
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun static const struct iio_chan_spec sx9500_channels[] = {
127*4882a593Smuzhiyun SX9500_CHANNEL(0),
128*4882a593Smuzhiyun SX9500_CHANNEL(1),
129*4882a593Smuzhiyun SX9500_CHANNEL(2),
130*4882a593Smuzhiyun SX9500_CHANNEL(3),
131*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(4),
132*4882a593Smuzhiyun };
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun static const struct {
135*4882a593Smuzhiyun int val;
136*4882a593Smuzhiyun int val2;
137*4882a593Smuzhiyun } sx9500_samp_freq_table[] = {
138*4882a593Smuzhiyun {33, 333333},
139*4882a593Smuzhiyun {16, 666666},
140*4882a593Smuzhiyun {11, 111111},
141*4882a593Smuzhiyun {8, 333333},
142*4882a593Smuzhiyun {6, 666666},
143*4882a593Smuzhiyun {5, 0},
144*4882a593Smuzhiyun {3, 333333},
145*4882a593Smuzhiyun {2, 500000},
146*4882a593Smuzhiyun };
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun static const unsigned int sx9500_scan_period_table[] = {
149*4882a593Smuzhiyun 30, 60, 90, 120, 150, 200, 300, 400,
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun static const struct regmap_range sx9500_writable_reg_ranges[] = {
153*4882a593Smuzhiyun regmap_reg_range(SX9500_REG_IRQ_MSK, SX9500_REG_IRQ_MSK),
154*4882a593Smuzhiyun regmap_reg_range(SX9500_REG_PROX_CTRL0, SX9500_REG_PROX_CTRL8),
155*4882a593Smuzhiyun regmap_reg_range(SX9500_REG_SENSOR_SEL, SX9500_REG_SENSOR_SEL),
156*4882a593Smuzhiyun regmap_reg_range(SX9500_REG_OFFSET_MSB, SX9500_REG_OFFSET_LSB),
157*4882a593Smuzhiyun regmap_reg_range(SX9500_REG_RESET, SX9500_REG_RESET),
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun static const struct regmap_access_table sx9500_writeable_regs = {
161*4882a593Smuzhiyun .yes_ranges = sx9500_writable_reg_ranges,
162*4882a593Smuzhiyun .n_yes_ranges = ARRAY_SIZE(sx9500_writable_reg_ranges),
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun /*
166*4882a593Smuzhiyun * All allocated registers are readable, so we just list unallocated
167*4882a593Smuzhiyun * ones.
168*4882a593Smuzhiyun */
169*4882a593Smuzhiyun static const struct regmap_range sx9500_non_readable_reg_ranges[] = {
170*4882a593Smuzhiyun regmap_reg_range(SX9500_REG_STAT + 1, SX9500_REG_STAT + 1),
171*4882a593Smuzhiyun regmap_reg_range(SX9500_REG_IRQ_MSK + 1, SX9500_REG_PROX_CTRL0 - 1),
172*4882a593Smuzhiyun regmap_reg_range(SX9500_REG_PROX_CTRL8 + 1, SX9500_REG_SENSOR_SEL - 1),
173*4882a593Smuzhiyun regmap_reg_range(SX9500_REG_OFFSET_LSB + 1, SX9500_REG_RESET - 1),
174*4882a593Smuzhiyun };
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun static const struct regmap_access_table sx9500_readable_regs = {
177*4882a593Smuzhiyun .no_ranges = sx9500_non_readable_reg_ranges,
178*4882a593Smuzhiyun .n_no_ranges = ARRAY_SIZE(sx9500_non_readable_reg_ranges),
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun static const struct regmap_range sx9500_volatile_reg_ranges[] = {
182*4882a593Smuzhiyun regmap_reg_range(SX9500_REG_IRQ_SRC, SX9500_REG_STAT),
183*4882a593Smuzhiyun regmap_reg_range(SX9500_REG_USE_MSB, SX9500_REG_OFFSET_LSB),
184*4882a593Smuzhiyun regmap_reg_range(SX9500_REG_RESET, SX9500_REG_RESET),
185*4882a593Smuzhiyun };
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun static const struct regmap_access_table sx9500_volatile_regs = {
188*4882a593Smuzhiyun .yes_ranges = sx9500_volatile_reg_ranges,
189*4882a593Smuzhiyun .n_yes_ranges = ARRAY_SIZE(sx9500_volatile_reg_ranges),
190*4882a593Smuzhiyun };
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun static const struct regmap_config sx9500_regmap_config = {
193*4882a593Smuzhiyun .reg_bits = 8,
194*4882a593Smuzhiyun .val_bits = 8,
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun .max_register = SX9500_REG_RESET,
197*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun .wr_table = &sx9500_writeable_regs,
200*4882a593Smuzhiyun .rd_table = &sx9500_readable_regs,
201*4882a593Smuzhiyun .volatile_table = &sx9500_volatile_regs,
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun
sx9500_inc_users(struct sx9500_data * data,int * counter,unsigned int reg,unsigned int bitmask)204*4882a593Smuzhiyun static int sx9500_inc_users(struct sx9500_data *data, int *counter,
205*4882a593Smuzhiyun unsigned int reg, unsigned int bitmask)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun (*counter)++;
208*4882a593Smuzhiyun if (*counter != 1)
209*4882a593Smuzhiyun /* Bit is already active, nothing to do. */
210*4882a593Smuzhiyun return 0;
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun return regmap_update_bits(data->regmap, reg, bitmask, bitmask);
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun
sx9500_dec_users(struct sx9500_data * data,int * counter,unsigned int reg,unsigned int bitmask)215*4882a593Smuzhiyun static int sx9500_dec_users(struct sx9500_data *data, int *counter,
216*4882a593Smuzhiyun unsigned int reg, unsigned int bitmask)
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun (*counter)--;
219*4882a593Smuzhiyun if (*counter != 0)
220*4882a593Smuzhiyun /* There are more users, do not deactivate. */
221*4882a593Smuzhiyun return 0;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun return regmap_update_bits(data->regmap, reg, bitmask, 0);
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
sx9500_inc_chan_users(struct sx9500_data * data,int chan)226*4882a593Smuzhiyun static int sx9500_inc_chan_users(struct sx9500_data *data, int chan)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun return sx9500_inc_users(data, &data->channel_users[chan],
229*4882a593Smuzhiyun SX9500_REG_PROX_CTRL0, BIT(chan));
230*4882a593Smuzhiyun }
231*4882a593Smuzhiyun
sx9500_dec_chan_users(struct sx9500_data * data,int chan)232*4882a593Smuzhiyun static int sx9500_dec_chan_users(struct sx9500_data *data, int chan)
233*4882a593Smuzhiyun {
234*4882a593Smuzhiyun return sx9500_dec_users(data, &data->channel_users[chan],
235*4882a593Smuzhiyun SX9500_REG_PROX_CTRL0, BIT(chan));
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun
sx9500_inc_data_rdy_users(struct sx9500_data * data)238*4882a593Smuzhiyun static int sx9500_inc_data_rdy_users(struct sx9500_data *data)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun return sx9500_inc_users(data, &data->data_rdy_users,
241*4882a593Smuzhiyun SX9500_REG_IRQ_MSK, SX9500_CONVDONE_IRQ);
242*4882a593Smuzhiyun }
243*4882a593Smuzhiyun
sx9500_dec_data_rdy_users(struct sx9500_data * data)244*4882a593Smuzhiyun static int sx9500_dec_data_rdy_users(struct sx9500_data *data)
245*4882a593Smuzhiyun {
246*4882a593Smuzhiyun return sx9500_dec_users(data, &data->data_rdy_users,
247*4882a593Smuzhiyun SX9500_REG_IRQ_MSK, SX9500_CONVDONE_IRQ);
248*4882a593Smuzhiyun }
249*4882a593Smuzhiyun
sx9500_inc_close_far_users(struct sx9500_data * data)250*4882a593Smuzhiyun static int sx9500_inc_close_far_users(struct sx9500_data *data)
251*4882a593Smuzhiyun {
252*4882a593Smuzhiyun return sx9500_inc_users(data, &data->close_far_users,
253*4882a593Smuzhiyun SX9500_REG_IRQ_MSK,
254*4882a593Smuzhiyun SX9500_CLOSE_IRQ | SX9500_FAR_IRQ);
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
sx9500_dec_close_far_users(struct sx9500_data * data)257*4882a593Smuzhiyun static int sx9500_dec_close_far_users(struct sx9500_data *data)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun return sx9500_dec_users(data, &data->close_far_users,
260*4882a593Smuzhiyun SX9500_REG_IRQ_MSK,
261*4882a593Smuzhiyun SX9500_CLOSE_IRQ | SX9500_FAR_IRQ);
262*4882a593Smuzhiyun }
263*4882a593Smuzhiyun
sx9500_read_prox_data(struct sx9500_data * data,const struct iio_chan_spec * chan,int * val)264*4882a593Smuzhiyun static int sx9500_read_prox_data(struct sx9500_data *data,
265*4882a593Smuzhiyun const struct iio_chan_spec *chan,
266*4882a593Smuzhiyun int *val)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun int ret;
269*4882a593Smuzhiyun __be16 regval;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun ret = regmap_write(data->regmap, SX9500_REG_SENSOR_SEL, chan->channel);
272*4882a593Smuzhiyun if (ret < 0)
273*4882a593Smuzhiyun return ret;
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun ret = regmap_bulk_read(data->regmap, SX9500_REG_USE_MSB, ®val, 2);
276*4882a593Smuzhiyun if (ret < 0)
277*4882a593Smuzhiyun return ret;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun *val = be16_to_cpu(regval);
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun return IIO_VAL_INT;
282*4882a593Smuzhiyun }
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun /*
285*4882a593Smuzhiyun * If we have no interrupt support, we have to wait for a scan period
286*4882a593Smuzhiyun * after enabling a channel to get a result.
287*4882a593Smuzhiyun */
sx9500_wait_for_sample(struct sx9500_data * data)288*4882a593Smuzhiyun static int sx9500_wait_for_sample(struct sx9500_data *data)
289*4882a593Smuzhiyun {
290*4882a593Smuzhiyun int ret;
291*4882a593Smuzhiyun unsigned int val;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun ret = regmap_read(data->regmap, SX9500_REG_PROX_CTRL0, &val);
294*4882a593Smuzhiyun if (ret < 0)
295*4882a593Smuzhiyun return ret;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun val = (val & SX9500_SCAN_PERIOD_MASK) >> SX9500_SCAN_PERIOD_SHIFT;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun msleep(sx9500_scan_period_table[val]);
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun return 0;
302*4882a593Smuzhiyun }
303*4882a593Smuzhiyun
sx9500_read_proximity(struct sx9500_data * data,const struct iio_chan_spec * chan,int * val)304*4882a593Smuzhiyun static int sx9500_read_proximity(struct sx9500_data *data,
305*4882a593Smuzhiyun const struct iio_chan_spec *chan,
306*4882a593Smuzhiyun int *val)
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun int ret;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun mutex_lock(&data->mutex);
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun ret = sx9500_inc_chan_users(data, chan->channel);
313*4882a593Smuzhiyun if (ret < 0)
314*4882a593Smuzhiyun goto out;
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun ret = sx9500_inc_data_rdy_users(data);
317*4882a593Smuzhiyun if (ret < 0)
318*4882a593Smuzhiyun goto out_dec_chan;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun mutex_unlock(&data->mutex);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun if (data->client->irq > 0)
323*4882a593Smuzhiyun ret = wait_for_completion_interruptible(&data->completion);
324*4882a593Smuzhiyun else
325*4882a593Smuzhiyun ret = sx9500_wait_for_sample(data);
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun mutex_lock(&data->mutex);
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun if (ret < 0)
330*4882a593Smuzhiyun goto out_dec_data_rdy;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun ret = sx9500_read_prox_data(data, chan, val);
333*4882a593Smuzhiyun if (ret < 0)
334*4882a593Smuzhiyun goto out_dec_data_rdy;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun ret = sx9500_dec_data_rdy_users(data);
337*4882a593Smuzhiyun if (ret < 0)
338*4882a593Smuzhiyun goto out_dec_chan;
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun ret = sx9500_dec_chan_users(data, chan->channel);
341*4882a593Smuzhiyun if (ret < 0)
342*4882a593Smuzhiyun goto out;
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun ret = IIO_VAL_INT;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun goto out;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun out_dec_data_rdy:
349*4882a593Smuzhiyun sx9500_dec_data_rdy_users(data);
350*4882a593Smuzhiyun out_dec_chan:
351*4882a593Smuzhiyun sx9500_dec_chan_users(data, chan->channel);
352*4882a593Smuzhiyun out:
353*4882a593Smuzhiyun mutex_unlock(&data->mutex);
354*4882a593Smuzhiyun reinit_completion(&data->completion);
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun return ret;
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun
sx9500_read_samp_freq(struct sx9500_data * data,int * val,int * val2)359*4882a593Smuzhiyun static int sx9500_read_samp_freq(struct sx9500_data *data,
360*4882a593Smuzhiyun int *val, int *val2)
361*4882a593Smuzhiyun {
362*4882a593Smuzhiyun int ret;
363*4882a593Smuzhiyun unsigned int regval;
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun mutex_lock(&data->mutex);
366*4882a593Smuzhiyun ret = regmap_read(data->regmap, SX9500_REG_PROX_CTRL0, ®val);
367*4882a593Smuzhiyun mutex_unlock(&data->mutex);
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun if (ret < 0)
370*4882a593Smuzhiyun return ret;
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun regval = (regval & SX9500_SCAN_PERIOD_MASK) >> SX9500_SCAN_PERIOD_SHIFT;
373*4882a593Smuzhiyun *val = sx9500_samp_freq_table[regval].val;
374*4882a593Smuzhiyun *val2 = sx9500_samp_freq_table[regval].val2;
375*4882a593Smuzhiyun
376*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
377*4882a593Smuzhiyun }
378*4882a593Smuzhiyun
sx9500_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long mask)379*4882a593Smuzhiyun static int sx9500_read_raw(struct iio_dev *indio_dev,
380*4882a593Smuzhiyun const struct iio_chan_spec *chan,
381*4882a593Smuzhiyun int *val, int *val2, long mask)
382*4882a593Smuzhiyun {
383*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
384*4882a593Smuzhiyun int ret;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun switch (chan->type) {
387*4882a593Smuzhiyun case IIO_PROXIMITY:
388*4882a593Smuzhiyun switch (mask) {
389*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
390*4882a593Smuzhiyun ret = iio_device_claim_direct_mode(indio_dev);
391*4882a593Smuzhiyun if (ret)
392*4882a593Smuzhiyun return ret;
393*4882a593Smuzhiyun ret = sx9500_read_proximity(data, chan, val);
394*4882a593Smuzhiyun iio_device_release_direct_mode(indio_dev);
395*4882a593Smuzhiyun return ret;
396*4882a593Smuzhiyun case IIO_CHAN_INFO_SAMP_FREQ:
397*4882a593Smuzhiyun return sx9500_read_samp_freq(data, val, val2);
398*4882a593Smuzhiyun default:
399*4882a593Smuzhiyun return -EINVAL;
400*4882a593Smuzhiyun }
401*4882a593Smuzhiyun default:
402*4882a593Smuzhiyun return -EINVAL;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun }
405*4882a593Smuzhiyun
sx9500_set_samp_freq(struct sx9500_data * data,int val,int val2)406*4882a593Smuzhiyun static int sx9500_set_samp_freq(struct sx9500_data *data,
407*4882a593Smuzhiyun int val, int val2)
408*4882a593Smuzhiyun {
409*4882a593Smuzhiyun int i, ret;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(sx9500_samp_freq_table); i++)
412*4882a593Smuzhiyun if (val == sx9500_samp_freq_table[i].val &&
413*4882a593Smuzhiyun val2 == sx9500_samp_freq_table[i].val2)
414*4882a593Smuzhiyun break;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun if (i == ARRAY_SIZE(sx9500_samp_freq_table))
417*4882a593Smuzhiyun return -EINVAL;
418*4882a593Smuzhiyun
419*4882a593Smuzhiyun mutex_lock(&data->mutex);
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun ret = regmap_update_bits(data->regmap, SX9500_REG_PROX_CTRL0,
422*4882a593Smuzhiyun SX9500_SCAN_PERIOD_MASK,
423*4882a593Smuzhiyun i << SX9500_SCAN_PERIOD_SHIFT);
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun mutex_unlock(&data->mutex);
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun return ret;
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun
sx9500_write_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int val,int val2,long mask)430*4882a593Smuzhiyun static int sx9500_write_raw(struct iio_dev *indio_dev,
431*4882a593Smuzhiyun const struct iio_chan_spec *chan,
432*4882a593Smuzhiyun int val, int val2, long mask)
433*4882a593Smuzhiyun {
434*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun switch (chan->type) {
437*4882a593Smuzhiyun case IIO_PROXIMITY:
438*4882a593Smuzhiyun switch (mask) {
439*4882a593Smuzhiyun case IIO_CHAN_INFO_SAMP_FREQ:
440*4882a593Smuzhiyun return sx9500_set_samp_freq(data, val, val2);
441*4882a593Smuzhiyun default:
442*4882a593Smuzhiyun return -EINVAL;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun default:
445*4882a593Smuzhiyun return -EINVAL;
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun
sx9500_irq_handler(int irq,void * private)449*4882a593Smuzhiyun static irqreturn_t sx9500_irq_handler(int irq, void *private)
450*4882a593Smuzhiyun {
451*4882a593Smuzhiyun struct iio_dev *indio_dev = private;
452*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun if (data->trigger_enabled)
455*4882a593Smuzhiyun iio_trigger_poll(data->trig);
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun /*
458*4882a593Smuzhiyun * Even if no event is enabled, we need to wake the thread to
459*4882a593Smuzhiyun * clear the interrupt state by reading SX9500_REG_IRQ_SRC. It
460*4882a593Smuzhiyun * is not possible to do that here because regmap_read takes a
461*4882a593Smuzhiyun * mutex.
462*4882a593Smuzhiyun */
463*4882a593Smuzhiyun return IRQ_WAKE_THREAD;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun
sx9500_push_events(struct iio_dev * indio_dev)466*4882a593Smuzhiyun static void sx9500_push_events(struct iio_dev *indio_dev)
467*4882a593Smuzhiyun {
468*4882a593Smuzhiyun int ret;
469*4882a593Smuzhiyun unsigned int val, chan;
470*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
471*4882a593Smuzhiyun
472*4882a593Smuzhiyun ret = regmap_read(data->regmap, SX9500_REG_STAT, &val);
473*4882a593Smuzhiyun if (ret < 0) {
474*4882a593Smuzhiyun dev_err(&data->client->dev, "i2c transfer error in irq\n");
475*4882a593Smuzhiyun return;
476*4882a593Smuzhiyun }
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun val >>= SX9500_PROXSTAT_SHIFT;
479*4882a593Smuzhiyun for (chan = 0; chan < SX9500_NUM_CHANNELS; chan++) {
480*4882a593Smuzhiyun int dir;
481*4882a593Smuzhiyun u64 ev;
482*4882a593Smuzhiyun bool new_prox = val & BIT(chan);
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun if (!data->event_enabled[chan])
485*4882a593Smuzhiyun continue;
486*4882a593Smuzhiyun if (new_prox == data->prox_stat[chan])
487*4882a593Smuzhiyun /* No change on this channel. */
488*4882a593Smuzhiyun continue;
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun dir = new_prox ? IIO_EV_DIR_FALLING : IIO_EV_DIR_RISING;
491*4882a593Smuzhiyun ev = IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, chan,
492*4882a593Smuzhiyun IIO_EV_TYPE_THRESH, dir);
493*4882a593Smuzhiyun iio_push_event(indio_dev, ev, iio_get_time_ns(indio_dev));
494*4882a593Smuzhiyun data->prox_stat[chan] = new_prox;
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
sx9500_irq_thread_handler(int irq,void * private)498*4882a593Smuzhiyun static irqreturn_t sx9500_irq_thread_handler(int irq, void *private)
499*4882a593Smuzhiyun {
500*4882a593Smuzhiyun struct iio_dev *indio_dev = private;
501*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
502*4882a593Smuzhiyun int ret;
503*4882a593Smuzhiyun unsigned int val;
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun mutex_lock(&data->mutex);
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun ret = regmap_read(data->regmap, SX9500_REG_IRQ_SRC, &val);
508*4882a593Smuzhiyun if (ret < 0) {
509*4882a593Smuzhiyun dev_err(&data->client->dev, "i2c transfer error in irq\n");
510*4882a593Smuzhiyun goto out;
511*4882a593Smuzhiyun }
512*4882a593Smuzhiyun
513*4882a593Smuzhiyun if (val & (SX9500_CLOSE_IRQ | SX9500_FAR_IRQ))
514*4882a593Smuzhiyun sx9500_push_events(indio_dev);
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun if (val & SX9500_CONVDONE_IRQ)
517*4882a593Smuzhiyun complete(&data->completion);
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun out:
520*4882a593Smuzhiyun mutex_unlock(&data->mutex);
521*4882a593Smuzhiyun
522*4882a593Smuzhiyun return IRQ_HANDLED;
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun
sx9500_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)525*4882a593Smuzhiyun static int sx9500_read_event_config(struct iio_dev *indio_dev,
526*4882a593Smuzhiyun const struct iio_chan_spec *chan,
527*4882a593Smuzhiyun enum iio_event_type type,
528*4882a593Smuzhiyun enum iio_event_direction dir)
529*4882a593Smuzhiyun {
530*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun if (chan->type != IIO_PROXIMITY || type != IIO_EV_TYPE_THRESH ||
533*4882a593Smuzhiyun dir != IIO_EV_DIR_EITHER)
534*4882a593Smuzhiyun return -EINVAL;
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun return data->event_enabled[chan->channel];
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun
sx9500_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)539*4882a593Smuzhiyun static int sx9500_write_event_config(struct iio_dev *indio_dev,
540*4882a593Smuzhiyun const struct iio_chan_spec *chan,
541*4882a593Smuzhiyun enum iio_event_type type,
542*4882a593Smuzhiyun enum iio_event_direction dir,
543*4882a593Smuzhiyun int state)
544*4882a593Smuzhiyun {
545*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
546*4882a593Smuzhiyun int ret;
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun if (chan->type != IIO_PROXIMITY || type != IIO_EV_TYPE_THRESH ||
549*4882a593Smuzhiyun dir != IIO_EV_DIR_EITHER)
550*4882a593Smuzhiyun return -EINVAL;
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun mutex_lock(&data->mutex);
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun if (state == 1) {
555*4882a593Smuzhiyun ret = sx9500_inc_chan_users(data, chan->channel);
556*4882a593Smuzhiyun if (ret < 0)
557*4882a593Smuzhiyun goto out_unlock;
558*4882a593Smuzhiyun ret = sx9500_inc_close_far_users(data);
559*4882a593Smuzhiyun if (ret < 0)
560*4882a593Smuzhiyun goto out_undo_chan;
561*4882a593Smuzhiyun } else {
562*4882a593Smuzhiyun ret = sx9500_dec_chan_users(data, chan->channel);
563*4882a593Smuzhiyun if (ret < 0)
564*4882a593Smuzhiyun goto out_unlock;
565*4882a593Smuzhiyun ret = sx9500_dec_close_far_users(data);
566*4882a593Smuzhiyun if (ret < 0)
567*4882a593Smuzhiyun goto out_undo_chan;
568*4882a593Smuzhiyun }
569*4882a593Smuzhiyun
570*4882a593Smuzhiyun data->event_enabled[chan->channel] = state;
571*4882a593Smuzhiyun goto out_unlock;
572*4882a593Smuzhiyun
573*4882a593Smuzhiyun out_undo_chan:
574*4882a593Smuzhiyun if (state == 1)
575*4882a593Smuzhiyun sx9500_dec_chan_users(data, chan->channel);
576*4882a593Smuzhiyun else
577*4882a593Smuzhiyun sx9500_inc_chan_users(data, chan->channel);
578*4882a593Smuzhiyun out_unlock:
579*4882a593Smuzhiyun mutex_unlock(&data->mutex);
580*4882a593Smuzhiyun return ret;
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun
sx9500_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * scan_mask)583*4882a593Smuzhiyun static int sx9500_update_scan_mode(struct iio_dev *indio_dev,
584*4882a593Smuzhiyun const unsigned long *scan_mask)
585*4882a593Smuzhiyun {
586*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun mutex_lock(&data->mutex);
589*4882a593Smuzhiyun kfree(data->buffer);
590*4882a593Smuzhiyun data->buffer = kzalloc(indio_dev->scan_bytes, GFP_KERNEL);
591*4882a593Smuzhiyun mutex_unlock(&data->mutex);
592*4882a593Smuzhiyun
593*4882a593Smuzhiyun if (data->buffer == NULL)
594*4882a593Smuzhiyun return -ENOMEM;
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun return 0;
597*4882a593Smuzhiyun }
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
600*4882a593Smuzhiyun "2.500000 3.333333 5 6.666666 8.333333 11.111111 16.666666 33.333333");
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun static struct attribute *sx9500_attributes[] = {
603*4882a593Smuzhiyun &iio_const_attr_sampling_frequency_available.dev_attr.attr,
604*4882a593Smuzhiyun NULL,
605*4882a593Smuzhiyun };
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun static const struct attribute_group sx9500_attribute_group = {
608*4882a593Smuzhiyun .attrs = sx9500_attributes,
609*4882a593Smuzhiyun };
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun static const struct iio_info sx9500_info = {
612*4882a593Smuzhiyun .attrs = &sx9500_attribute_group,
613*4882a593Smuzhiyun .read_raw = &sx9500_read_raw,
614*4882a593Smuzhiyun .write_raw = &sx9500_write_raw,
615*4882a593Smuzhiyun .read_event_config = &sx9500_read_event_config,
616*4882a593Smuzhiyun .write_event_config = &sx9500_write_event_config,
617*4882a593Smuzhiyun .update_scan_mode = &sx9500_update_scan_mode,
618*4882a593Smuzhiyun };
619*4882a593Smuzhiyun
sx9500_set_trigger_state(struct iio_trigger * trig,bool state)620*4882a593Smuzhiyun static int sx9500_set_trigger_state(struct iio_trigger *trig,
621*4882a593Smuzhiyun bool state)
622*4882a593Smuzhiyun {
623*4882a593Smuzhiyun struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
624*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
625*4882a593Smuzhiyun int ret;
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun mutex_lock(&data->mutex);
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun if (state)
630*4882a593Smuzhiyun ret = sx9500_inc_data_rdy_users(data);
631*4882a593Smuzhiyun else
632*4882a593Smuzhiyun ret = sx9500_dec_data_rdy_users(data);
633*4882a593Smuzhiyun if (ret < 0)
634*4882a593Smuzhiyun goto out;
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun data->trigger_enabled = state;
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun out:
639*4882a593Smuzhiyun mutex_unlock(&data->mutex);
640*4882a593Smuzhiyun
641*4882a593Smuzhiyun return ret;
642*4882a593Smuzhiyun }
643*4882a593Smuzhiyun
644*4882a593Smuzhiyun static const struct iio_trigger_ops sx9500_trigger_ops = {
645*4882a593Smuzhiyun .set_trigger_state = sx9500_set_trigger_state,
646*4882a593Smuzhiyun };
647*4882a593Smuzhiyun
sx9500_trigger_handler(int irq,void * private)648*4882a593Smuzhiyun static irqreturn_t sx9500_trigger_handler(int irq, void *private)
649*4882a593Smuzhiyun {
650*4882a593Smuzhiyun struct iio_poll_func *pf = private;
651*4882a593Smuzhiyun struct iio_dev *indio_dev = pf->indio_dev;
652*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
653*4882a593Smuzhiyun int val, bit, ret, i = 0;
654*4882a593Smuzhiyun
655*4882a593Smuzhiyun mutex_lock(&data->mutex);
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun for_each_set_bit(bit, indio_dev->active_scan_mask,
658*4882a593Smuzhiyun indio_dev->masklength) {
659*4882a593Smuzhiyun ret = sx9500_read_prox_data(data, &indio_dev->channels[bit],
660*4882a593Smuzhiyun &val);
661*4882a593Smuzhiyun if (ret < 0)
662*4882a593Smuzhiyun goto out;
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun data->buffer[i++] = val;
665*4882a593Smuzhiyun }
666*4882a593Smuzhiyun
667*4882a593Smuzhiyun iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
668*4882a593Smuzhiyun iio_get_time_ns(indio_dev));
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun out:
671*4882a593Smuzhiyun mutex_unlock(&data->mutex);
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun iio_trigger_notify_done(indio_dev->trig);
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun return IRQ_HANDLED;
676*4882a593Smuzhiyun }
677*4882a593Smuzhiyun
sx9500_buffer_postenable(struct iio_dev * indio_dev)678*4882a593Smuzhiyun static int sx9500_buffer_postenable(struct iio_dev *indio_dev)
679*4882a593Smuzhiyun {
680*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
681*4882a593Smuzhiyun int ret = 0, i;
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun mutex_lock(&data->mutex);
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun for (i = 0; i < SX9500_NUM_CHANNELS; i++)
686*4882a593Smuzhiyun if (test_bit(i, indio_dev->active_scan_mask)) {
687*4882a593Smuzhiyun ret = sx9500_inc_chan_users(data, i);
688*4882a593Smuzhiyun if (ret)
689*4882a593Smuzhiyun break;
690*4882a593Smuzhiyun }
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun if (ret)
693*4882a593Smuzhiyun for (i = i - 1; i >= 0; i--)
694*4882a593Smuzhiyun if (test_bit(i, indio_dev->active_scan_mask))
695*4882a593Smuzhiyun sx9500_dec_chan_users(data, i);
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun mutex_unlock(&data->mutex);
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun return ret;
700*4882a593Smuzhiyun }
701*4882a593Smuzhiyun
sx9500_buffer_predisable(struct iio_dev * indio_dev)702*4882a593Smuzhiyun static int sx9500_buffer_predisable(struct iio_dev *indio_dev)
703*4882a593Smuzhiyun {
704*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
705*4882a593Smuzhiyun int ret = 0, i;
706*4882a593Smuzhiyun
707*4882a593Smuzhiyun mutex_lock(&data->mutex);
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun for (i = 0; i < SX9500_NUM_CHANNELS; i++)
710*4882a593Smuzhiyun if (test_bit(i, indio_dev->active_scan_mask)) {
711*4882a593Smuzhiyun ret = sx9500_dec_chan_users(data, i);
712*4882a593Smuzhiyun if (ret)
713*4882a593Smuzhiyun break;
714*4882a593Smuzhiyun }
715*4882a593Smuzhiyun
716*4882a593Smuzhiyun if (ret)
717*4882a593Smuzhiyun for (i = i - 1; i >= 0; i--)
718*4882a593Smuzhiyun if (test_bit(i, indio_dev->active_scan_mask))
719*4882a593Smuzhiyun sx9500_inc_chan_users(data, i);
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun mutex_unlock(&data->mutex);
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun return ret;
724*4882a593Smuzhiyun }
725*4882a593Smuzhiyun
726*4882a593Smuzhiyun static const struct iio_buffer_setup_ops sx9500_buffer_setup_ops = {
727*4882a593Smuzhiyun .postenable = sx9500_buffer_postenable,
728*4882a593Smuzhiyun .predisable = sx9500_buffer_predisable,
729*4882a593Smuzhiyun };
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun struct sx9500_reg_default {
732*4882a593Smuzhiyun u8 reg;
733*4882a593Smuzhiyun u8 def;
734*4882a593Smuzhiyun };
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun static const struct sx9500_reg_default sx9500_default_regs[] = {
737*4882a593Smuzhiyun {
738*4882a593Smuzhiyun .reg = SX9500_REG_PROX_CTRL1,
739*4882a593Smuzhiyun /* Shield enabled, small range. */
740*4882a593Smuzhiyun .def = 0x43,
741*4882a593Smuzhiyun },
742*4882a593Smuzhiyun {
743*4882a593Smuzhiyun .reg = SX9500_REG_PROX_CTRL2,
744*4882a593Smuzhiyun /* x8 gain, 167kHz frequency, finest resolution. */
745*4882a593Smuzhiyun .def = 0x77,
746*4882a593Smuzhiyun },
747*4882a593Smuzhiyun {
748*4882a593Smuzhiyun .reg = SX9500_REG_PROX_CTRL3,
749*4882a593Smuzhiyun /* Doze enabled, 2x scan period doze, no raw filter. */
750*4882a593Smuzhiyun .def = 0x40,
751*4882a593Smuzhiyun },
752*4882a593Smuzhiyun {
753*4882a593Smuzhiyun .reg = SX9500_REG_PROX_CTRL4,
754*4882a593Smuzhiyun /* Average threshold. */
755*4882a593Smuzhiyun .def = 0x30,
756*4882a593Smuzhiyun },
757*4882a593Smuzhiyun {
758*4882a593Smuzhiyun .reg = SX9500_REG_PROX_CTRL5,
759*4882a593Smuzhiyun /*
760*4882a593Smuzhiyun * Debouncer off, lowest average negative filter,
761*4882a593Smuzhiyun * highest average postive filter.
762*4882a593Smuzhiyun */
763*4882a593Smuzhiyun .def = 0x0f,
764*4882a593Smuzhiyun },
765*4882a593Smuzhiyun {
766*4882a593Smuzhiyun .reg = SX9500_REG_PROX_CTRL6,
767*4882a593Smuzhiyun /* Proximity detection threshold: 280 */
768*4882a593Smuzhiyun .def = 0x0e,
769*4882a593Smuzhiyun },
770*4882a593Smuzhiyun {
771*4882a593Smuzhiyun .reg = SX9500_REG_PROX_CTRL7,
772*4882a593Smuzhiyun /*
773*4882a593Smuzhiyun * No automatic compensation, compensate each pin
774*4882a593Smuzhiyun * independently, proximity hysteresis: 32, close
775*4882a593Smuzhiyun * debouncer off, far debouncer off.
776*4882a593Smuzhiyun */
777*4882a593Smuzhiyun .def = 0x00,
778*4882a593Smuzhiyun },
779*4882a593Smuzhiyun {
780*4882a593Smuzhiyun .reg = SX9500_REG_PROX_CTRL8,
781*4882a593Smuzhiyun /* No stuck timeout, no periodic compensation. */
782*4882a593Smuzhiyun .def = 0x00,
783*4882a593Smuzhiyun },
784*4882a593Smuzhiyun {
785*4882a593Smuzhiyun .reg = SX9500_REG_PROX_CTRL0,
786*4882a593Smuzhiyun /* Scan period: 30ms, all sensors disabled. */
787*4882a593Smuzhiyun .def = 0x00,
788*4882a593Smuzhiyun },
789*4882a593Smuzhiyun };
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun /* Activate all channels and perform an initial compensation. */
sx9500_init_compensation(struct iio_dev * indio_dev)792*4882a593Smuzhiyun static int sx9500_init_compensation(struct iio_dev *indio_dev)
793*4882a593Smuzhiyun {
794*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
795*4882a593Smuzhiyun int i, ret;
796*4882a593Smuzhiyun unsigned int val;
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun ret = regmap_update_bits(data->regmap, SX9500_REG_PROX_CTRL0,
799*4882a593Smuzhiyun SX9500_CHAN_MASK, SX9500_CHAN_MASK);
800*4882a593Smuzhiyun if (ret < 0)
801*4882a593Smuzhiyun return ret;
802*4882a593Smuzhiyun
803*4882a593Smuzhiyun for (i = 10; i >= 0; i--) {
804*4882a593Smuzhiyun usleep_range(10000, 20000);
805*4882a593Smuzhiyun ret = regmap_read(data->regmap, SX9500_REG_STAT, &val);
806*4882a593Smuzhiyun if (ret < 0)
807*4882a593Smuzhiyun goto out;
808*4882a593Smuzhiyun if (!(val & SX9500_COMPSTAT_MASK))
809*4882a593Smuzhiyun break;
810*4882a593Smuzhiyun }
811*4882a593Smuzhiyun
812*4882a593Smuzhiyun if (i < 0) {
813*4882a593Smuzhiyun dev_err(&data->client->dev, "initial compensation timed out");
814*4882a593Smuzhiyun ret = -ETIMEDOUT;
815*4882a593Smuzhiyun }
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun out:
818*4882a593Smuzhiyun regmap_update_bits(data->regmap, SX9500_REG_PROX_CTRL0,
819*4882a593Smuzhiyun SX9500_CHAN_MASK, 0);
820*4882a593Smuzhiyun return ret;
821*4882a593Smuzhiyun }
822*4882a593Smuzhiyun
sx9500_init_device(struct iio_dev * indio_dev)823*4882a593Smuzhiyun static int sx9500_init_device(struct iio_dev *indio_dev)
824*4882a593Smuzhiyun {
825*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
826*4882a593Smuzhiyun int ret, i;
827*4882a593Smuzhiyun unsigned int val;
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun if (data->gpiod_rst) {
830*4882a593Smuzhiyun gpiod_set_value_cansleep(data->gpiod_rst, 0);
831*4882a593Smuzhiyun usleep_range(1000, 2000);
832*4882a593Smuzhiyun gpiod_set_value_cansleep(data->gpiod_rst, 1);
833*4882a593Smuzhiyun usleep_range(1000, 2000);
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun ret = regmap_write(data->regmap, SX9500_REG_IRQ_MSK, 0);
837*4882a593Smuzhiyun if (ret < 0)
838*4882a593Smuzhiyun return ret;
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun ret = regmap_write(data->regmap, SX9500_REG_RESET,
841*4882a593Smuzhiyun SX9500_SOFT_RESET);
842*4882a593Smuzhiyun if (ret < 0)
843*4882a593Smuzhiyun return ret;
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun ret = regmap_read(data->regmap, SX9500_REG_IRQ_SRC, &val);
846*4882a593Smuzhiyun if (ret < 0)
847*4882a593Smuzhiyun return ret;
848*4882a593Smuzhiyun
849*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(sx9500_default_regs); i++) {
850*4882a593Smuzhiyun ret = regmap_write(data->regmap,
851*4882a593Smuzhiyun sx9500_default_regs[i].reg,
852*4882a593Smuzhiyun sx9500_default_regs[i].def);
853*4882a593Smuzhiyun if (ret < 0)
854*4882a593Smuzhiyun return ret;
855*4882a593Smuzhiyun }
856*4882a593Smuzhiyun
857*4882a593Smuzhiyun return sx9500_init_compensation(indio_dev);
858*4882a593Smuzhiyun }
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
861*4882a593Smuzhiyun static const struct acpi_gpio_params interrupt_gpios = { 2, 0, false };
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun static const struct acpi_gpio_mapping acpi_sx9500_gpios[] = {
864*4882a593Smuzhiyun { "reset-gpios", &reset_gpios, 1 },
865*4882a593Smuzhiyun /*
866*4882a593Smuzhiyun * Some platforms have a bug in ACPI GPIO description making IRQ
867*4882a593Smuzhiyun * GPIO to be output only. Ask the GPIO core to ignore this limit.
868*4882a593Smuzhiyun */
869*4882a593Smuzhiyun { "interrupt-gpios", &interrupt_gpios, 1, ACPI_GPIO_QUIRK_NO_IO_RESTRICTION },
870*4882a593Smuzhiyun { },
871*4882a593Smuzhiyun };
872*4882a593Smuzhiyun
sx9500_gpio_probe(struct i2c_client * client,struct sx9500_data * data)873*4882a593Smuzhiyun static void sx9500_gpio_probe(struct i2c_client *client,
874*4882a593Smuzhiyun struct sx9500_data *data)
875*4882a593Smuzhiyun {
876*4882a593Smuzhiyun struct gpio_desc *gpiod_int;
877*4882a593Smuzhiyun struct device *dev;
878*4882a593Smuzhiyun int ret;
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun if (!client)
881*4882a593Smuzhiyun return;
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun dev = &client->dev;
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun ret = devm_acpi_dev_add_driver_gpios(dev, acpi_sx9500_gpios);
886*4882a593Smuzhiyun if (ret)
887*4882a593Smuzhiyun dev_dbg(dev, "Unable to add GPIO mapping table\n");
888*4882a593Smuzhiyun
889*4882a593Smuzhiyun if (client->irq <= 0) {
890*4882a593Smuzhiyun gpiod_int = devm_gpiod_get(dev, "interrupt", GPIOD_IN);
891*4882a593Smuzhiyun if (IS_ERR(gpiod_int))
892*4882a593Smuzhiyun dev_err(dev, "gpio get irq failed\n");
893*4882a593Smuzhiyun else
894*4882a593Smuzhiyun client->irq = gpiod_to_irq(gpiod_int);
895*4882a593Smuzhiyun }
896*4882a593Smuzhiyun
897*4882a593Smuzhiyun data->gpiod_rst = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
898*4882a593Smuzhiyun if (IS_ERR(data->gpiod_rst)) {
899*4882a593Smuzhiyun dev_warn(dev, "gpio get reset pin failed\n");
900*4882a593Smuzhiyun data->gpiod_rst = NULL;
901*4882a593Smuzhiyun }
902*4882a593Smuzhiyun }
903*4882a593Smuzhiyun
sx9500_probe(struct i2c_client * client,const struct i2c_device_id * id)904*4882a593Smuzhiyun static int sx9500_probe(struct i2c_client *client,
905*4882a593Smuzhiyun const struct i2c_device_id *id)
906*4882a593Smuzhiyun {
907*4882a593Smuzhiyun int ret;
908*4882a593Smuzhiyun struct iio_dev *indio_dev;
909*4882a593Smuzhiyun struct sx9500_data *data;
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
912*4882a593Smuzhiyun if (indio_dev == NULL)
913*4882a593Smuzhiyun return -ENOMEM;
914*4882a593Smuzhiyun
915*4882a593Smuzhiyun data = iio_priv(indio_dev);
916*4882a593Smuzhiyun data->client = client;
917*4882a593Smuzhiyun mutex_init(&data->mutex);
918*4882a593Smuzhiyun init_completion(&data->completion);
919*4882a593Smuzhiyun data->trigger_enabled = false;
920*4882a593Smuzhiyun
921*4882a593Smuzhiyun data->regmap = devm_regmap_init_i2c(client, &sx9500_regmap_config);
922*4882a593Smuzhiyun if (IS_ERR(data->regmap))
923*4882a593Smuzhiyun return PTR_ERR(data->regmap);
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun indio_dev->name = SX9500_DRIVER_NAME;
926*4882a593Smuzhiyun indio_dev->channels = sx9500_channels;
927*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(sx9500_channels);
928*4882a593Smuzhiyun indio_dev->info = &sx9500_info;
929*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
930*4882a593Smuzhiyun i2c_set_clientdata(client, indio_dev);
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun sx9500_gpio_probe(client, data);
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun ret = sx9500_init_device(indio_dev);
935*4882a593Smuzhiyun if (ret < 0)
936*4882a593Smuzhiyun return ret;
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun if (client->irq <= 0)
939*4882a593Smuzhiyun dev_warn(&client->dev, "no valid irq found\n");
940*4882a593Smuzhiyun else {
941*4882a593Smuzhiyun ret = devm_request_threaded_irq(&client->dev, client->irq,
942*4882a593Smuzhiyun sx9500_irq_handler, sx9500_irq_thread_handler,
943*4882a593Smuzhiyun IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
944*4882a593Smuzhiyun SX9500_IRQ_NAME, indio_dev);
945*4882a593Smuzhiyun if (ret < 0)
946*4882a593Smuzhiyun return ret;
947*4882a593Smuzhiyun
948*4882a593Smuzhiyun data->trig = devm_iio_trigger_alloc(&client->dev,
949*4882a593Smuzhiyun "%s-dev%d", indio_dev->name, indio_dev->id);
950*4882a593Smuzhiyun if (!data->trig)
951*4882a593Smuzhiyun return -ENOMEM;
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun data->trig->dev.parent = &client->dev;
954*4882a593Smuzhiyun data->trig->ops = &sx9500_trigger_ops;
955*4882a593Smuzhiyun iio_trigger_set_drvdata(data->trig, indio_dev);
956*4882a593Smuzhiyun
957*4882a593Smuzhiyun ret = iio_trigger_register(data->trig);
958*4882a593Smuzhiyun if (ret)
959*4882a593Smuzhiyun return ret;
960*4882a593Smuzhiyun }
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun ret = iio_triggered_buffer_setup(indio_dev, NULL,
963*4882a593Smuzhiyun sx9500_trigger_handler,
964*4882a593Smuzhiyun &sx9500_buffer_setup_ops);
965*4882a593Smuzhiyun if (ret < 0)
966*4882a593Smuzhiyun goto out_trigger_unregister;
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
969*4882a593Smuzhiyun if (ret < 0)
970*4882a593Smuzhiyun goto out_buffer_cleanup;
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun return 0;
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun out_buffer_cleanup:
975*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
976*4882a593Smuzhiyun out_trigger_unregister:
977*4882a593Smuzhiyun if (client->irq > 0)
978*4882a593Smuzhiyun iio_trigger_unregister(data->trig);
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun return ret;
981*4882a593Smuzhiyun }
982*4882a593Smuzhiyun
sx9500_remove(struct i2c_client * client)983*4882a593Smuzhiyun static int sx9500_remove(struct i2c_client *client)
984*4882a593Smuzhiyun {
985*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(client);
986*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
987*4882a593Smuzhiyun
988*4882a593Smuzhiyun iio_device_unregister(indio_dev);
989*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
990*4882a593Smuzhiyun if (client->irq > 0)
991*4882a593Smuzhiyun iio_trigger_unregister(data->trig);
992*4882a593Smuzhiyun kfree(data->buffer);
993*4882a593Smuzhiyun
994*4882a593Smuzhiyun return 0;
995*4882a593Smuzhiyun }
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
sx9500_suspend(struct device * dev)998*4882a593Smuzhiyun static int sx9500_suspend(struct device *dev)
999*4882a593Smuzhiyun {
1000*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1001*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
1002*4882a593Smuzhiyun int ret;
1003*4882a593Smuzhiyun
1004*4882a593Smuzhiyun mutex_lock(&data->mutex);
1005*4882a593Smuzhiyun ret = regmap_read(data->regmap, SX9500_REG_PROX_CTRL0,
1006*4882a593Smuzhiyun &data->suspend_ctrl0);
1007*4882a593Smuzhiyun if (ret < 0)
1008*4882a593Smuzhiyun goto out;
1009*4882a593Smuzhiyun
1010*4882a593Smuzhiyun /*
1011*4882a593Smuzhiyun * Scan period doesn't matter because when all the sensors are
1012*4882a593Smuzhiyun * deactivated the device is in sleep mode.
1013*4882a593Smuzhiyun */
1014*4882a593Smuzhiyun ret = regmap_write(data->regmap, SX9500_REG_PROX_CTRL0, 0);
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun out:
1017*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1018*4882a593Smuzhiyun return ret;
1019*4882a593Smuzhiyun }
1020*4882a593Smuzhiyun
sx9500_resume(struct device * dev)1021*4882a593Smuzhiyun static int sx9500_resume(struct device *dev)
1022*4882a593Smuzhiyun {
1023*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1024*4882a593Smuzhiyun struct sx9500_data *data = iio_priv(indio_dev);
1025*4882a593Smuzhiyun int ret;
1026*4882a593Smuzhiyun
1027*4882a593Smuzhiyun mutex_lock(&data->mutex);
1028*4882a593Smuzhiyun ret = regmap_write(data->regmap, SX9500_REG_PROX_CTRL0,
1029*4882a593Smuzhiyun data->suspend_ctrl0);
1030*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1031*4882a593Smuzhiyun
1032*4882a593Smuzhiyun return ret;
1033*4882a593Smuzhiyun }
1034*4882a593Smuzhiyun #endif /* CONFIG_PM_SLEEP */
1035*4882a593Smuzhiyun
1036*4882a593Smuzhiyun static const struct dev_pm_ops sx9500_pm_ops = {
1037*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(sx9500_suspend, sx9500_resume)
1038*4882a593Smuzhiyun };
1039*4882a593Smuzhiyun
1040*4882a593Smuzhiyun static const struct acpi_device_id sx9500_acpi_match[] = {
1041*4882a593Smuzhiyun {"SSX9500", 0},
1042*4882a593Smuzhiyun {"SASX9500", 0},
1043*4882a593Smuzhiyun { },
1044*4882a593Smuzhiyun };
1045*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, sx9500_acpi_match);
1046*4882a593Smuzhiyun
1047*4882a593Smuzhiyun static const struct of_device_id sx9500_of_match[] = {
1048*4882a593Smuzhiyun { .compatible = "semtech,sx9500", },
1049*4882a593Smuzhiyun { }
1050*4882a593Smuzhiyun };
1051*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sx9500_of_match);
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun static const struct i2c_device_id sx9500_id[] = {
1054*4882a593Smuzhiyun {"sx9500", 0},
1055*4882a593Smuzhiyun { },
1056*4882a593Smuzhiyun };
1057*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, sx9500_id);
1058*4882a593Smuzhiyun
1059*4882a593Smuzhiyun static struct i2c_driver sx9500_driver = {
1060*4882a593Smuzhiyun .driver = {
1061*4882a593Smuzhiyun .name = SX9500_DRIVER_NAME,
1062*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(sx9500_acpi_match),
1063*4882a593Smuzhiyun .of_match_table = of_match_ptr(sx9500_of_match),
1064*4882a593Smuzhiyun .pm = &sx9500_pm_ops,
1065*4882a593Smuzhiyun },
1066*4882a593Smuzhiyun .probe = sx9500_probe,
1067*4882a593Smuzhiyun .remove = sx9500_remove,
1068*4882a593Smuzhiyun .id_table = sx9500_id,
1069*4882a593Smuzhiyun };
1070*4882a593Smuzhiyun module_i2c_driver(sx9500_driver);
1071*4882a593Smuzhiyun
1072*4882a593Smuzhiyun MODULE_AUTHOR("Vlad Dogaru <vlad.dogaru@intel.com>");
1073*4882a593Smuzhiyun MODULE_DESCRIPTION("Driver for Semtech SX9500 proximity sensor");
1074*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1075