xref: /OK3568_Linux_fs/kernel/drivers/iio/proximity/sx9310.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright 2018 Google LLC.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Driver for Semtech's SX9310/SX9311 capacitive proximity/button solution.
6*4882a593Smuzhiyun  * Based on SX9500 driver and Semtech driver using the input framework
7*4882a593Smuzhiyun  * <https://my.syncplicity.com/share/teouwsim8niiaud/
8*4882a593Smuzhiyun  *          linux-driver-SX9310_NoSmartHSensing>.
9*4882a593Smuzhiyun  * Reworked in April 2019 by Evan Green <evgreen@chromium.org>
10*4882a593Smuzhiyun  * and in January 2020 by Daniel Campello <campello@chromium.org>.
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/acpi.h>
14*4882a593Smuzhiyun #include <linux/bitfield.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/i2c.h>
17*4882a593Smuzhiyun #include <linux/irq.h>
18*4882a593Smuzhiyun #include <linux/kernel.h>
19*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
20*4882a593Smuzhiyun #include <linux/module.h>
21*4882a593Smuzhiyun #include <linux/pm.h>
22*4882a593Smuzhiyun #include <linux/regmap.h>
23*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
24*4882a593Smuzhiyun #include <linux/slab.h>
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #include <linux/iio/buffer.h>
27*4882a593Smuzhiyun #include <linux/iio/events.h>
28*4882a593Smuzhiyun #include <linux/iio/iio.h>
29*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
30*4882a593Smuzhiyun #include <linux/iio/trigger.h>
31*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
32*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /* Register definitions. */
35*4882a593Smuzhiyun #define SX9310_REG_IRQ_SRC				0x00
36*4882a593Smuzhiyun #define SX9310_REG_STAT0				0x01
37*4882a593Smuzhiyun #define SX9310_REG_STAT1				0x02
38*4882a593Smuzhiyun #define SX9310_REG_STAT1_COMPSTAT_MASK			GENMASK(3, 0)
39*4882a593Smuzhiyun #define SX9310_REG_IRQ_MSK				0x03
40*4882a593Smuzhiyun #define   SX9310_CONVDONE_IRQ				BIT(3)
41*4882a593Smuzhiyun #define   SX9310_FAR_IRQ				BIT(5)
42*4882a593Smuzhiyun #define   SX9310_CLOSE_IRQ				BIT(6)
43*4882a593Smuzhiyun #define SX9310_REG_IRQ_FUNC				0x04
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL0				0x10
46*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL0_SENSOREN_MASK		GENMASK(3, 0)
47*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL0_SCANPERIOD_MASK		GENMASK(7, 4)
48*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL0_SCANPERIOD_15MS		0x01
49*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL1				0x11
50*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL2				0x12
51*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL2_COMBMODE_CS1_CS2	(0x02 << 6)
52*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL2_SHIELDEN_DYNAMIC	(0x01 << 2)
53*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL3				0x13
54*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL3_GAIN0_X8		(0x03 << 2)
55*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL3_GAIN12_X4		0x02
56*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL4				0x14
57*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL4_RESOLUTION_FINEST	0x07
58*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL5				0x15
59*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL5_RANGE_SMALL		(0x03 << 6)
60*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL5_STARTUPSENS_CS1		(0x01 << 2)
61*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL5_RAWFILT_1P25		0x02
62*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL6				0x16
63*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL6_AVGTHRESH_DEFAULT	0x20
64*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL7				0x17
65*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL7_AVGNEGFILT_2		(0x01 << 3)
66*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL7_AVGPOSFILT_512		0x05
67*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL8				0x18
68*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL9				0x19
69*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL8_9_PTHRESH_28		(0x08 << 3)
70*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL8_9_PTHRESH_96		(0x11 << 3)
71*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL8_9_BODYTHRESH_900	0x03
72*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL8_9_BODYTHRESH_1500	0x05
73*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL10				0x1a
74*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL10_HYST_6PCT		(0x01 << 4)
75*4882a593Smuzhiyun #define   SX9310_REG_PROX_CTRL10_FAR_DEBOUNCE_2		0x01
76*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL11				0x1b
77*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL12				0x1c
78*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL13				0x1d
79*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL14				0x1e
80*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL15				0x1f
81*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL16				0x20
82*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL17				0x21
83*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL18				0x22
84*4882a593Smuzhiyun #define SX9310_REG_PROX_CTRL19				0x23
85*4882a593Smuzhiyun #define SX9310_REG_SAR_CTRL0				0x2a
86*4882a593Smuzhiyun #define   SX9310_REG_SAR_CTRL0_SARDEB_4_SAMPLES		(0x02 << 5)
87*4882a593Smuzhiyun #define   SX9310_REG_SAR_CTRL0_SARHYST_8		(0x02 << 3)
88*4882a593Smuzhiyun #define SX9310_REG_SAR_CTRL1				0x2b
89*4882a593Smuzhiyun /* Each increment of the slope register is 0.0078125. */
90*4882a593Smuzhiyun #define   SX9310_REG_SAR_CTRL1_SLOPE(_hnslope)		(_hnslope / 78125)
91*4882a593Smuzhiyun #define SX9310_REG_SAR_CTRL2				0x2c
92*4882a593Smuzhiyun #define   SX9310_REG_SAR_CTRL2_SAROFFSET_DEFAULT	0x3c
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun #define SX9310_REG_SENSOR_SEL				0x30
95*4882a593Smuzhiyun #define SX9310_REG_USE_MSB				0x31
96*4882a593Smuzhiyun #define SX9310_REG_USE_LSB				0x32
97*4882a593Smuzhiyun #define SX9310_REG_AVG_MSB				0x33
98*4882a593Smuzhiyun #define SX9310_REG_AVG_LSB				0x34
99*4882a593Smuzhiyun #define SX9310_REG_DIFF_MSB				0x35
100*4882a593Smuzhiyun #define SX9310_REG_DIFF_LSB				0x36
101*4882a593Smuzhiyun #define SX9310_REG_OFFSET_MSB				0x37
102*4882a593Smuzhiyun #define SX9310_REG_OFFSET_LSB				0x38
103*4882a593Smuzhiyun #define SX9310_REG_SAR_MSB				0x39
104*4882a593Smuzhiyun #define SX9310_REG_SAR_LSB				0x3a
105*4882a593Smuzhiyun #define SX9310_REG_I2C_ADDR				0x40
106*4882a593Smuzhiyun #define SX9310_REG_PAUSE				0x41
107*4882a593Smuzhiyun #define SX9310_REG_WHOAMI				0x42
108*4882a593Smuzhiyun #define   SX9310_WHOAMI_VALUE				0x01
109*4882a593Smuzhiyun #define   SX9311_WHOAMI_VALUE				0x02
110*4882a593Smuzhiyun #define SX9310_REG_RESET				0x7f
111*4882a593Smuzhiyun #define   SX9310_SOFT_RESET				0xde
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun /* 4 hardware channels, as defined in STAT0: COMB, CS2, CS1 and CS0. */
115*4882a593Smuzhiyun #define SX9310_NUM_CHANNELS				4
116*4882a593Smuzhiyun static_assert(SX9310_NUM_CHANNELS < BITS_PER_LONG);
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun struct sx9310_data {
119*4882a593Smuzhiyun 	/* Serialize access to registers and channel configuration */
120*4882a593Smuzhiyun 	struct mutex mutex;
121*4882a593Smuzhiyun 	struct i2c_client *client;
122*4882a593Smuzhiyun 	struct iio_trigger *trig;
123*4882a593Smuzhiyun 	struct regmap *regmap;
124*4882a593Smuzhiyun 	struct regulator_bulk_data supplies[2];
125*4882a593Smuzhiyun 	/*
126*4882a593Smuzhiyun 	 * Last reading of the proximity status for each channel.
127*4882a593Smuzhiyun 	 * We only send an event to user space when this changes.
128*4882a593Smuzhiyun 	 */
129*4882a593Smuzhiyun 	unsigned long chan_prox_stat;
130*4882a593Smuzhiyun 	bool trigger_enabled;
131*4882a593Smuzhiyun 	/* Ensure correct alignment of timestamp when present. */
132*4882a593Smuzhiyun 	struct {
133*4882a593Smuzhiyun 		__be16 channels[SX9310_NUM_CHANNELS];
134*4882a593Smuzhiyun 		s64 ts __aligned(8);
135*4882a593Smuzhiyun 	} buffer;
136*4882a593Smuzhiyun 	/* Remember enabled channels and sample rate during suspend. */
137*4882a593Smuzhiyun 	unsigned int suspend_ctrl0;
138*4882a593Smuzhiyun 	struct completion completion;
139*4882a593Smuzhiyun 	unsigned long chan_read;
140*4882a593Smuzhiyun 	unsigned long chan_event;
141*4882a593Smuzhiyun 	unsigned int whoami;
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun static const struct iio_event_spec sx9310_events[] = {
145*4882a593Smuzhiyun 	{
146*4882a593Smuzhiyun 		.type = IIO_EV_TYPE_THRESH,
147*4882a593Smuzhiyun 		.dir = IIO_EV_DIR_EITHER,
148*4882a593Smuzhiyun 		.mask_separate = BIT(IIO_EV_INFO_ENABLE),
149*4882a593Smuzhiyun 	},
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun #define SX9310_NAMED_CHANNEL(idx, name)					 \
153*4882a593Smuzhiyun 	{								 \
154*4882a593Smuzhiyun 		.type = IIO_PROXIMITY,					 \
155*4882a593Smuzhiyun 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		 \
156*4882a593Smuzhiyun 		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
157*4882a593Smuzhiyun 		.indexed = 1,						 \
158*4882a593Smuzhiyun 		.channel = idx,						 \
159*4882a593Smuzhiyun 		.extend_name = name,					 \
160*4882a593Smuzhiyun 		.address = SX9310_REG_DIFF_MSB,				 \
161*4882a593Smuzhiyun 		.event_spec = sx9310_events,				 \
162*4882a593Smuzhiyun 		.num_event_specs = ARRAY_SIZE(sx9310_events),		 \
163*4882a593Smuzhiyun 		.scan_index = idx,					 \
164*4882a593Smuzhiyun 		.scan_type = {						 \
165*4882a593Smuzhiyun 			.sign = 's',					 \
166*4882a593Smuzhiyun 			.realbits = 12,					 \
167*4882a593Smuzhiyun 			.storagebits = 16,				 \
168*4882a593Smuzhiyun 			.endianness = IIO_BE,				 \
169*4882a593Smuzhiyun 		},							 \
170*4882a593Smuzhiyun 	}
171*4882a593Smuzhiyun #define SX9310_CHANNEL(idx) SX9310_NAMED_CHANNEL(idx, NULL)
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun static const struct iio_chan_spec sx9310_channels[] = {
174*4882a593Smuzhiyun 	SX9310_CHANNEL(0),			/* CS0 */
175*4882a593Smuzhiyun 	SX9310_CHANNEL(1),			/* CS1 */
176*4882a593Smuzhiyun 	SX9310_CHANNEL(2),			/* CS2 */
177*4882a593Smuzhiyun 	SX9310_NAMED_CHANNEL(3, "comb"),	/* COMB */
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	IIO_CHAN_SOFT_TIMESTAMP(4),
180*4882a593Smuzhiyun };
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun /*
183*4882a593Smuzhiyun  * Each entry contains the integer part (val) and the fractional part, in micro
184*4882a593Smuzhiyun  * seconds. It conforms to the IIO output IIO_VAL_INT_PLUS_MICRO.
185*4882a593Smuzhiyun  */
186*4882a593Smuzhiyun static const struct {
187*4882a593Smuzhiyun 	int val;
188*4882a593Smuzhiyun 	int val2;
189*4882a593Smuzhiyun } sx9310_samp_freq_table[] = {
190*4882a593Smuzhiyun 	{ 500, 0 }, /* 0000: Min (no idle time) */
191*4882a593Smuzhiyun 	{ 66, 666666 }, /* 0001: 15 ms */
192*4882a593Smuzhiyun 	{ 33, 333333 }, /* 0010: 30 ms (Typ.) */
193*4882a593Smuzhiyun 	{ 22, 222222 }, /* 0011: 45 ms */
194*4882a593Smuzhiyun 	{ 16, 666666 }, /* 0100: 60 ms */
195*4882a593Smuzhiyun 	{ 11, 111111 }, /* 0101: 90 ms */
196*4882a593Smuzhiyun 	{ 8, 333333 }, /* 0110: 120 ms */
197*4882a593Smuzhiyun 	{ 5, 0 }, /* 0111: 200 ms */
198*4882a593Smuzhiyun 	{ 2, 500000 }, /* 1000: 400 ms */
199*4882a593Smuzhiyun 	{ 1, 666666 }, /* 1001: 600 ms */
200*4882a593Smuzhiyun 	{ 1, 250000 }, /* 1010: 800 ms */
201*4882a593Smuzhiyun 	{ 1, 0 }, /* 1011: 1 s */
202*4882a593Smuzhiyun 	{ 0, 500000 }, /* 1100: 2 s */
203*4882a593Smuzhiyun 	{ 0, 333333 }, /* 1101: 3 s */
204*4882a593Smuzhiyun 	{ 0, 250000 }, /* 1110: 4 s */
205*4882a593Smuzhiyun 	{ 0, 200000 }, /* 1111: 5 s */
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun static const unsigned int sx9310_scan_period_table[] = {
208*4882a593Smuzhiyun 	2,   15,  30,  45,   60,   90,	 120,  200,
209*4882a593Smuzhiyun 	400, 600, 800, 1000, 2000, 3000, 4000, 5000,
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun 
sx9310_show_samp_freq_avail(struct device * dev,struct device_attribute * attr,char * buf)212*4882a593Smuzhiyun static ssize_t sx9310_show_samp_freq_avail(struct device *dev,
213*4882a593Smuzhiyun 					   struct device_attribute *attr,
214*4882a593Smuzhiyun 					   char *buf)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun 	size_t len = 0;
217*4882a593Smuzhiyun 	int i;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(sx9310_samp_freq_table); i++)
220*4882a593Smuzhiyun 		len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%d ",
221*4882a593Smuzhiyun 				 sx9310_samp_freq_table[i].val,
222*4882a593Smuzhiyun 				 sx9310_samp_freq_table[i].val2);
223*4882a593Smuzhiyun 	buf[len - 1] = '\n';
224*4882a593Smuzhiyun 	return len;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(sx9310_show_samp_freq_avail);
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun static const struct regmap_range sx9310_writable_reg_ranges[] = {
229*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_IRQ_MSK, SX9310_REG_IRQ_FUNC),
230*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_PROX_CTRL0, SX9310_REG_PROX_CTRL19),
231*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_SAR_CTRL0, SX9310_REG_SAR_CTRL2),
232*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_SENSOR_SEL, SX9310_REG_SENSOR_SEL),
233*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_OFFSET_MSB, SX9310_REG_OFFSET_LSB),
234*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_PAUSE, SX9310_REG_PAUSE),
235*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_RESET, SX9310_REG_RESET),
236*4882a593Smuzhiyun };
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun static const struct regmap_access_table sx9310_writeable_regs = {
239*4882a593Smuzhiyun 	.yes_ranges = sx9310_writable_reg_ranges,
240*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(sx9310_writable_reg_ranges),
241*4882a593Smuzhiyun };
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun static const struct regmap_range sx9310_readable_reg_ranges[] = {
244*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_IRQ_SRC, SX9310_REG_IRQ_FUNC),
245*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_PROX_CTRL0, SX9310_REG_PROX_CTRL19),
246*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_SAR_CTRL0, SX9310_REG_SAR_CTRL2),
247*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_SENSOR_SEL, SX9310_REG_SAR_LSB),
248*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_I2C_ADDR, SX9310_REG_WHOAMI),
249*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_RESET, SX9310_REG_RESET),
250*4882a593Smuzhiyun };
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun static const struct regmap_access_table sx9310_readable_regs = {
253*4882a593Smuzhiyun 	.yes_ranges = sx9310_readable_reg_ranges,
254*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(sx9310_readable_reg_ranges),
255*4882a593Smuzhiyun };
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun static const struct regmap_range sx9310_volatile_reg_ranges[] = {
258*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_IRQ_SRC, SX9310_REG_STAT1),
259*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_USE_MSB, SX9310_REG_DIFF_LSB),
260*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_SAR_MSB, SX9310_REG_SAR_LSB),
261*4882a593Smuzhiyun 	regmap_reg_range(SX9310_REG_RESET, SX9310_REG_RESET),
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun static const struct regmap_access_table sx9310_volatile_regs = {
265*4882a593Smuzhiyun 	.yes_ranges = sx9310_volatile_reg_ranges,
266*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(sx9310_volatile_reg_ranges),
267*4882a593Smuzhiyun };
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun static const struct regmap_config sx9310_regmap_config = {
270*4882a593Smuzhiyun 	.reg_bits = 8,
271*4882a593Smuzhiyun 	.val_bits = 8,
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	.max_register = SX9310_REG_RESET,
274*4882a593Smuzhiyun 	.cache_type = REGCACHE_RBTREE,
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun 	.wr_table = &sx9310_writeable_regs,
277*4882a593Smuzhiyun 	.rd_table = &sx9310_readable_regs,
278*4882a593Smuzhiyun 	.volatile_table = &sx9310_volatile_regs,
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun 
sx9310_update_chan_en(struct sx9310_data * data,unsigned long chan_read,unsigned long chan_event)281*4882a593Smuzhiyun static int sx9310_update_chan_en(struct sx9310_data *data,
282*4882a593Smuzhiyun 				 unsigned long chan_read,
283*4882a593Smuzhiyun 				 unsigned long chan_event)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun 	int ret;
286*4882a593Smuzhiyun 	unsigned long channels = chan_read | chan_event;
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 	if ((data->chan_read | data->chan_event) != channels) {
289*4882a593Smuzhiyun 		ret = regmap_update_bits(data->regmap, SX9310_REG_PROX_CTRL0,
290*4882a593Smuzhiyun 					 SX9310_REG_PROX_CTRL0_SENSOREN_MASK,
291*4882a593Smuzhiyun 					 channels);
292*4882a593Smuzhiyun 		if (ret)
293*4882a593Smuzhiyun 			return ret;
294*4882a593Smuzhiyun 	}
295*4882a593Smuzhiyun 	data->chan_read = chan_read;
296*4882a593Smuzhiyun 	data->chan_event = chan_event;
297*4882a593Smuzhiyun 	return 0;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun 
sx9310_get_read_channel(struct sx9310_data * data,int channel)300*4882a593Smuzhiyun static int sx9310_get_read_channel(struct sx9310_data *data, int channel)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun 	return sx9310_update_chan_en(data, data->chan_read | BIT(channel),
303*4882a593Smuzhiyun 				     data->chan_event);
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun 
sx9310_put_read_channel(struct sx9310_data * data,int channel)306*4882a593Smuzhiyun static int sx9310_put_read_channel(struct sx9310_data *data, int channel)
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun 	return sx9310_update_chan_en(data, data->chan_read & ~BIT(channel),
309*4882a593Smuzhiyun 				     data->chan_event);
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun 
sx9310_get_event_channel(struct sx9310_data * data,int channel)312*4882a593Smuzhiyun static int sx9310_get_event_channel(struct sx9310_data *data, int channel)
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun 	return sx9310_update_chan_en(data, data->chan_read,
315*4882a593Smuzhiyun 				     data->chan_event | BIT(channel));
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun 
sx9310_put_event_channel(struct sx9310_data * data,int channel)318*4882a593Smuzhiyun static int sx9310_put_event_channel(struct sx9310_data *data, int channel)
319*4882a593Smuzhiyun {
320*4882a593Smuzhiyun 	return sx9310_update_chan_en(data, data->chan_read,
321*4882a593Smuzhiyun 				     data->chan_event & ~BIT(channel));
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun 
sx9310_enable_irq(struct sx9310_data * data,unsigned int irq)324*4882a593Smuzhiyun static int sx9310_enable_irq(struct sx9310_data *data, unsigned int irq)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun 	if (!data->client->irq)
327*4882a593Smuzhiyun 		return 0;
328*4882a593Smuzhiyun 	return regmap_update_bits(data->regmap, SX9310_REG_IRQ_MSK, irq, irq);
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun 
sx9310_disable_irq(struct sx9310_data * data,unsigned int irq)331*4882a593Smuzhiyun static int sx9310_disable_irq(struct sx9310_data *data, unsigned int irq)
332*4882a593Smuzhiyun {
333*4882a593Smuzhiyun 	if (!data->client->irq)
334*4882a593Smuzhiyun 		return 0;
335*4882a593Smuzhiyun 	return regmap_update_bits(data->regmap, SX9310_REG_IRQ_MSK, irq, 0);
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun 
sx9310_read_prox_data(struct sx9310_data * data,const struct iio_chan_spec * chan,__be16 * val)338*4882a593Smuzhiyun static int sx9310_read_prox_data(struct sx9310_data *data,
339*4882a593Smuzhiyun 				 const struct iio_chan_spec *chan, __be16 *val)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun 	int ret;
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	ret = regmap_write(data->regmap, SX9310_REG_SENSOR_SEL, chan->channel);
344*4882a593Smuzhiyun 	if (ret)
345*4882a593Smuzhiyun 		return ret;
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun 	return regmap_bulk_read(data->regmap, chan->address, val, sizeof(*val));
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun /*
351*4882a593Smuzhiyun  * If we have no interrupt support, we have to wait for a scan period
352*4882a593Smuzhiyun  * after enabling a channel to get a result.
353*4882a593Smuzhiyun  */
sx9310_wait_for_sample(struct sx9310_data * data)354*4882a593Smuzhiyun static int sx9310_wait_for_sample(struct sx9310_data *data)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun 	int ret;
357*4882a593Smuzhiyun 	unsigned int val;
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0, &val);
360*4882a593Smuzhiyun 	if (ret)
361*4882a593Smuzhiyun 		return ret;
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	val = FIELD_GET(SX9310_REG_PROX_CTRL0_SCANPERIOD_MASK, val);
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	msleep(sx9310_scan_period_table[val]);
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun 	return 0;
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun 
sx9310_read_proximity(struct sx9310_data * data,const struct iio_chan_spec * chan,int * val)370*4882a593Smuzhiyun static int sx9310_read_proximity(struct sx9310_data *data,
371*4882a593Smuzhiyun 				 const struct iio_chan_spec *chan, int *val)
372*4882a593Smuzhiyun {
373*4882a593Smuzhiyun 	int ret;
374*4882a593Smuzhiyun 	__be16 rawval;
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	ret = sx9310_get_read_channel(data, chan->channel);
379*4882a593Smuzhiyun 	if (ret)
380*4882a593Smuzhiyun 		goto out;
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	ret = sx9310_enable_irq(data, SX9310_CONVDONE_IRQ);
383*4882a593Smuzhiyun 	if (ret)
384*4882a593Smuzhiyun 		goto out_put_channel;
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun 	if (data->client->irq) {
389*4882a593Smuzhiyun 		ret = wait_for_completion_interruptible(&data->completion);
390*4882a593Smuzhiyun 		reinit_completion(&data->completion);
391*4882a593Smuzhiyun 	} else {
392*4882a593Smuzhiyun 		ret = sx9310_wait_for_sample(data);
393*4882a593Smuzhiyun 	}
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	if (ret)
398*4882a593Smuzhiyun 		goto out_disable_irq;
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	ret = sx9310_read_prox_data(data, chan, &rawval);
401*4882a593Smuzhiyun 	if (ret)
402*4882a593Smuzhiyun 		goto out_disable_irq;
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	*val = sign_extend32(be16_to_cpu(rawval),
405*4882a593Smuzhiyun 			     chan->address == SX9310_REG_DIFF_MSB ? 11 : 15);
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	ret = sx9310_disable_irq(data, SX9310_CONVDONE_IRQ);
408*4882a593Smuzhiyun 	if (ret)
409*4882a593Smuzhiyun 		goto out_put_channel;
410*4882a593Smuzhiyun 
411*4882a593Smuzhiyun 	ret = sx9310_put_read_channel(data, chan->channel);
412*4882a593Smuzhiyun 	if (ret)
413*4882a593Smuzhiyun 		goto out;
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	return IIO_VAL_INT;
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun out_disable_irq:
420*4882a593Smuzhiyun 	sx9310_disable_irq(data, SX9310_CONVDONE_IRQ);
421*4882a593Smuzhiyun out_put_channel:
422*4882a593Smuzhiyun 	sx9310_put_read_channel(data, chan->channel);
423*4882a593Smuzhiyun out:
424*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun 	return ret;
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun 
sx9310_read_samp_freq(struct sx9310_data * data,int * val,int * val2)429*4882a593Smuzhiyun static int sx9310_read_samp_freq(struct sx9310_data *data, int *val, int *val2)
430*4882a593Smuzhiyun {
431*4882a593Smuzhiyun 	unsigned int regval;
432*4882a593Smuzhiyun 	int ret;
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0, &regval);
435*4882a593Smuzhiyun 	if (ret)
436*4882a593Smuzhiyun 		return ret;
437*4882a593Smuzhiyun 
438*4882a593Smuzhiyun 	regval = FIELD_GET(SX9310_REG_PROX_CTRL0_SCANPERIOD_MASK, regval);
439*4882a593Smuzhiyun 	*val = sx9310_samp_freq_table[regval].val;
440*4882a593Smuzhiyun 	*val2 = sx9310_samp_freq_table[regval].val2;
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun 	return IIO_VAL_INT_PLUS_MICRO;
443*4882a593Smuzhiyun }
444*4882a593Smuzhiyun 
sx9310_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long mask)445*4882a593Smuzhiyun static int sx9310_read_raw(struct iio_dev *indio_dev,
446*4882a593Smuzhiyun 			   const struct iio_chan_spec *chan, int *val,
447*4882a593Smuzhiyun 			   int *val2, long mask)
448*4882a593Smuzhiyun {
449*4882a593Smuzhiyun 	struct sx9310_data *data = iio_priv(indio_dev);
450*4882a593Smuzhiyun 	int ret;
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	if (chan->type != IIO_PROXIMITY)
453*4882a593Smuzhiyun 		return -EINVAL;
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun 	switch (mask) {
456*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
457*4882a593Smuzhiyun 		ret = iio_device_claim_direct_mode(indio_dev);
458*4882a593Smuzhiyun 		if (ret)
459*4882a593Smuzhiyun 			return ret;
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 		ret = sx9310_read_proximity(data, chan, val);
462*4882a593Smuzhiyun 		iio_device_release_direct_mode(indio_dev);
463*4882a593Smuzhiyun 		return ret;
464*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SAMP_FREQ:
465*4882a593Smuzhiyun 		return sx9310_read_samp_freq(data, val, val2);
466*4882a593Smuzhiyun 	default:
467*4882a593Smuzhiyun 		return -EINVAL;
468*4882a593Smuzhiyun 	}
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun 
sx9310_set_samp_freq(struct sx9310_data * data,int val,int val2)471*4882a593Smuzhiyun static int sx9310_set_samp_freq(struct sx9310_data *data, int val, int val2)
472*4882a593Smuzhiyun {
473*4882a593Smuzhiyun 	int i, ret;
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(sx9310_samp_freq_table); i++)
476*4882a593Smuzhiyun 		if (val == sx9310_samp_freq_table[i].val &&
477*4882a593Smuzhiyun 		    val2 == sx9310_samp_freq_table[i].val2)
478*4882a593Smuzhiyun 			break;
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	if (i == ARRAY_SIZE(sx9310_samp_freq_table))
481*4882a593Smuzhiyun 		return -EINVAL;
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 	ret = regmap_update_bits(
486*4882a593Smuzhiyun 		data->regmap, SX9310_REG_PROX_CTRL0,
487*4882a593Smuzhiyun 		SX9310_REG_PROX_CTRL0_SCANPERIOD_MASK,
488*4882a593Smuzhiyun 		FIELD_PREP(SX9310_REG_PROX_CTRL0_SCANPERIOD_MASK, i));
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun 	return ret;
493*4882a593Smuzhiyun }
494*4882a593Smuzhiyun 
sx9310_write_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int val,int val2,long mask)495*4882a593Smuzhiyun static int sx9310_write_raw(struct iio_dev *indio_dev,
496*4882a593Smuzhiyun 			    const struct iio_chan_spec *chan, int val, int val2,
497*4882a593Smuzhiyun 			    long mask)
498*4882a593Smuzhiyun {
499*4882a593Smuzhiyun 	struct sx9310_data *data = iio_priv(indio_dev);
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 	if (chan->type != IIO_PROXIMITY)
502*4882a593Smuzhiyun 		return -EINVAL;
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 	if (mask != IIO_CHAN_INFO_SAMP_FREQ)
505*4882a593Smuzhiyun 		return -EINVAL;
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun 	return sx9310_set_samp_freq(data, val, val2);
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun 
sx9310_irq_handler(int irq,void * private)510*4882a593Smuzhiyun static irqreturn_t sx9310_irq_handler(int irq, void *private)
511*4882a593Smuzhiyun {
512*4882a593Smuzhiyun 	struct iio_dev *indio_dev = private;
513*4882a593Smuzhiyun 	struct sx9310_data *data = iio_priv(indio_dev);
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 	if (data->trigger_enabled)
516*4882a593Smuzhiyun 		iio_trigger_poll(data->trig);
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun 	/*
519*4882a593Smuzhiyun 	 * Even if no event is enabled, we need to wake the thread to clear the
520*4882a593Smuzhiyun 	 * interrupt state by reading SX9310_REG_IRQ_SRC.
521*4882a593Smuzhiyun 	 * It is not possible to do that here because regmap_read takes a mutex.
522*4882a593Smuzhiyun 	 */
523*4882a593Smuzhiyun 	return IRQ_WAKE_THREAD;
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun 
sx9310_push_events(struct iio_dev * indio_dev)526*4882a593Smuzhiyun static void sx9310_push_events(struct iio_dev *indio_dev)
527*4882a593Smuzhiyun {
528*4882a593Smuzhiyun 	int ret;
529*4882a593Smuzhiyun 	unsigned int val, chan;
530*4882a593Smuzhiyun 	struct sx9310_data *data = iio_priv(indio_dev);
531*4882a593Smuzhiyun 	s64 timestamp = iio_get_time_ns(indio_dev);
532*4882a593Smuzhiyun 	unsigned long prox_changed;
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 	/* Read proximity state on all channels */
535*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, SX9310_REG_STAT0, &val);
536*4882a593Smuzhiyun 	if (ret) {
537*4882a593Smuzhiyun 		dev_err(&data->client->dev, "i2c transfer error in irq\n");
538*4882a593Smuzhiyun 		return;
539*4882a593Smuzhiyun 	}
540*4882a593Smuzhiyun 
541*4882a593Smuzhiyun 	/*
542*4882a593Smuzhiyun 	 * Only iterate over channels with changes on proximity status that have
543*4882a593Smuzhiyun 	 * events enabled.
544*4882a593Smuzhiyun 	 */
545*4882a593Smuzhiyun 	prox_changed = (data->chan_prox_stat ^ val) & data->chan_event;
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun 	for_each_set_bit(chan, &prox_changed, SX9310_NUM_CHANNELS) {
548*4882a593Smuzhiyun 		int dir;
549*4882a593Smuzhiyun 		u64 ev;
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 		dir = (val & BIT(chan)) ? IIO_EV_DIR_FALLING : IIO_EV_DIR_RISING;
552*4882a593Smuzhiyun 		ev = IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY, chan,
553*4882a593Smuzhiyun 					  IIO_EV_TYPE_THRESH, dir);
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 		iio_push_event(indio_dev, ev, timestamp);
556*4882a593Smuzhiyun 	}
557*4882a593Smuzhiyun 	data->chan_prox_stat = val;
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun 
sx9310_irq_thread_handler(int irq,void * private)560*4882a593Smuzhiyun static irqreturn_t sx9310_irq_thread_handler(int irq, void *private)
561*4882a593Smuzhiyun {
562*4882a593Smuzhiyun 	struct iio_dev *indio_dev = private;
563*4882a593Smuzhiyun 	struct sx9310_data *data = iio_priv(indio_dev);
564*4882a593Smuzhiyun 	int ret;
565*4882a593Smuzhiyun 	unsigned int val;
566*4882a593Smuzhiyun 
567*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
568*4882a593Smuzhiyun 
569*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, SX9310_REG_IRQ_SRC, &val);
570*4882a593Smuzhiyun 	if (ret) {
571*4882a593Smuzhiyun 		dev_err(&data->client->dev, "i2c transfer error in irq\n");
572*4882a593Smuzhiyun 		goto out;
573*4882a593Smuzhiyun 	}
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	if (val & (SX9310_FAR_IRQ | SX9310_CLOSE_IRQ))
576*4882a593Smuzhiyun 		sx9310_push_events(indio_dev);
577*4882a593Smuzhiyun 
578*4882a593Smuzhiyun 	if (val & SX9310_CONVDONE_IRQ)
579*4882a593Smuzhiyun 		complete(&data->completion);
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun out:
582*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
583*4882a593Smuzhiyun 
584*4882a593Smuzhiyun 	return IRQ_HANDLED;
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun 
sx9310_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)587*4882a593Smuzhiyun static int sx9310_read_event_config(struct iio_dev *indio_dev,
588*4882a593Smuzhiyun 				    const struct iio_chan_spec *chan,
589*4882a593Smuzhiyun 				    enum iio_event_type type,
590*4882a593Smuzhiyun 				    enum iio_event_direction dir)
591*4882a593Smuzhiyun {
592*4882a593Smuzhiyun 	struct sx9310_data *data = iio_priv(indio_dev);
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	return !!(data->chan_event & BIT(chan->channel));
595*4882a593Smuzhiyun }
596*4882a593Smuzhiyun 
sx9310_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)597*4882a593Smuzhiyun static int sx9310_write_event_config(struct iio_dev *indio_dev,
598*4882a593Smuzhiyun 				     const struct iio_chan_spec *chan,
599*4882a593Smuzhiyun 				     enum iio_event_type type,
600*4882a593Smuzhiyun 				     enum iio_event_direction dir, int state)
601*4882a593Smuzhiyun {
602*4882a593Smuzhiyun 	struct sx9310_data *data = iio_priv(indio_dev);
603*4882a593Smuzhiyun 	unsigned int eventirq = SX9310_FAR_IRQ | SX9310_CLOSE_IRQ;
604*4882a593Smuzhiyun 	int ret;
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	/* If the state hasn't changed, there's nothing to do. */
607*4882a593Smuzhiyun 	if (!!(data->chan_event & BIT(chan->channel)) == state)
608*4882a593Smuzhiyun 		return 0;
609*4882a593Smuzhiyun 
610*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
611*4882a593Smuzhiyun 	if (state) {
612*4882a593Smuzhiyun 		ret = sx9310_get_event_channel(data, chan->channel);
613*4882a593Smuzhiyun 		if (ret)
614*4882a593Smuzhiyun 			goto out_unlock;
615*4882a593Smuzhiyun 		if (!(data->chan_event & ~BIT(chan->channel))) {
616*4882a593Smuzhiyun 			ret = sx9310_enable_irq(data, eventirq);
617*4882a593Smuzhiyun 			if (ret)
618*4882a593Smuzhiyun 				sx9310_put_event_channel(data, chan->channel);
619*4882a593Smuzhiyun 		}
620*4882a593Smuzhiyun 	} else {
621*4882a593Smuzhiyun 		ret = sx9310_put_event_channel(data, chan->channel);
622*4882a593Smuzhiyun 		if (ret)
623*4882a593Smuzhiyun 			goto out_unlock;
624*4882a593Smuzhiyun 		if (!data->chan_event) {
625*4882a593Smuzhiyun 			ret = sx9310_disable_irq(data, eventirq);
626*4882a593Smuzhiyun 			if (ret)
627*4882a593Smuzhiyun 				sx9310_get_event_channel(data, chan->channel);
628*4882a593Smuzhiyun 		}
629*4882a593Smuzhiyun 	}
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun out_unlock:
632*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
633*4882a593Smuzhiyun 	return ret;
634*4882a593Smuzhiyun }
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun static struct attribute *sx9310_attributes[] = {
637*4882a593Smuzhiyun 	&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
638*4882a593Smuzhiyun 	NULL
639*4882a593Smuzhiyun };
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun static const struct attribute_group sx9310_attribute_group = {
642*4882a593Smuzhiyun 	.attrs = sx9310_attributes,
643*4882a593Smuzhiyun };
644*4882a593Smuzhiyun 
645*4882a593Smuzhiyun static const struct iio_info sx9310_info = {
646*4882a593Smuzhiyun 	.attrs = &sx9310_attribute_group,
647*4882a593Smuzhiyun 	.read_raw = sx9310_read_raw,
648*4882a593Smuzhiyun 	.write_raw = sx9310_write_raw,
649*4882a593Smuzhiyun 	.read_event_config = sx9310_read_event_config,
650*4882a593Smuzhiyun 	.write_event_config = sx9310_write_event_config,
651*4882a593Smuzhiyun };
652*4882a593Smuzhiyun 
sx9310_set_trigger_state(struct iio_trigger * trig,bool state)653*4882a593Smuzhiyun static int sx9310_set_trigger_state(struct iio_trigger *trig, bool state)
654*4882a593Smuzhiyun {
655*4882a593Smuzhiyun 	struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
656*4882a593Smuzhiyun 	struct sx9310_data *data = iio_priv(indio_dev);
657*4882a593Smuzhiyun 	int ret = 0;
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 	if (state)
662*4882a593Smuzhiyun 		ret = sx9310_enable_irq(data, SX9310_CONVDONE_IRQ);
663*4882a593Smuzhiyun 	else if (!data->chan_read)
664*4882a593Smuzhiyun 		ret = sx9310_disable_irq(data, SX9310_CONVDONE_IRQ);
665*4882a593Smuzhiyun 	if (ret)
666*4882a593Smuzhiyun 		goto out;
667*4882a593Smuzhiyun 
668*4882a593Smuzhiyun 	data->trigger_enabled = state;
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun out:
671*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
672*4882a593Smuzhiyun 
673*4882a593Smuzhiyun 	return ret;
674*4882a593Smuzhiyun }
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun static const struct iio_trigger_ops sx9310_trigger_ops = {
677*4882a593Smuzhiyun 	.set_trigger_state = sx9310_set_trigger_state,
678*4882a593Smuzhiyun };
679*4882a593Smuzhiyun 
sx9310_trigger_handler(int irq,void * private)680*4882a593Smuzhiyun static irqreturn_t sx9310_trigger_handler(int irq, void *private)
681*4882a593Smuzhiyun {
682*4882a593Smuzhiyun 	struct iio_poll_func *pf = private;
683*4882a593Smuzhiyun 	struct iio_dev *indio_dev = pf->indio_dev;
684*4882a593Smuzhiyun 	struct sx9310_data *data = iio_priv(indio_dev);
685*4882a593Smuzhiyun 	__be16 val;
686*4882a593Smuzhiyun 	int bit, ret, i = 0;
687*4882a593Smuzhiyun 
688*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
689*4882a593Smuzhiyun 
690*4882a593Smuzhiyun 	for_each_set_bit(bit, indio_dev->active_scan_mask,
691*4882a593Smuzhiyun 			 indio_dev->masklength) {
692*4882a593Smuzhiyun 		ret = sx9310_read_prox_data(data, &indio_dev->channels[bit],
693*4882a593Smuzhiyun 					    &val);
694*4882a593Smuzhiyun 		if (ret)
695*4882a593Smuzhiyun 			goto out;
696*4882a593Smuzhiyun 
697*4882a593Smuzhiyun 		data->buffer.channels[i++] = val;
698*4882a593Smuzhiyun 	}
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun 	iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
701*4882a593Smuzhiyun 					   pf->timestamp);
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun out:
704*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
705*4882a593Smuzhiyun 
706*4882a593Smuzhiyun 	iio_trigger_notify_done(indio_dev->trig);
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun 	return IRQ_HANDLED;
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun 
sx9310_buffer_preenable(struct iio_dev * indio_dev)711*4882a593Smuzhiyun static int sx9310_buffer_preenable(struct iio_dev *indio_dev)
712*4882a593Smuzhiyun {
713*4882a593Smuzhiyun 	struct sx9310_data *data = iio_priv(indio_dev);
714*4882a593Smuzhiyun 	unsigned long channels = 0;
715*4882a593Smuzhiyun 	int bit, ret;
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
718*4882a593Smuzhiyun 	for_each_set_bit(bit, indio_dev->active_scan_mask,
719*4882a593Smuzhiyun 			 indio_dev->masklength)
720*4882a593Smuzhiyun 		__set_bit(indio_dev->channels[bit].channel, &channels);
721*4882a593Smuzhiyun 
722*4882a593Smuzhiyun 	ret = sx9310_update_chan_en(data, channels, data->chan_event);
723*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
724*4882a593Smuzhiyun 	return ret;
725*4882a593Smuzhiyun }
726*4882a593Smuzhiyun 
sx9310_buffer_postdisable(struct iio_dev * indio_dev)727*4882a593Smuzhiyun static int sx9310_buffer_postdisable(struct iio_dev *indio_dev)
728*4882a593Smuzhiyun {
729*4882a593Smuzhiyun 	struct sx9310_data *data = iio_priv(indio_dev);
730*4882a593Smuzhiyun 	int ret;
731*4882a593Smuzhiyun 
732*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
733*4882a593Smuzhiyun 	ret = sx9310_update_chan_en(data, 0, data->chan_event);
734*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
735*4882a593Smuzhiyun 	return ret;
736*4882a593Smuzhiyun }
737*4882a593Smuzhiyun 
738*4882a593Smuzhiyun static const struct iio_buffer_setup_ops sx9310_buffer_setup_ops = {
739*4882a593Smuzhiyun 	.preenable = sx9310_buffer_preenable,
740*4882a593Smuzhiyun 	.postdisable = sx9310_buffer_postdisable,
741*4882a593Smuzhiyun };
742*4882a593Smuzhiyun 
743*4882a593Smuzhiyun struct sx9310_reg_default {
744*4882a593Smuzhiyun 	u8 reg;
745*4882a593Smuzhiyun 	u8 def;
746*4882a593Smuzhiyun };
747*4882a593Smuzhiyun 
748*4882a593Smuzhiyun static const struct sx9310_reg_default sx9310_default_regs[] = {
749*4882a593Smuzhiyun 	{ SX9310_REG_IRQ_MSK, 0x00 },
750*4882a593Smuzhiyun 	{ SX9310_REG_IRQ_FUNC, 0x00 },
751*4882a593Smuzhiyun 	/*
752*4882a593Smuzhiyun 	 * The lower 4 bits should not be set as it enable sensors measurements.
753*4882a593Smuzhiyun 	 * Turning the detection on before the configuration values are set to
754*4882a593Smuzhiyun 	 * good values can cause the device to return erroneous readings.
755*4882a593Smuzhiyun 	 */
756*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL0, SX9310_REG_PROX_CTRL0_SCANPERIOD_15MS },
757*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL1, 0x00 },
758*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL2, SX9310_REG_PROX_CTRL2_COMBMODE_CS1_CS2 |
759*4882a593Smuzhiyun 				 SX9310_REG_PROX_CTRL2_SHIELDEN_DYNAMIC },
760*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL3, SX9310_REG_PROX_CTRL3_GAIN0_X8 |
761*4882a593Smuzhiyun 				 SX9310_REG_PROX_CTRL3_GAIN12_X4 },
762*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL4, SX9310_REG_PROX_CTRL4_RESOLUTION_FINEST },
763*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL5, SX9310_REG_PROX_CTRL5_RANGE_SMALL |
764*4882a593Smuzhiyun 				 SX9310_REG_PROX_CTRL5_STARTUPSENS_CS1 |
765*4882a593Smuzhiyun 				 SX9310_REG_PROX_CTRL5_RAWFILT_1P25 },
766*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL6, SX9310_REG_PROX_CTRL6_AVGTHRESH_DEFAULT },
767*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL7, SX9310_REG_PROX_CTRL7_AVGNEGFILT_2 |
768*4882a593Smuzhiyun 				 SX9310_REG_PROX_CTRL7_AVGPOSFILT_512 },
769*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL8, SX9310_REG_PROX_CTRL8_9_PTHRESH_96 |
770*4882a593Smuzhiyun 				 SX9310_REG_PROX_CTRL8_9_BODYTHRESH_1500 },
771*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL9, SX9310_REG_PROX_CTRL8_9_PTHRESH_28 |
772*4882a593Smuzhiyun 				 SX9310_REG_PROX_CTRL8_9_BODYTHRESH_900 },
773*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL10, SX9310_REG_PROX_CTRL10_HYST_6PCT |
774*4882a593Smuzhiyun 				  SX9310_REG_PROX_CTRL10_FAR_DEBOUNCE_2 },
775*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL11, 0x00 },
776*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL12, 0x00 },
777*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL13, 0x00 },
778*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL14, 0x00 },
779*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL15, 0x00 },
780*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL16, 0x00 },
781*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL17, 0x00 },
782*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL18, 0x00 },
783*4882a593Smuzhiyun 	{ SX9310_REG_PROX_CTRL19, 0x00 },
784*4882a593Smuzhiyun 	{ SX9310_REG_SAR_CTRL0, SX9310_REG_SAR_CTRL0_SARDEB_4_SAMPLES |
785*4882a593Smuzhiyun 				SX9310_REG_SAR_CTRL0_SARHYST_8 },
786*4882a593Smuzhiyun 	{ SX9310_REG_SAR_CTRL1, SX9310_REG_SAR_CTRL1_SLOPE(10781250) },
787*4882a593Smuzhiyun 	{ SX9310_REG_SAR_CTRL2, SX9310_REG_SAR_CTRL2_SAROFFSET_DEFAULT },
788*4882a593Smuzhiyun };
789*4882a593Smuzhiyun 
790*4882a593Smuzhiyun /* Activate all channels and perform an initial compensation. */
sx9310_init_compensation(struct iio_dev * indio_dev)791*4882a593Smuzhiyun static int sx9310_init_compensation(struct iio_dev *indio_dev)
792*4882a593Smuzhiyun {
793*4882a593Smuzhiyun 	struct sx9310_data *data = iio_priv(indio_dev);
794*4882a593Smuzhiyun 	int ret;
795*4882a593Smuzhiyun 	unsigned int val;
796*4882a593Smuzhiyun 	unsigned int ctrl0;
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0, &ctrl0);
799*4882a593Smuzhiyun 	if (ret)
800*4882a593Smuzhiyun 		return ret;
801*4882a593Smuzhiyun 
802*4882a593Smuzhiyun 	/* run the compensation phase on all channels */
803*4882a593Smuzhiyun 	ret = regmap_write(data->regmap, SX9310_REG_PROX_CTRL0,
804*4882a593Smuzhiyun 			   ctrl0 | SX9310_REG_PROX_CTRL0_SENSOREN_MASK);
805*4882a593Smuzhiyun 	if (ret)
806*4882a593Smuzhiyun 		return ret;
807*4882a593Smuzhiyun 
808*4882a593Smuzhiyun 	ret = regmap_read_poll_timeout(data->regmap, SX9310_REG_STAT1, val,
809*4882a593Smuzhiyun 				       !(val & SX9310_REG_STAT1_COMPSTAT_MASK),
810*4882a593Smuzhiyun 				       20000, 2000000);
811*4882a593Smuzhiyun 	if (ret) {
812*4882a593Smuzhiyun 		if (ret == -ETIMEDOUT)
813*4882a593Smuzhiyun 			dev_err(&data->client->dev,
814*4882a593Smuzhiyun 				"initial compensation timed out: 0x%02x\n",
815*4882a593Smuzhiyun 				val);
816*4882a593Smuzhiyun 		return ret;
817*4882a593Smuzhiyun 	}
818*4882a593Smuzhiyun 
819*4882a593Smuzhiyun 	regmap_write(data->regmap, SX9310_REG_PROX_CTRL0, ctrl0);
820*4882a593Smuzhiyun 	return ret;
821*4882a593Smuzhiyun }
822*4882a593Smuzhiyun 
sx9310_init_device(struct iio_dev * indio_dev)823*4882a593Smuzhiyun static int sx9310_init_device(struct iio_dev *indio_dev)
824*4882a593Smuzhiyun {
825*4882a593Smuzhiyun 	struct sx9310_data *data = iio_priv(indio_dev);
826*4882a593Smuzhiyun 	const struct sx9310_reg_default *initval;
827*4882a593Smuzhiyun 	int ret;
828*4882a593Smuzhiyun 	unsigned int i, val;
829*4882a593Smuzhiyun 
830*4882a593Smuzhiyun 	ret = regmap_write(data->regmap, SX9310_REG_RESET, SX9310_SOFT_RESET);
831*4882a593Smuzhiyun 	if (ret)
832*4882a593Smuzhiyun 		return ret;
833*4882a593Smuzhiyun 
834*4882a593Smuzhiyun 	usleep_range(1000, 2000); /* power-up time is ~1ms. */
835*4882a593Smuzhiyun 
836*4882a593Smuzhiyun 	/* Clear reset interrupt state by reading SX9310_REG_IRQ_SRC. */
837*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, SX9310_REG_IRQ_SRC, &val);
838*4882a593Smuzhiyun 	if (ret)
839*4882a593Smuzhiyun 		return ret;
840*4882a593Smuzhiyun 
841*4882a593Smuzhiyun 	/* Program some sane defaults. */
842*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(sx9310_default_regs); i++) {
843*4882a593Smuzhiyun 		initval = &sx9310_default_regs[i];
844*4882a593Smuzhiyun 		ret = regmap_write(data->regmap, initval->reg, initval->def);
845*4882a593Smuzhiyun 		if (ret)
846*4882a593Smuzhiyun 			return ret;
847*4882a593Smuzhiyun 	}
848*4882a593Smuzhiyun 
849*4882a593Smuzhiyun 	return sx9310_init_compensation(indio_dev);
850*4882a593Smuzhiyun }
851*4882a593Smuzhiyun 
sx9310_set_indio_dev_name(struct device * dev,struct iio_dev * indio_dev,unsigned int whoami)852*4882a593Smuzhiyun static int sx9310_set_indio_dev_name(struct device *dev,
853*4882a593Smuzhiyun 				     struct iio_dev *indio_dev,
854*4882a593Smuzhiyun 				     unsigned int whoami)
855*4882a593Smuzhiyun {
856*4882a593Smuzhiyun 	unsigned int long ddata;
857*4882a593Smuzhiyun 
858*4882a593Smuzhiyun 	ddata = (uintptr_t)device_get_match_data(dev);
859*4882a593Smuzhiyun 	if (ddata != whoami) {
860*4882a593Smuzhiyun 		dev_err(dev, "WHOAMI does not match device data: %u\n", whoami);
861*4882a593Smuzhiyun 		return -ENODEV;
862*4882a593Smuzhiyun 	}
863*4882a593Smuzhiyun 
864*4882a593Smuzhiyun 	switch (whoami) {
865*4882a593Smuzhiyun 	case SX9310_WHOAMI_VALUE:
866*4882a593Smuzhiyun 		indio_dev->name = "sx9310";
867*4882a593Smuzhiyun 		break;
868*4882a593Smuzhiyun 	case SX9311_WHOAMI_VALUE:
869*4882a593Smuzhiyun 		indio_dev->name = "sx9311";
870*4882a593Smuzhiyun 		break;
871*4882a593Smuzhiyun 	default:
872*4882a593Smuzhiyun 		dev_err(dev, "unexpected WHOAMI response: %u\n", whoami);
873*4882a593Smuzhiyun 		return -ENODEV;
874*4882a593Smuzhiyun 	}
875*4882a593Smuzhiyun 
876*4882a593Smuzhiyun 	return 0;
877*4882a593Smuzhiyun }
878*4882a593Smuzhiyun 
sx9310_regulator_disable(void * _data)879*4882a593Smuzhiyun static void sx9310_regulator_disable(void *_data)
880*4882a593Smuzhiyun {
881*4882a593Smuzhiyun 	struct sx9310_data *data = _data;
882*4882a593Smuzhiyun 
883*4882a593Smuzhiyun 	regulator_bulk_disable(ARRAY_SIZE(data->supplies), data->supplies);
884*4882a593Smuzhiyun }
885*4882a593Smuzhiyun 
sx9310_probe(struct i2c_client * client)886*4882a593Smuzhiyun static int sx9310_probe(struct i2c_client *client)
887*4882a593Smuzhiyun {
888*4882a593Smuzhiyun 	int ret;
889*4882a593Smuzhiyun 	struct device *dev = &client->dev;
890*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
891*4882a593Smuzhiyun 	struct sx9310_data *data;
892*4882a593Smuzhiyun 
893*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
894*4882a593Smuzhiyun 	if (!indio_dev)
895*4882a593Smuzhiyun 		return -ENOMEM;
896*4882a593Smuzhiyun 
897*4882a593Smuzhiyun 	data = iio_priv(indio_dev);
898*4882a593Smuzhiyun 	data->client = client;
899*4882a593Smuzhiyun 	data->supplies[0].supply = "vdd";
900*4882a593Smuzhiyun 	data->supplies[1].supply = "svdd";
901*4882a593Smuzhiyun 	mutex_init(&data->mutex);
902*4882a593Smuzhiyun 	init_completion(&data->completion);
903*4882a593Smuzhiyun 
904*4882a593Smuzhiyun 	data->regmap = devm_regmap_init_i2c(client, &sx9310_regmap_config);
905*4882a593Smuzhiyun 	if (IS_ERR(data->regmap))
906*4882a593Smuzhiyun 		return PTR_ERR(data->regmap);
907*4882a593Smuzhiyun 
908*4882a593Smuzhiyun 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(data->supplies),
909*4882a593Smuzhiyun 				      data->supplies);
910*4882a593Smuzhiyun 	if (ret)
911*4882a593Smuzhiyun 		return ret;
912*4882a593Smuzhiyun 
913*4882a593Smuzhiyun 	ret = regulator_bulk_enable(ARRAY_SIZE(data->supplies), data->supplies);
914*4882a593Smuzhiyun 	if (ret)
915*4882a593Smuzhiyun 		return ret;
916*4882a593Smuzhiyun 	/* Must wait for Tpor time after initial power up */
917*4882a593Smuzhiyun 	usleep_range(1000, 1100);
918*4882a593Smuzhiyun 
919*4882a593Smuzhiyun 	ret = devm_add_action_or_reset(dev, sx9310_regulator_disable, data);
920*4882a593Smuzhiyun 	if (ret)
921*4882a593Smuzhiyun 		return ret;
922*4882a593Smuzhiyun 
923*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, SX9310_REG_WHOAMI, &data->whoami);
924*4882a593Smuzhiyun 	if (ret) {
925*4882a593Smuzhiyun 		dev_err(dev, "error in reading WHOAMI register: %d", ret);
926*4882a593Smuzhiyun 		return ret;
927*4882a593Smuzhiyun 	}
928*4882a593Smuzhiyun 
929*4882a593Smuzhiyun 	ret = sx9310_set_indio_dev_name(dev, indio_dev, data->whoami);
930*4882a593Smuzhiyun 	if (ret)
931*4882a593Smuzhiyun 		return ret;
932*4882a593Smuzhiyun 
933*4882a593Smuzhiyun 	ACPI_COMPANION_SET(&indio_dev->dev, ACPI_COMPANION(dev));
934*4882a593Smuzhiyun 	indio_dev->channels = sx9310_channels;
935*4882a593Smuzhiyun 	indio_dev->num_channels = ARRAY_SIZE(sx9310_channels);
936*4882a593Smuzhiyun 	indio_dev->info = &sx9310_info;
937*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
938*4882a593Smuzhiyun 	i2c_set_clientdata(client, indio_dev);
939*4882a593Smuzhiyun 
940*4882a593Smuzhiyun 	ret = sx9310_init_device(indio_dev);
941*4882a593Smuzhiyun 	if (ret)
942*4882a593Smuzhiyun 		return ret;
943*4882a593Smuzhiyun 
944*4882a593Smuzhiyun 	if (client->irq) {
945*4882a593Smuzhiyun 		ret = devm_request_threaded_irq(dev, client->irq,
946*4882a593Smuzhiyun 						sx9310_irq_handler,
947*4882a593Smuzhiyun 						sx9310_irq_thread_handler,
948*4882a593Smuzhiyun 						IRQF_ONESHOT,
949*4882a593Smuzhiyun 						"sx9310_event", indio_dev);
950*4882a593Smuzhiyun 		if (ret)
951*4882a593Smuzhiyun 			return ret;
952*4882a593Smuzhiyun 
953*4882a593Smuzhiyun 		data->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
954*4882a593Smuzhiyun 						    indio_dev->name,
955*4882a593Smuzhiyun 						    indio_dev->id);
956*4882a593Smuzhiyun 		if (!data->trig)
957*4882a593Smuzhiyun 			return -ENOMEM;
958*4882a593Smuzhiyun 
959*4882a593Smuzhiyun 		data->trig->dev.parent = dev;
960*4882a593Smuzhiyun 		data->trig->ops = &sx9310_trigger_ops;
961*4882a593Smuzhiyun 		iio_trigger_set_drvdata(data->trig, indio_dev);
962*4882a593Smuzhiyun 
963*4882a593Smuzhiyun 		ret = devm_iio_trigger_register(dev, data->trig);
964*4882a593Smuzhiyun 		if (ret)
965*4882a593Smuzhiyun 			return ret;
966*4882a593Smuzhiyun 	}
967*4882a593Smuzhiyun 
968*4882a593Smuzhiyun 	ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
969*4882a593Smuzhiyun 					      iio_pollfunc_store_time,
970*4882a593Smuzhiyun 					      sx9310_trigger_handler,
971*4882a593Smuzhiyun 					      &sx9310_buffer_setup_ops);
972*4882a593Smuzhiyun 	if (ret)
973*4882a593Smuzhiyun 		return ret;
974*4882a593Smuzhiyun 
975*4882a593Smuzhiyun 	return devm_iio_device_register(dev, indio_dev);
976*4882a593Smuzhiyun }
977*4882a593Smuzhiyun 
sx9310_suspend(struct device * dev)978*4882a593Smuzhiyun static int __maybe_unused sx9310_suspend(struct device *dev)
979*4882a593Smuzhiyun {
980*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
981*4882a593Smuzhiyun 	struct sx9310_data *data = iio_priv(indio_dev);
982*4882a593Smuzhiyun 	u8 ctrl0;
983*4882a593Smuzhiyun 	int ret;
984*4882a593Smuzhiyun 
985*4882a593Smuzhiyun 	disable_irq_nosync(data->client->irq);
986*4882a593Smuzhiyun 
987*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
988*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, SX9310_REG_PROX_CTRL0,
989*4882a593Smuzhiyun 			  &data->suspend_ctrl0);
990*4882a593Smuzhiyun 	if (ret)
991*4882a593Smuzhiyun 		goto out;
992*4882a593Smuzhiyun 
993*4882a593Smuzhiyun 	ctrl0 = data->suspend_ctrl0 & ~SX9310_REG_PROX_CTRL0_SENSOREN_MASK;
994*4882a593Smuzhiyun 	ret = regmap_write(data->regmap, SX9310_REG_PROX_CTRL0, ctrl0);
995*4882a593Smuzhiyun 	if (ret)
996*4882a593Smuzhiyun 		goto out;
997*4882a593Smuzhiyun 
998*4882a593Smuzhiyun 	ret = regmap_write(data->regmap, SX9310_REG_PAUSE, 0);
999*4882a593Smuzhiyun 
1000*4882a593Smuzhiyun out:
1001*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
1002*4882a593Smuzhiyun 	return ret;
1003*4882a593Smuzhiyun }
1004*4882a593Smuzhiyun 
sx9310_resume(struct device * dev)1005*4882a593Smuzhiyun static int __maybe_unused sx9310_resume(struct device *dev)
1006*4882a593Smuzhiyun {
1007*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1008*4882a593Smuzhiyun 	struct sx9310_data *data = iio_priv(indio_dev);
1009*4882a593Smuzhiyun 	int ret;
1010*4882a593Smuzhiyun 
1011*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
1012*4882a593Smuzhiyun 	ret = regmap_write(data->regmap, SX9310_REG_PAUSE, 1);
1013*4882a593Smuzhiyun 	if (ret)
1014*4882a593Smuzhiyun 		goto out;
1015*4882a593Smuzhiyun 
1016*4882a593Smuzhiyun 	ret = regmap_write(data->regmap, SX9310_REG_PROX_CTRL0,
1017*4882a593Smuzhiyun 			   data->suspend_ctrl0);
1018*4882a593Smuzhiyun 
1019*4882a593Smuzhiyun out:
1020*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
1021*4882a593Smuzhiyun 	if (ret)
1022*4882a593Smuzhiyun 		return ret;
1023*4882a593Smuzhiyun 
1024*4882a593Smuzhiyun 	enable_irq(data->client->irq);
1025*4882a593Smuzhiyun 	return 0;
1026*4882a593Smuzhiyun }
1027*4882a593Smuzhiyun 
1028*4882a593Smuzhiyun static const struct dev_pm_ops sx9310_pm_ops = {
1029*4882a593Smuzhiyun 	SET_SYSTEM_SLEEP_PM_OPS(sx9310_suspend, sx9310_resume)
1030*4882a593Smuzhiyun };
1031*4882a593Smuzhiyun 
1032*4882a593Smuzhiyun static const struct acpi_device_id sx9310_acpi_match[] = {
1033*4882a593Smuzhiyun 	{ "STH9310", SX9310_WHOAMI_VALUE },
1034*4882a593Smuzhiyun 	{ "STH9311", SX9311_WHOAMI_VALUE },
1035*4882a593Smuzhiyun 	{}
1036*4882a593Smuzhiyun };
1037*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, sx9310_acpi_match);
1038*4882a593Smuzhiyun 
1039*4882a593Smuzhiyun static const struct of_device_id sx9310_of_match[] = {
1040*4882a593Smuzhiyun 	{ .compatible = "semtech,sx9310", (void *)SX9310_WHOAMI_VALUE },
1041*4882a593Smuzhiyun 	{ .compatible = "semtech,sx9311", (void *)SX9311_WHOAMI_VALUE },
1042*4882a593Smuzhiyun 	{}
1043*4882a593Smuzhiyun };
1044*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sx9310_of_match);
1045*4882a593Smuzhiyun 
1046*4882a593Smuzhiyun static const struct i2c_device_id sx9310_id[] = {
1047*4882a593Smuzhiyun 	{ "sx9310", SX9310_WHOAMI_VALUE },
1048*4882a593Smuzhiyun 	{ "sx9311", SX9311_WHOAMI_VALUE },
1049*4882a593Smuzhiyun 	{}
1050*4882a593Smuzhiyun };
1051*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, sx9310_id);
1052*4882a593Smuzhiyun 
1053*4882a593Smuzhiyun static struct i2c_driver sx9310_driver = {
1054*4882a593Smuzhiyun 	.driver = {
1055*4882a593Smuzhiyun 		.name	= "sx9310",
1056*4882a593Smuzhiyun 		.acpi_match_table = sx9310_acpi_match,
1057*4882a593Smuzhiyun 		.of_match_table = sx9310_of_match,
1058*4882a593Smuzhiyun 		.pm = &sx9310_pm_ops,
1059*4882a593Smuzhiyun 
1060*4882a593Smuzhiyun 		/*
1061*4882a593Smuzhiyun 		 * Lots of i2c transfers in probe + over 200 ms waiting in
1062*4882a593Smuzhiyun 		 * sx9310_init_compensation() mean a slow probe; prefer async
1063*4882a593Smuzhiyun 		 * so we don't delay boot if we're builtin to the kernel.
1064*4882a593Smuzhiyun 		 */
1065*4882a593Smuzhiyun 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
1066*4882a593Smuzhiyun 	},
1067*4882a593Smuzhiyun 	.probe_new	= sx9310_probe,
1068*4882a593Smuzhiyun 	.id_table	= sx9310_id,
1069*4882a593Smuzhiyun };
1070*4882a593Smuzhiyun module_i2c_driver(sx9310_driver);
1071*4882a593Smuzhiyun 
1072*4882a593Smuzhiyun MODULE_AUTHOR("Gwendal Grignou <gwendal@chromium.org>");
1073*4882a593Smuzhiyun MODULE_AUTHOR("Daniel Campello <campello@chromium.org>");
1074*4882a593Smuzhiyun MODULE_DESCRIPTION("Driver for Semtech SX9310/SX9311 proximity sensor");
1075*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1076