xref: /OK3568_Linux_fs/kernel/drivers/iio/pressure/mpl3115.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * mpl3115.c - Support for Freescale MPL3115A2 pressure/temperature sensor
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2013 Peter Meerwald <pmeerw@pmeerw.net>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * (7-bit I2C slave address 0x60)
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * TODO: FIFO buffer, altimeter mode, oversampling, continuous mode,
10*4882a593Smuzhiyun  * interrupts, user offset correction, raw mode
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/iio/iio.h>
16*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
17*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
18*4882a593Smuzhiyun #include <linux/iio/buffer.h>
19*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
20*4882a593Smuzhiyun #include <linux/delay.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #define MPL3115_STATUS 0x00
23*4882a593Smuzhiyun #define MPL3115_OUT_PRESS 0x01 /* MSB first, 20 bit */
24*4882a593Smuzhiyun #define MPL3115_OUT_TEMP 0x04 /* MSB first, 12 bit */
25*4882a593Smuzhiyun #define MPL3115_WHO_AM_I 0x0c
26*4882a593Smuzhiyun #define MPL3115_CTRL_REG1 0x26
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define MPL3115_DEVICE_ID 0xc4
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define MPL3115_STATUS_PRESS_RDY BIT(2)
31*4882a593Smuzhiyun #define MPL3115_STATUS_TEMP_RDY BIT(1)
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define MPL3115_CTRL_RESET BIT(2) /* software reset */
34*4882a593Smuzhiyun #define MPL3115_CTRL_OST BIT(1) /* initiate measurement */
35*4882a593Smuzhiyun #define MPL3115_CTRL_ACTIVE BIT(0) /* continuous measurement */
36*4882a593Smuzhiyun #define MPL3115_CTRL_OS_258MS (BIT(5) | BIT(4)) /* 64x oversampling */
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun struct mpl3115_data {
39*4882a593Smuzhiyun 	struct i2c_client *client;
40*4882a593Smuzhiyun 	struct mutex lock;
41*4882a593Smuzhiyun 	u8 ctrl_reg1;
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun 
mpl3115_request(struct mpl3115_data * data)44*4882a593Smuzhiyun static int mpl3115_request(struct mpl3115_data *data)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun 	int ret, tries = 15;
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun 	/* trigger measurement */
49*4882a593Smuzhiyun 	ret = i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG1,
50*4882a593Smuzhiyun 		data->ctrl_reg1 | MPL3115_CTRL_OST);
51*4882a593Smuzhiyun 	if (ret < 0)
52*4882a593Smuzhiyun 		return ret;
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun 	while (tries-- > 0) {
55*4882a593Smuzhiyun 		ret = i2c_smbus_read_byte_data(data->client, MPL3115_CTRL_REG1);
56*4882a593Smuzhiyun 		if (ret < 0)
57*4882a593Smuzhiyun 			return ret;
58*4882a593Smuzhiyun 		/* wait for data ready, i.e. OST cleared */
59*4882a593Smuzhiyun 		if (!(ret & MPL3115_CTRL_OST))
60*4882a593Smuzhiyun 			break;
61*4882a593Smuzhiyun 		msleep(20);
62*4882a593Smuzhiyun 	}
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	if (tries < 0) {
65*4882a593Smuzhiyun 		dev_err(&data->client->dev, "data not ready\n");
66*4882a593Smuzhiyun 		return -EIO;
67*4882a593Smuzhiyun 	}
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun 	return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun 
mpl3115_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)72*4882a593Smuzhiyun static int mpl3115_read_raw(struct iio_dev *indio_dev,
73*4882a593Smuzhiyun 			    struct iio_chan_spec const *chan,
74*4882a593Smuzhiyun 			    int *val, int *val2, long mask)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun 	struct mpl3115_data *data = iio_priv(indio_dev);
77*4882a593Smuzhiyun 	__be32 tmp = 0;
78*4882a593Smuzhiyun 	int ret;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	switch (mask) {
81*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
82*4882a593Smuzhiyun 		ret = iio_device_claim_direct_mode(indio_dev);
83*4882a593Smuzhiyun 		if (ret)
84*4882a593Smuzhiyun 			return ret;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 		switch (chan->type) {
87*4882a593Smuzhiyun 		case IIO_PRESSURE: /* in 0.25 pascal / LSB */
88*4882a593Smuzhiyun 			mutex_lock(&data->lock);
89*4882a593Smuzhiyun 			ret = mpl3115_request(data);
90*4882a593Smuzhiyun 			if (ret < 0) {
91*4882a593Smuzhiyun 				mutex_unlock(&data->lock);
92*4882a593Smuzhiyun 				break;
93*4882a593Smuzhiyun 			}
94*4882a593Smuzhiyun 			ret = i2c_smbus_read_i2c_block_data(data->client,
95*4882a593Smuzhiyun 				MPL3115_OUT_PRESS, 3, (u8 *) &tmp);
96*4882a593Smuzhiyun 			mutex_unlock(&data->lock);
97*4882a593Smuzhiyun 			if (ret < 0)
98*4882a593Smuzhiyun 				break;
99*4882a593Smuzhiyun 			*val = be32_to_cpu(tmp) >> 12;
100*4882a593Smuzhiyun 			ret = IIO_VAL_INT;
101*4882a593Smuzhiyun 			break;
102*4882a593Smuzhiyun 		case IIO_TEMP: /* in 0.0625 celsius / LSB */
103*4882a593Smuzhiyun 			mutex_lock(&data->lock);
104*4882a593Smuzhiyun 			ret = mpl3115_request(data);
105*4882a593Smuzhiyun 			if (ret < 0) {
106*4882a593Smuzhiyun 				mutex_unlock(&data->lock);
107*4882a593Smuzhiyun 				break;
108*4882a593Smuzhiyun 			}
109*4882a593Smuzhiyun 			ret = i2c_smbus_read_i2c_block_data(data->client,
110*4882a593Smuzhiyun 				MPL3115_OUT_TEMP, 2, (u8 *) &tmp);
111*4882a593Smuzhiyun 			mutex_unlock(&data->lock);
112*4882a593Smuzhiyun 			if (ret < 0)
113*4882a593Smuzhiyun 				break;
114*4882a593Smuzhiyun 			*val = sign_extend32(be32_to_cpu(tmp) >> 20, 11);
115*4882a593Smuzhiyun 			ret = IIO_VAL_INT;
116*4882a593Smuzhiyun 			break;
117*4882a593Smuzhiyun 		default:
118*4882a593Smuzhiyun 			ret = -EINVAL;
119*4882a593Smuzhiyun 			break;
120*4882a593Smuzhiyun 		}
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 		iio_device_release_direct_mode(indio_dev);
123*4882a593Smuzhiyun 		return ret;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
126*4882a593Smuzhiyun 		switch (chan->type) {
127*4882a593Smuzhiyun 		case IIO_PRESSURE:
128*4882a593Smuzhiyun 			*val = 0;
129*4882a593Smuzhiyun 			*val2 = 250; /* want kilopascal */
130*4882a593Smuzhiyun 			return IIO_VAL_INT_PLUS_MICRO;
131*4882a593Smuzhiyun 		case IIO_TEMP:
132*4882a593Smuzhiyun 			*val = 0;
133*4882a593Smuzhiyun 			*val2 = 62500;
134*4882a593Smuzhiyun 			return IIO_VAL_INT_PLUS_MICRO;
135*4882a593Smuzhiyun 		default:
136*4882a593Smuzhiyun 			return -EINVAL;
137*4882a593Smuzhiyun 		}
138*4882a593Smuzhiyun 	}
139*4882a593Smuzhiyun 	return -EINVAL;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
mpl3115_trigger_handler(int irq,void * p)142*4882a593Smuzhiyun static irqreturn_t mpl3115_trigger_handler(int irq, void *p)
143*4882a593Smuzhiyun {
144*4882a593Smuzhiyun 	struct iio_poll_func *pf = p;
145*4882a593Smuzhiyun 	struct iio_dev *indio_dev = pf->indio_dev;
146*4882a593Smuzhiyun 	struct mpl3115_data *data = iio_priv(indio_dev);
147*4882a593Smuzhiyun 	/*
148*4882a593Smuzhiyun 	 * 32-bit channel + 16-bit channel + padding + ts
149*4882a593Smuzhiyun 	 * Note that it is possible for only one of the first 2
150*4882a593Smuzhiyun 	 * channels to be enabled. If that happens, the first element
151*4882a593Smuzhiyun 	 * of the buffer may be either 16 or 32-bits.  As such we cannot
152*4882a593Smuzhiyun 	 * use a simple structure definition to express this data layout.
153*4882a593Smuzhiyun 	 */
154*4882a593Smuzhiyun 	u8 buffer[16] __aligned(8);
155*4882a593Smuzhiyun 	int ret, pos = 0;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	mutex_lock(&data->lock);
158*4882a593Smuzhiyun 	ret = mpl3115_request(data);
159*4882a593Smuzhiyun 	if (ret < 0) {
160*4882a593Smuzhiyun 		mutex_unlock(&data->lock);
161*4882a593Smuzhiyun 		goto done;
162*4882a593Smuzhiyun 	}
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	memset(buffer, 0, sizeof(buffer));
165*4882a593Smuzhiyun 	if (test_bit(0, indio_dev->active_scan_mask)) {
166*4882a593Smuzhiyun 		ret = i2c_smbus_read_i2c_block_data(data->client,
167*4882a593Smuzhiyun 			MPL3115_OUT_PRESS, 3, &buffer[pos]);
168*4882a593Smuzhiyun 		if (ret < 0) {
169*4882a593Smuzhiyun 			mutex_unlock(&data->lock);
170*4882a593Smuzhiyun 			goto done;
171*4882a593Smuzhiyun 		}
172*4882a593Smuzhiyun 		pos += 4;
173*4882a593Smuzhiyun 	}
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	if (test_bit(1, indio_dev->active_scan_mask)) {
176*4882a593Smuzhiyun 		ret = i2c_smbus_read_i2c_block_data(data->client,
177*4882a593Smuzhiyun 			MPL3115_OUT_TEMP, 2, &buffer[pos]);
178*4882a593Smuzhiyun 		if (ret < 0) {
179*4882a593Smuzhiyun 			mutex_unlock(&data->lock);
180*4882a593Smuzhiyun 			goto done;
181*4882a593Smuzhiyun 		}
182*4882a593Smuzhiyun 	}
183*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 	iio_push_to_buffers_with_timestamp(indio_dev, buffer,
186*4882a593Smuzhiyun 		iio_get_time_ns(indio_dev));
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun done:
189*4882a593Smuzhiyun 	iio_trigger_notify_done(indio_dev->trig);
190*4882a593Smuzhiyun 	return IRQ_HANDLED;
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun 
193*4882a593Smuzhiyun static const struct iio_chan_spec mpl3115_channels[] = {
194*4882a593Smuzhiyun 	{
195*4882a593Smuzhiyun 		.type = IIO_PRESSURE,
196*4882a593Smuzhiyun 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
197*4882a593Smuzhiyun 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
198*4882a593Smuzhiyun 		.scan_index = 0,
199*4882a593Smuzhiyun 		.scan_type = {
200*4882a593Smuzhiyun 			.sign = 'u',
201*4882a593Smuzhiyun 			.realbits = 20,
202*4882a593Smuzhiyun 			.storagebits = 32,
203*4882a593Smuzhiyun 			.shift = 12,
204*4882a593Smuzhiyun 			.endianness = IIO_BE,
205*4882a593Smuzhiyun 		}
206*4882a593Smuzhiyun 	},
207*4882a593Smuzhiyun 	{
208*4882a593Smuzhiyun 		.type = IIO_TEMP,
209*4882a593Smuzhiyun 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
210*4882a593Smuzhiyun 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
211*4882a593Smuzhiyun 		.scan_index = 1,
212*4882a593Smuzhiyun 		.scan_type = {
213*4882a593Smuzhiyun 			.sign = 's',
214*4882a593Smuzhiyun 			.realbits = 12,
215*4882a593Smuzhiyun 			.storagebits = 16,
216*4882a593Smuzhiyun 			.shift = 4,
217*4882a593Smuzhiyun 			.endianness = IIO_BE,
218*4882a593Smuzhiyun 		}
219*4882a593Smuzhiyun 	},
220*4882a593Smuzhiyun 	IIO_CHAN_SOFT_TIMESTAMP(2),
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun static const struct iio_info mpl3115_info = {
224*4882a593Smuzhiyun 	.read_raw = &mpl3115_read_raw,
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun 
mpl3115_probe(struct i2c_client * client,const struct i2c_device_id * id)227*4882a593Smuzhiyun static int mpl3115_probe(struct i2c_client *client,
228*4882a593Smuzhiyun 			 const struct i2c_device_id *id)
229*4882a593Smuzhiyun {
230*4882a593Smuzhiyun 	struct mpl3115_data *data;
231*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
232*4882a593Smuzhiyun 	int ret;
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(client, MPL3115_WHO_AM_I);
235*4882a593Smuzhiyun 	if (ret < 0)
236*4882a593Smuzhiyun 		return ret;
237*4882a593Smuzhiyun 	if (ret != MPL3115_DEVICE_ID)
238*4882a593Smuzhiyun 		return -ENODEV;
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
241*4882a593Smuzhiyun 	if (!indio_dev)
242*4882a593Smuzhiyun 		return -ENOMEM;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	data = iio_priv(indio_dev);
245*4882a593Smuzhiyun 	data->client = client;
246*4882a593Smuzhiyun 	mutex_init(&data->lock);
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	i2c_set_clientdata(client, indio_dev);
249*4882a593Smuzhiyun 	indio_dev->info = &mpl3115_info;
250*4882a593Smuzhiyun 	indio_dev->name = id->name;
251*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
252*4882a593Smuzhiyun 	indio_dev->channels = mpl3115_channels;
253*4882a593Smuzhiyun 	indio_dev->num_channels = ARRAY_SIZE(mpl3115_channels);
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	/* software reset, I2C transfer is aborted (fails) */
256*4882a593Smuzhiyun 	i2c_smbus_write_byte_data(client, MPL3115_CTRL_REG1,
257*4882a593Smuzhiyun 		MPL3115_CTRL_RESET);
258*4882a593Smuzhiyun 	msleep(50);
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun 	data->ctrl_reg1 = MPL3115_CTRL_OS_258MS;
261*4882a593Smuzhiyun 	ret = i2c_smbus_write_byte_data(client, MPL3115_CTRL_REG1,
262*4882a593Smuzhiyun 		data->ctrl_reg1);
263*4882a593Smuzhiyun 	if (ret < 0)
264*4882a593Smuzhiyun 		return ret;
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	ret = iio_triggered_buffer_setup(indio_dev, NULL,
267*4882a593Smuzhiyun 		mpl3115_trigger_handler, NULL);
268*4882a593Smuzhiyun 	if (ret < 0)
269*4882a593Smuzhiyun 		return ret;
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	ret = iio_device_register(indio_dev);
272*4882a593Smuzhiyun 	if (ret < 0)
273*4882a593Smuzhiyun 		goto buffer_cleanup;
274*4882a593Smuzhiyun 	return 0;
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun buffer_cleanup:
277*4882a593Smuzhiyun 	iio_triggered_buffer_cleanup(indio_dev);
278*4882a593Smuzhiyun 	return ret;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun 
mpl3115_standby(struct mpl3115_data * data)281*4882a593Smuzhiyun static int mpl3115_standby(struct mpl3115_data *data)
282*4882a593Smuzhiyun {
283*4882a593Smuzhiyun 	return i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG1,
284*4882a593Smuzhiyun 		data->ctrl_reg1 & ~MPL3115_CTRL_ACTIVE);
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun 
mpl3115_remove(struct i2c_client * client)287*4882a593Smuzhiyun static int mpl3115_remove(struct i2c_client *client)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
292*4882a593Smuzhiyun 	iio_triggered_buffer_cleanup(indio_dev);
293*4882a593Smuzhiyun 	mpl3115_standby(iio_priv(indio_dev));
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	return 0;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
mpl3115_suspend(struct device * dev)299*4882a593Smuzhiyun static int mpl3115_suspend(struct device *dev)
300*4882a593Smuzhiyun {
301*4882a593Smuzhiyun 	return mpl3115_standby(iio_priv(i2c_get_clientdata(
302*4882a593Smuzhiyun 		to_i2c_client(dev))));
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun 
mpl3115_resume(struct device * dev)305*4882a593Smuzhiyun static int mpl3115_resume(struct device *dev)
306*4882a593Smuzhiyun {
307*4882a593Smuzhiyun 	struct mpl3115_data *data = iio_priv(i2c_get_clientdata(
308*4882a593Smuzhiyun 		to_i2c_client(dev)));
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	return i2c_smbus_write_byte_data(data->client, MPL3115_CTRL_REG1,
311*4882a593Smuzhiyun 		data->ctrl_reg1);
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun 
314*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(mpl3115_pm_ops, mpl3115_suspend, mpl3115_resume);
315*4882a593Smuzhiyun #define MPL3115_PM_OPS (&mpl3115_pm_ops)
316*4882a593Smuzhiyun #else
317*4882a593Smuzhiyun #define MPL3115_PM_OPS NULL
318*4882a593Smuzhiyun #endif
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun static const struct i2c_device_id mpl3115_id[] = {
321*4882a593Smuzhiyun 	{ "mpl3115", 0 },
322*4882a593Smuzhiyun 	{ }
323*4882a593Smuzhiyun };
324*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, mpl3115_id);
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun static const struct of_device_id mpl3115_of_match[] = {
327*4882a593Smuzhiyun 	{ .compatible = "fsl,mpl3115" },
328*4882a593Smuzhiyun 	{ }
329*4882a593Smuzhiyun };
330*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mpl3115_of_match);
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun static struct i2c_driver mpl3115_driver = {
333*4882a593Smuzhiyun 	.driver = {
334*4882a593Smuzhiyun 		.name	= "mpl3115",
335*4882a593Smuzhiyun 		.of_match_table = mpl3115_of_match,
336*4882a593Smuzhiyun 		.pm	= MPL3115_PM_OPS,
337*4882a593Smuzhiyun 	},
338*4882a593Smuzhiyun 	.probe = mpl3115_probe,
339*4882a593Smuzhiyun 	.remove = mpl3115_remove,
340*4882a593Smuzhiyun 	.id_table = mpl3115_id,
341*4882a593Smuzhiyun };
342*4882a593Smuzhiyun module_i2c_driver(mpl3115_driver);
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
345*4882a593Smuzhiyun MODULE_DESCRIPTION("Freescale MPL3115 pressure/temperature driver");
346*4882a593Smuzhiyun MODULE_LICENSE("GPL");
347