1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * All Sensors DLH series low voltage digital pressure sensors
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2019 AVL DiTEST GmbH
6*4882a593Smuzhiyun * Tomislav Denis <tomislav.denis@avl.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Datasheet: https://www.allsensors.com/cad/DS-0355_Rev_B.PDF
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/iio/iio.h>
15*4882a593Smuzhiyun #include <linux/iio/buffer.h>
16*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
17*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
18*4882a593Smuzhiyun #include <asm/unaligned.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun /* Commands */
21*4882a593Smuzhiyun #define DLH_START_SINGLE 0xAA
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun /* Status bits */
24*4882a593Smuzhiyun #define DLH_STATUS_OK 0x40
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /* DLH data format */
27*4882a593Smuzhiyun #define DLH_NUM_READ_BYTES 7
28*4882a593Smuzhiyun #define DLH_NUM_DATA_BYTES 3
29*4882a593Smuzhiyun #define DLH_NUM_PR_BITS 24
30*4882a593Smuzhiyun #define DLH_NUM_TEMP_BITS 24
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun /* DLH timings */
33*4882a593Smuzhiyun #define DLH_SINGLE_DUT_MS 5
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun enum dhl_ids {
36*4882a593Smuzhiyun dlhl60d,
37*4882a593Smuzhiyun dlhl60g,
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun struct dlh_info {
41*4882a593Smuzhiyun u8 osdig; /* digital offset factor */
42*4882a593Smuzhiyun unsigned int fss; /* full scale span (inch H2O) */
43*4882a593Smuzhiyun };
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun struct dlh_state {
46*4882a593Smuzhiyun struct i2c_client *client;
47*4882a593Smuzhiyun struct dlh_info info;
48*4882a593Smuzhiyun bool use_interrupt;
49*4882a593Smuzhiyun struct completion completion;
50*4882a593Smuzhiyun u8 rx_buf[DLH_NUM_READ_BYTES] ____cacheline_aligned;
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun static struct dlh_info dlh_info_tbl[] = {
54*4882a593Smuzhiyun [dlhl60d] = {
55*4882a593Smuzhiyun .osdig = 2,
56*4882a593Smuzhiyun .fss = 120,
57*4882a593Smuzhiyun },
58*4882a593Smuzhiyun [dlhl60g] = {
59*4882a593Smuzhiyun .osdig = 10,
60*4882a593Smuzhiyun .fss = 60,
61*4882a593Smuzhiyun },
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun
dlh_cmd_start_single(struct dlh_state * st)65*4882a593Smuzhiyun static int dlh_cmd_start_single(struct dlh_state *st)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun int ret;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun ret = i2c_smbus_write_byte(st->client, DLH_START_SINGLE);
70*4882a593Smuzhiyun if (ret)
71*4882a593Smuzhiyun dev_err(&st->client->dev,
72*4882a593Smuzhiyun "%s: I2C write byte failed\n", __func__);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun return ret;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
dlh_cmd_read_data(struct dlh_state * st)77*4882a593Smuzhiyun static int dlh_cmd_read_data(struct dlh_state *st)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun int ret;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun ret = i2c_master_recv(st->client, st->rx_buf, DLH_NUM_READ_BYTES);
82*4882a593Smuzhiyun if (ret < 0) {
83*4882a593Smuzhiyun dev_err(&st->client->dev,
84*4882a593Smuzhiyun "%s: I2C read block failed\n", __func__);
85*4882a593Smuzhiyun return ret;
86*4882a593Smuzhiyun }
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun if (st->rx_buf[0] != DLH_STATUS_OK) {
89*4882a593Smuzhiyun dev_err(&st->client->dev,
90*4882a593Smuzhiyun "%s: invalid status 0x%02x\n", __func__, st->rx_buf[0]);
91*4882a593Smuzhiyun return -EBUSY;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun return 0;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
dlh_start_capture_and_read(struct dlh_state * st)97*4882a593Smuzhiyun static int dlh_start_capture_and_read(struct dlh_state *st)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun int ret;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun if (st->use_interrupt)
102*4882a593Smuzhiyun reinit_completion(&st->completion);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun ret = dlh_cmd_start_single(st);
105*4882a593Smuzhiyun if (ret)
106*4882a593Smuzhiyun return ret;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun if (st->use_interrupt) {
109*4882a593Smuzhiyun ret = wait_for_completion_timeout(&st->completion,
110*4882a593Smuzhiyun msecs_to_jiffies(DLH_SINGLE_DUT_MS));
111*4882a593Smuzhiyun if (!ret) {
112*4882a593Smuzhiyun dev_err(&st->client->dev,
113*4882a593Smuzhiyun "%s: conversion timed out\n", __func__);
114*4882a593Smuzhiyun return -ETIMEDOUT;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun } else {
117*4882a593Smuzhiyun mdelay(DLH_SINGLE_DUT_MS);
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun return dlh_cmd_read_data(st);
121*4882a593Smuzhiyun }
122*4882a593Smuzhiyun
dlh_read_direct(struct dlh_state * st,unsigned int * pressure,unsigned int * temperature)123*4882a593Smuzhiyun static int dlh_read_direct(struct dlh_state *st,
124*4882a593Smuzhiyun unsigned int *pressure, unsigned int *temperature)
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun int ret;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun ret = dlh_start_capture_and_read(st);
129*4882a593Smuzhiyun if (ret)
130*4882a593Smuzhiyun return ret;
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun *pressure = get_unaligned_be32(&st->rx_buf[1]) >> 8;
133*4882a593Smuzhiyun *temperature = get_unaligned_be32(&st->rx_buf[3]) &
134*4882a593Smuzhiyun GENMASK(DLH_NUM_TEMP_BITS - 1, 0);
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun return 0;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun
dlh_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * channel,int * value,int * value2,long mask)139*4882a593Smuzhiyun static int dlh_read_raw(struct iio_dev *indio_dev,
140*4882a593Smuzhiyun struct iio_chan_spec const *channel, int *value,
141*4882a593Smuzhiyun int *value2, long mask)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun struct dlh_state *st = iio_priv(indio_dev);
144*4882a593Smuzhiyun unsigned int pressure, temperature;
145*4882a593Smuzhiyun int ret;
146*4882a593Smuzhiyun s64 tmp;
147*4882a593Smuzhiyun s32 rem;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun switch (mask) {
150*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
151*4882a593Smuzhiyun ret = iio_device_claim_direct_mode(indio_dev);
152*4882a593Smuzhiyun if (ret)
153*4882a593Smuzhiyun return ret;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun ret = dlh_read_direct(st, &pressure, &temperature);
156*4882a593Smuzhiyun iio_device_release_direct_mode(indio_dev);
157*4882a593Smuzhiyun if (ret)
158*4882a593Smuzhiyun return ret;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun switch (channel->type) {
161*4882a593Smuzhiyun case IIO_PRESSURE:
162*4882a593Smuzhiyun *value = pressure;
163*4882a593Smuzhiyun return IIO_VAL_INT;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun case IIO_TEMP:
166*4882a593Smuzhiyun *value = temperature;
167*4882a593Smuzhiyun return IIO_VAL_INT;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun default:
170*4882a593Smuzhiyun return -EINVAL;
171*4882a593Smuzhiyun }
172*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
173*4882a593Smuzhiyun switch (channel->type) {
174*4882a593Smuzhiyun case IIO_PRESSURE:
175*4882a593Smuzhiyun tmp = div_s64(125LL * st->info.fss * 24909 * 100,
176*4882a593Smuzhiyun 1 << DLH_NUM_PR_BITS);
177*4882a593Smuzhiyun tmp = div_s64_rem(tmp, 1000000000LL, &rem);
178*4882a593Smuzhiyun *value = tmp;
179*4882a593Smuzhiyun *value2 = rem;
180*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_NANO;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun case IIO_TEMP:
183*4882a593Smuzhiyun *value = 125 * 1000;
184*4882a593Smuzhiyun *value2 = DLH_NUM_TEMP_BITS;
185*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL_LOG2;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun default:
188*4882a593Smuzhiyun return -EINVAL;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun case IIO_CHAN_INFO_OFFSET:
191*4882a593Smuzhiyun switch (channel->type) {
192*4882a593Smuzhiyun case IIO_PRESSURE:
193*4882a593Smuzhiyun *value = -125 * st->info.fss * 24909;
194*4882a593Smuzhiyun *value2 = 100 * st->info.osdig * 100000;
195*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun case IIO_TEMP:
198*4882a593Smuzhiyun *value = -40 * 1000;
199*4882a593Smuzhiyun return IIO_VAL_INT;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun default:
202*4882a593Smuzhiyun return -EINVAL;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun return -EINVAL;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun static const struct iio_info dlh_info = {
210*4882a593Smuzhiyun .read_raw = dlh_read_raw,
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun static const struct iio_chan_spec dlh_channels[] = {
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun .type = IIO_PRESSURE,
216*4882a593Smuzhiyun .indexed = 1,
217*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
218*4882a593Smuzhiyun .info_mask_shared_by_type =
219*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE) |
220*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_OFFSET),
221*4882a593Smuzhiyun .scan_index = 0,
222*4882a593Smuzhiyun .scan_type = {
223*4882a593Smuzhiyun .sign = 'u',
224*4882a593Smuzhiyun .realbits = DLH_NUM_PR_BITS,
225*4882a593Smuzhiyun .storagebits = 32,
226*4882a593Smuzhiyun .shift = 8,
227*4882a593Smuzhiyun .endianness = IIO_BE,
228*4882a593Smuzhiyun },
229*4882a593Smuzhiyun }, {
230*4882a593Smuzhiyun .type = IIO_TEMP,
231*4882a593Smuzhiyun .indexed = 1,
232*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
233*4882a593Smuzhiyun .info_mask_shared_by_type =
234*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE) |
235*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_OFFSET),
236*4882a593Smuzhiyun .scan_index = 1,
237*4882a593Smuzhiyun .scan_type = {
238*4882a593Smuzhiyun .sign = 'u',
239*4882a593Smuzhiyun .realbits = DLH_NUM_TEMP_BITS,
240*4882a593Smuzhiyun .storagebits = 32,
241*4882a593Smuzhiyun .shift = 8,
242*4882a593Smuzhiyun .endianness = IIO_BE,
243*4882a593Smuzhiyun },
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun
dlh_trigger_handler(int irq,void * private)247*4882a593Smuzhiyun static irqreturn_t dlh_trigger_handler(int irq, void *private)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun struct iio_poll_func *pf = private;
250*4882a593Smuzhiyun struct iio_dev *indio_dev = pf->indio_dev;
251*4882a593Smuzhiyun struct dlh_state *st = iio_priv(indio_dev);
252*4882a593Smuzhiyun int ret;
253*4882a593Smuzhiyun unsigned int chn, i = 0;
254*4882a593Smuzhiyun __be32 tmp_buf[2];
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun ret = dlh_start_capture_and_read(st);
257*4882a593Smuzhiyun if (ret)
258*4882a593Smuzhiyun goto out;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun for_each_set_bit(chn, indio_dev->active_scan_mask,
261*4882a593Smuzhiyun indio_dev->masklength) {
262*4882a593Smuzhiyun memcpy(tmp_buf + i,
263*4882a593Smuzhiyun &st->rx_buf[1] + chn * DLH_NUM_DATA_BYTES,
264*4882a593Smuzhiyun DLH_NUM_DATA_BYTES);
265*4882a593Smuzhiyun i++;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun iio_push_to_buffers(indio_dev, tmp_buf);
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun out:
271*4882a593Smuzhiyun iio_trigger_notify_done(indio_dev->trig);
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun return IRQ_HANDLED;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun
dlh_interrupt(int irq,void * private)276*4882a593Smuzhiyun static irqreturn_t dlh_interrupt(int irq, void *private)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun struct iio_dev *indio_dev = private;
279*4882a593Smuzhiyun struct dlh_state *st = iio_priv(indio_dev);
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun complete(&st->completion);
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun return IRQ_HANDLED;
284*4882a593Smuzhiyun };
285*4882a593Smuzhiyun
dlh_probe(struct i2c_client * client,const struct i2c_device_id * id)286*4882a593Smuzhiyun static int dlh_probe(struct i2c_client *client,
287*4882a593Smuzhiyun const struct i2c_device_id *id)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun struct dlh_state *st;
290*4882a593Smuzhiyun struct iio_dev *indio_dev;
291*4882a593Smuzhiyun int ret;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun if (!i2c_check_functionality(client->adapter,
294*4882a593Smuzhiyun I2C_FUNC_I2C | I2C_FUNC_SMBUS_WRITE_BYTE)) {
295*4882a593Smuzhiyun dev_err(&client->dev,
296*4882a593Smuzhiyun "adapter doesn't support required i2c functionality\n");
297*4882a593Smuzhiyun return -EOPNOTSUPP;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
301*4882a593Smuzhiyun if (!indio_dev) {
302*4882a593Smuzhiyun dev_err(&client->dev, "failed to allocate iio device\n");
303*4882a593Smuzhiyun return -ENOMEM;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun i2c_set_clientdata(client, indio_dev);
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun st = iio_priv(indio_dev);
309*4882a593Smuzhiyun st->info = dlh_info_tbl[id->driver_data];
310*4882a593Smuzhiyun st->client = client;
311*4882a593Smuzhiyun st->use_interrupt = false;
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun indio_dev->name = id->name;
314*4882a593Smuzhiyun indio_dev->info = &dlh_info;
315*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
316*4882a593Smuzhiyun indio_dev->channels = dlh_channels;
317*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(dlh_channels);
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun if (client->irq > 0) {
320*4882a593Smuzhiyun ret = devm_request_threaded_irq(&client->dev, client->irq,
321*4882a593Smuzhiyun dlh_interrupt, NULL,
322*4882a593Smuzhiyun IRQF_TRIGGER_RISING | IRQF_ONESHOT,
323*4882a593Smuzhiyun id->name, indio_dev);
324*4882a593Smuzhiyun if (ret) {
325*4882a593Smuzhiyun dev_err(&client->dev, "failed to allocate threaded irq");
326*4882a593Smuzhiyun return ret;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun st->use_interrupt = true;
330*4882a593Smuzhiyun init_completion(&st->completion);
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev,
334*4882a593Smuzhiyun NULL, &dlh_trigger_handler, NULL);
335*4882a593Smuzhiyun if (ret) {
336*4882a593Smuzhiyun dev_err(&client->dev, "failed to setup iio buffer\n");
337*4882a593Smuzhiyun return ret;
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun ret = devm_iio_device_register(&client->dev, indio_dev);
341*4882a593Smuzhiyun if (ret)
342*4882a593Smuzhiyun dev_err(&client->dev, "failed to register iio device\n");
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun return ret;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun static const struct of_device_id dlh_of_match[] = {
348*4882a593Smuzhiyun { .compatible = "asc,dlhl60d" },
349*4882a593Smuzhiyun { .compatible = "asc,dlhl60g" },
350*4882a593Smuzhiyun {}
351*4882a593Smuzhiyun };
352*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, dlh_of_match);
353*4882a593Smuzhiyun
354*4882a593Smuzhiyun static const struct i2c_device_id dlh_id[] = {
355*4882a593Smuzhiyun { "dlhl60d", dlhl60d },
356*4882a593Smuzhiyun { "dlhl60g", dlhl60g },
357*4882a593Smuzhiyun {}
358*4882a593Smuzhiyun };
359*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, dlh_id);
360*4882a593Smuzhiyun
361*4882a593Smuzhiyun static struct i2c_driver dlh_driver = {
362*4882a593Smuzhiyun .driver = {
363*4882a593Smuzhiyun .name = "dlhl60d",
364*4882a593Smuzhiyun .of_match_table = dlh_of_match,
365*4882a593Smuzhiyun },
366*4882a593Smuzhiyun .probe = dlh_probe,
367*4882a593Smuzhiyun .id_table = dlh_id,
368*4882a593Smuzhiyun };
369*4882a593Smuzhiyun module_i2c_driver(dlh_driver);
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun MODULE_AUTHOR("Tomislav Denis <tomislav.denis@avl.com>");
372*4882a593Smuzhiyun MODULE_DESCRIPTION("Driver for All Sensors DLH series pressure sensors");
373*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
374