xref: /OK3568_Linux_fs/kernel/drivers/iio/potentiometer/mcp4131.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Industrial I/O driver for Microchip digital potentiometers
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2016 Slawomir Stepien
6*4882a593Smuzhiyun  * Based on: Peter Rosin's code from mcp4531.c
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Datasheet: https://ww1.microchip.com/downloads/en/DeviceDoc/22060b.pdf
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * DEVID	#Wipers	#Positions	Resistor Opts (kOhm)
11*4882a593Smuzhiyun  * mcp4131	1	129		5, 10, 50, 100
12*4882a593Smuzhiyun  * mcp4132	1	129		5, 10, 50, 100
13*4882a593Smuzhiyun  * mcp4141	1	129		5, 10, 50, 100
14*4882a593Smuzhiyun  * mcp4142	1	129		5, 10, 50, 100
15*4882a593Smuzhiyun  * mcp4151	1	257		5, 10, 50, 100
16*4882a593Smuzhiyun  * mcp4152	1	257		5, 10, 50, 100
17*4882a593Smuzhiyun  * mcp4161	1	257		5, 10, 50, 100
18*4882a593Smuzhiyun  * mcp4162	1	257		5, 10, 50, 100
19*4882a593Smuzhiyun  * mcp4231	2	129		5, 10, 50, 100
20*4882a593Smuzhiyun  * mcp4232	2	129		5, 10, 50, 100
21*4882a593Smuzhiyun  * mcp4241	2	129		5, 10, 50, 100
22*4882a593Smuzhiyun  * mcp4242	2	129		5, 10, 50, 100
23*4882a593Smuzhiyun  * mcp4251	2	257		5, 10, 50, 100
24*4882a593Smuzhiyun  * mcp4252	2	257		5, 10, 50, 100
25*4882a593Smuzhiyun  * mcp4261	2	257		5, 10, 50, 100
26*4882a593Smuzhiyun  * mcp4262	2	257		5, 10, 50, 100
27*4882a593Smuzhiyun  */
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /*
30*4882a593Smuzhiyun  * TODO:
31*4882a593Smuzhiyun  * 1. Write wiper setting to EEPROM for EEPROM capable models.
32*4882a593Smuzhiyun  */
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #include <linux/cache.h>
35*4882a593Smuzhiyun #include <linux/err.h>
36*4882a593Smuzhiyun #include <linux/export.h>
37*4882a593Smuzhiyun #include <linux/iio/iio.h>
38*4882a593Smuzhiyun #include <linux/iio/types.h>
39*4882a593Smuzhiyun #include <linux/module.h>
40*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
41*4882a593Smuzhiyun #include <linux/mutex.h>
42*4882a593Smuzhiyun #include <linux/property.h>
43*4882a593Smuzhiyun #include <linux/spi/spi.h>
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define MCP4131_WRITE		(0x00 << 2)
46*4882a593Smuzhiyun #define MCP4131_READ		(0x03 << 2)
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #define MCP4131_WIPER_SHIFT	4
49*4882a593Smuzhiyun #define MCP4131_CMDERR(r)	((r[0]) & 0x02)
50*4882a593Smuzhiyun #define MCP4131_RAW(r)		((r[0]) == 0xff ? 0x100 : (r[1]))
51*4882a593Smuzhiyun 
52*4882a593Smuzhiyun struct mcp4131_cfg {
53*4882a593Smuzhiyun 	int wipers;
54*4882a593Smuzhiyun 	int max_pos;
55*4882a593Smuzhiyun 	int kohms;
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun enum mcp4131_type {
59*4882a593Smuzhiyun 	MCP413x_502 = 0,
60*4882a593Smuzhiyun 	MCP413x_103,
61*4882a593Smuzhiyun 	MCP413x_503,
62*4882a593Smuzhiyun 	MCP413x_104,
63*4882a593Smuzhiyun 	MCP414x_502,
64*4882a593Smuzhiyun 	MCP414x_103,
65*4882a593Smuzhiyun 	MCP414x_503,
66*4882a593Smuzhiyun 	MCP414x_104,
67*4882a593Smuzhiyun 	MCP415x_502,
68*4882a593Smuzhiyun 	MCP415x_103,
69*4882a593Smuzhiyun 	MCP415x_503,
70*4882a593Smuzhiyun 	MCP415x_104,
71*4882a593Smuzhiyun 	MCP416x_502,
72*4882a593Smuzhiyun 	MCP416x_103,
73*4882a593Smuzhiyun 	MCP416x_503,
74*4882a593Smuzhiyun 	MCP416x_104,
75*4882a593Smuzhiyun 	MCP423x_502,
76*4882a593Smuzhiyun 	MCP423x_103,
77*4882a593Smuzhiyun 	MCP423x_503,
78*4882a593Smuzhiyun 	MCP423x_104,
79*4882a593Smuzhiyun 	MCP424x_502,
80*4882a593Smuzhiyun 	MCP424x_103,
81*4882a593Smuzhiyun 	MCP424x_503,
82*4882a593Smuzhiyun 	MCP424x_104,
83*4882a593Smuzhiyun 	MCP425x_502,
84*4882a593Smuzhiyun 	MCP425x_103,
85*4882a593Smuzhiyun 	MCP425x_503,
86*4882a593Smuzhiyun 	MCP425x_104,
87*4882a593Smuzhiyun 	MCP426x_502,
88*4882a593Smuzhiyun 	MCP426x_103,
89*4882a593Smuzhiyun 	MCP426x_503,
90*4882a593Smuzhiyun 	MCP426x_104,
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun static const struct mcp4131_cfg mcp4131_cfg[] = {
94*4882a593Smuzhiyun 	[MCP413x_502] = { .wipers = 1, .max_pos = 128, .kohms =   5, },
95*4882a593Smuzhiyun 	[MCP413x_103] = { .wipers = 1, .max_pos = 128, .kohms =  10, },
96*4882a593Smuzhiyun 	[MCP413x_503] = { .wipers = 1, .max_pos = 128, .kohms =  50, },
97*4882a593Smuzhiyun 	[MCP413x_104] = { .wipers = 1, .max_pos = 128, .kohms = 100, },
98*4882a593Smuzhiyun 	[MCP414x_502] = { .wipers = 1, .max_pos = 128, .kohms =   5, },
99*4882a593Smuzhiyun 	[MCP414x_103] = { .wipers = 1, .max_pos = 128, .kohms =  10, },
100*4882a593Smuzhiyun 	[MCP414x_503] = { .wipers = 1, .max_pos = 128, .kohms =  50, },
101*4882a593Smuzhiyun 	[MCP414x_104] = { .wipers = 1, .max_pos = 128, .kohms = 100, },
102*4882a593Smuzhiyun 	[MCP415x_502] = { .wipers = 1, .max_pos = 256, .kohms =   5, },
103*4882a593Smuzhiyun 	[MCP415x_103] = { .wipers = 1, .max_pos = 256, .kohms =  10, },
104*4882a593Smuzhiyun 	[MCP415x_503] = { .wipers = 1, .max_pos = 256, .kohms =  50, },
105*4882a593Smuzhiyun 	[MCP415x_104] = { .wipers = 1, .max_pos = 256, .kohms = 100, },
106*4882a593Smuzhiyun 	[MCP416x_502] = { .wipers = 1, .max_pos = 256, .kohms =   5, },
107*4882a593Smuzhiyun 	[MCP416x_103] = { .wipers = 1, .max_pos = 256, .kohms =  10, },
108*4882a593Smuzhiyun 	[MCP416x_503] = { .wipers = 1, .max_pos = 256, .kohms =  50, },
109*4882a593Smuzhiyun 	[MCP416x_104] = { .wipers = 1, .max_pos = 256, .kohms = 100, },
110*4882a593Smuzhiyun 	[MCP423x_502] = { .wipers = 2, .max_pos = 128, .kohms =   5, },
111*4882a593Smuzhiyun 	[MCP423x_103] = { .wipers = 2, .max_pos = 128, .kohms =  10, },
112*4882a593Smuzhiyun 	[MCP423x_503] = { .wipers = 2, .max_pos = 128, .kohms =  50, },
113*4882a593Smuzhiyun 	[MCP423x_104] = { .wipers = 2, .max_pos = 128, .kohms = 100, },
114*4882a593Smuzhiyun 	[MCP424x_502] = { .wipers = 2, .max_pos = 128, .kohms =   5, },
115*4882a593Smuzhiyun 	[MCP424x_103] = { .wipers = 2, .max_pos = 128, .kohms =  10, },
116*4882a593Smuzhiyun 	[MCP424x_503] = { .wipers = 2, .max_pos = 128, .kohms =  50, },
117*4882a593Smuzhiyun 	[MCP424x_104] = { .wipers = 2, .max_pos = 128, .kohms = 100, },
118*4882a593Smuzhiyun 	[MCP425x_502] = { .wipers = 2, .max_pos = 256, .kohms =   5, },
119*4882a593Smuzhiyun 	[MCP425x_103] = { .wipers = 2, .max_pos = 256, .kohms =  10, },
120*4882a593Smuzhiyun 	[MCP425x_503] = { .wipers = 2, .max_pos = 256, .kohms =  50, },
121*4882a593Smuzhiyun 	[MCP425x_104] = { .wipers = 2, .max_pos = 256, .kohms = 100, },
122*4882a593Smuzhiyun 	[MCP426x_502] = { .wipers = 2, .max_pos = 256, .kohms =   5, },
123*4882a593Smuzhiyun 	[MCP426x_103] = { .wipers = 2, .max_pos = 256, .kohms =  10, },
124*4882a593Smuzhiyun 	[MCP426x_503] = { .wipers = 2, .max_pos = 256, .kohms =  50, },
125*4882a593Smuzhiyun 	[MCP426x_104] = { .wipers = 2, .max_pos = 256, .kohms = 100, },
126*4882a593Smuzhiyun };
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun struct mcp4131_data {
129*4882a593Smuzhiyun 	struct spi_device *spi;
130*4882a593Smuzhiyun 	const struct mcp4131_cfg *cfg;
131*4882a593Smuzhiyun 	struct mutex lock;
132*4882a593Smuzhiyun 	u8 buf[2] ____cacheline_aligned;
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun #define MCP4131_CHANNEL(ch) {					\
136*4882a593Smuzhiyun 	.type = IIO_RESISTANCE,					\
137*4882a593Smuzhiyun 	.indexed = 1,						\
138*4882a593Smuzhiyun 	.output = 1,						\
139*4882a593Smuzhiyun 	.channel = (ch),					\
140*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
141*4882a593Smuzhiyun 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun static const struct iio_chan_spec mcp4131_channels[] = {
145*4882a593Smuzhiyun 	MCP4131_CHANNEL(0),
146*4882a593Smuzhiyun 	MCP4131_CHANNEL(1),
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun 
mcp4131_read(struct spi_device * spi,void * buf,size_t len)149*4882a593Smuzhiyun static int mcp4131_read(struct spi_device *spi, void *buf, size_t len)
150*4882a593Smuzhiyun {
151*4882a593Smuzhiyun 	struct spi_transfer t = {
152*4882a593Smuzhiyun 		.tx_buf = buf, /* We need to send addr, cmd and 12 bits */
153*4882a593Smuzhiyun 		.rx_buf	= buf,
154*4882a593Smuzhiyun 		.len = len,
155*4882a593Smuzhiyun 	};
156*4882a593Smuzhiyun 	struct spi_message m;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	spi_message_init(&m);
159*4882a593Smuzhiyun 	spi_message_add_tail(&t, &m);
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	return spi_sync(spi, &m);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun 
mcp4131_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)164*4882a593Smuzhiyun static int mcp4131_read_raw(struct iio_dev *indio_dev,
165*4882a593Smuzhiyun 			    struct iio_chan_spec const *chan,
166*4882a593Smuzhiyun 			    int *val, int *val2, long mask)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun 	int err;
169*4882a593Smuzhiyun 	struct mcp4131_data *data = iio_priv(indio_dev);
170*4882a593Smuzhiyun 	int address = chan->channel;
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	switch (mask) {
173*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
174*4882a593Smuzhiyun 		mutex_lock(&data->lock);
175*4882a593Smuzhiyun 
176*4882a593Smuzhiyun 		data->buf[0] = (address << MCP4131_WIPER_SHIFT) | MCP4131_READ;
177*4882a593Smuzhiyun 		data->buf[1] = 0;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 		err = mcp4131_read(data->spi, data->buf, 2);
180*4882a593Smuzhiyun 		if (err) {
181*4882a593Smuzhiyun 			mutex_unlock(&data->lock);
182*4882a593Smuzhiyun 			return err;
183*4882a593Smuzhiyun 		}
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun 		/* Error, bad address/command combination */
186*4882a593Smuzhiyun 		if (!MCP4131_CMDERR(data->buf)) {
187*4882a593Smuzhiyun 			mutex_unlock(&data->lock);
188*4882a593Smuzhiyun 			return -EIO;
189*4882a593Smuzhiyun 		}
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 		*val = MCP4131_RAW(data->buf);
192*4882a593Smuzhiyun 		mutex_unlock(&data->lock);
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 		return IIO_VAL_INT;
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
197*4882a593Smuzhiyun 		*val = 1000 * data->cfg->kohms;
198*4882a593Smuzhiyun 		*val2 = data->cfg->max_pos;
199*4882a593Smuzhiyun 		return IIO_VAL_FRACTIONAL;
200*4882a593Smuzhiyun 	}
201*4882a593Smuzhiyun 
202*4882a593Smuzhiyun 	return -EINVAL;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun 
mcp4131_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)205*4882a593Smuzhiyun static int mcp4131_write_raw(struct iio_dev *indio_dev,
206*4882a593Smuzhiyun 			     struct iio_chan_spec const *chan,
207*4882a593Smuzhiyun 			     int val, int val2, long mask)
208*4882a593Smuzhiyun {
209*4882a593Smuzhiyun 	int err;
210*4882a593Smuzhiyun 	struct mcp4131_data *data = iio_priv(indio_dev);
211*4882a593Smuzhiyun 	int address = chan->channel << MCP4131_WIPER_SHIFT;
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 	switch (mask) {
214*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
215*4882a593Smuzhiyun 		if (val > data->cfg->max_pos || val < 0)
216*4882a593Smuzhiyun 			return -EINVAL;
217*4882a593Smuzhiyun 		break;
218*4882a593Smuzhiyun 
219*4882a593Smuzhiyun 	default:
220*4882a593Smuzhiyun 		return -EINVAL;
221*4882a593Smuzhiyun 	}
222*4882a593Smuzhiyun 
223*4882a593Smuzhiyun 	mutex_lock(&data->lock);
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	data->buf[0] = address << MCP4131_WIPER_SHIFT;
226*4882a593Smuzhiyun 	data->buf[0] |= MCP4131_WRITE | (val >> 8);
227*4882a593Smuzhiyun 	data->buf[1] = val & 0xFF; /* 8 bits here */
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	err = spi_write(data->spi, data->buf, 2);
230*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	return err;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun static const struct iio_info mcp4131_info = {
236*4882a593Smuzhiyun 	.read_raw = mcp4131_read_raw,
237*4882a593Smuzhiyun 	.write_raw = mcp4131_write_raw,
238*4882a593Smuzhiyun };
239*4882a593Smuzhiyun 
mcp4131_probe(struct spi_device * spi)240*4882a593Smuzhiyun static int mcp4131_probe(struct spi_device *spi)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun 	int err;
243*4882a593Smuzhiyun 	struct device *dev = &spi->dev;
244*4882a593Smuzhiyun 	unsigned long devid;
245*4882a593Smuzhiyun 	struct mcp4131_data *data;
246*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
247*4882a593Smuzhiyun 
248*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
249*4882a593Smuzhiyun 	if (!indio_dev)
250*4882a593Smuzhiyun 		return -ENOMEM;
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	data = iio_priv(indio_dev);
253*4882a593Smuzhiyun 	spi_set_drvdata(spi, indio_dev);
254*4882a593Smuzhiyun 	data->spi = spi;
255*4882a593Smuzhiyun 	data->cfg = device_get_match_data(&spi->dev);
256*4882a593Smuzhiyun 	if (!data->cfg) {
257*4882a593Smuzhiyun 		devid = spi_get_device_id(spi)->driver_data;
258*4882a593Smuzhiyun 		data->cfg = &mcp4131_cfg[devid];
259*4882a593Smuzhiyun 	}
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	mutex_init(&data->lock);
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun 	indio_dev->info = &mcp4131_info;
264*4882a593Smuzhiyun 	indio_dev->channels = mcp4131_channels;
265*4882a593Smuzhiyun 	indio_dev->num_channels = data->cfg->wipers;
266*4882a593Smuzhiyun 	indio_dev->name = spi_get_device_id(spi)->name;
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	err = devm_iio_device_register(dev, indio_dev);
269*4882a593Smuzhiyun 	if (err) {
270*4882a593Smuzhiyun 		dev_info(&spi->dev, "Unable to register %s\n", indio_dev->name);
271*4882a593Smuzhiyun 		return err;
272*4882a593Smuzhiyun 	}
273*4882a593Smuzhiyun 
274*4882a593Smuzhiyun 	return 0;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun static const struct of_device_id mcp4131_dt_ids[] = {
278*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4131-502",
279*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP413x_502] },
280*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4131-103",
281*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP413x_103] },
282*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4131-503",
283*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP413x_503] },
284*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4131-104",
285*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP413x_104] },
286*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4132-502",
287*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP413x_502] },
288*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4132-103",
289*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP413x_103] },
290*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4132-503",
291*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP413x_503] },
292*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4132-104",
293*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP413x_104] },
294*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4141-502",
295*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP414x_502] },
296*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4141-103",
297*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP414x_103] },
298*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4141-503",
299*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP414x_503] },
300*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4141-104",
301*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP414x_104] },
302*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4142-502",
303*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP414x_502] },
304*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4142-103",
305*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP414x_103] },
306*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4142-503",
307*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP414x_503] },
308*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4142-104",
309*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP414x_104] },
310*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4151-502",
311*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP415x_502] },
312*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4151-103",
313*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP415x_103] },
314*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4151-503",
315*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP415x_503] },
316*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4151-104",
317*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP415x_104] },
318*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4152-502",
319*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP415x_502] },
320*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4152-103",
321*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP415x_103] },
322*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4152-503",
323*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP415x_503] },
324*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4152-104",
325*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP415x_104] },
326*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4161-502",
327*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP416x_502] },
328*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4161-103",
329*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP416x_103] },
330*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4161-503",
331*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP416x_503] },
332*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4161-104",
333*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP416x_104] },
334*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4162-502",
335*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP416x_502] },
336*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4162-103",
337*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP416x_103] },
338*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4162-503",
339*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP416x_503] },
340*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4162-104",
341*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP416x_104] },
342*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4231-502",
343*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP423x_502] },
344*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4231-103",
345*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP423x_103] },
346*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4231-503",
347*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP423x_503] },
348*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4231-104",
349*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP423x_104] },
350*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4232-502",
351*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP423x_502] },
352*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4232-103",
353*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP423x_103] },
354*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4232-503",
355*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP423x_503] },
356*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4232-104",
357*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP423x_104] },
358*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4241-502",
359*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP424x_502] },
360*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4241-103",
361*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP424x_103] },
362*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4241-503",
363*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP424x_503] },
364*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4241-104",
365*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP424x_104] },
366*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4242-502",
367*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP424x_502] },
368*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4242-103",
369*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP424x_103] },
370*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4242-503",
371*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP424x_503] },
372*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4242-104",
373*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP424x_104] },
374*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4251-502",
375*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP425x_502] },
376*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4251-103",
377*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP425x_103] },
378*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4251-503",
379*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP425x_503] },
380*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4251-104",
381*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP425x_104] },
382*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4252-502",
383*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP425x_502] },
384*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4252-103",
385*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP425x_103] },
386*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4252-503",
387*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP425x_503] },
388*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4252-104",
389*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP425x_104] },
390*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4261-502",
391*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP426x_502] },
392*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4261-103",
393*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP426x_103] },
394*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4261-503",
395*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP426x_503] },
396*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4261-104",
397*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP426x_104] },
398*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4262-502",
399*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP426x_502] },
400*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4262-103",
401*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP426x_103] },
402*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4262-503",
403*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP426x_503] },
404*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp4262-104",
405*4882a593Smuzhiyun 		.data = &mcp4131_cfg[MCP426x_104] },
406*4882a593Smuzhiyun 	{}
407*4882a593Smuzhiyun };
408*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mcp4131_dt_ids);
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun static const struct spi_device_id mcp4131_id[] = {
411*4882a593Smuzhiyun 	{ "mcp4131-502", MCP413x_502 },
412*4882a593Smuzhiyun 	{ "mcp4131-103", MCP413x_103 },
413*4882a593Smuzhiyun 	{ "mcp4131-503", MCP413x_503 },
414*4882a593Smuzhiyun 	{ "mcp4131-104", MCP413x_104 },
415*4882a593Smuzhiyun 	{ "mcp4132-502", MCP413x_502 },
416*4882a593Smuzhiyun 	{ "mcp4132-103", MCP413x_103 },
417*4882a593Smuzhiyun 	{ "mcp4132-503", MCP413x_503 },
418*4882a593Smuzhiyun 	{ "mcp4132-104", MCP413x_104 },
419*4882a593Smuzhiyun 	{ "mcp4141-502", MCP414x_502 },
420*4882a593Smuzhiyun 	{ "mcp4141-103", MCP414x_103 },
421*4882a593Smuzhiyun 	{ "mcp4141-503", MCP414x_503 },
422*4882a593Smuzhiyun 	{ "mcp4141-104", MCP414x_104 },
423*4882a593Smuzhiyun 	{ "mcp4142-502", MCP414x_502 },
424*4882a593Smuzhiyun 	{ "mcp4142-103", MCP414x_103 },
425*4882a593Smuzhiyun 	{ "mcp4142-503", MCP414x_503 },
426*4882a593Smuzhiyun 	{ "mcp4142-104", MCP414x_104 },
427*4882a593Smuzhiyun 	{ "mcp4151-502", MCP415x_502 },
428*4882a593Smuzhiyun 	{ "mcp4151-103", MCP415x_103 },
429*4882a593Smuzhiyun 	{ "mcp4151-503", MCP415x_503 },
430*4882a593Smuzhiyun 	{ "mcp4151-104", MCP415x_104 },
431*4882a593Smuzhiyun 	{ "mcp4152-502", MCP415x_502 },
432*4882a593Smuzhiyun 	{ "mcp4152-103", MCP415x_103 },
433*4882a593Smuzhiyun 	{ "mcp4152-503", MCP415x_503 },
434*4882a593Smuzhiyun 	{ "mcp4152-104", MCP415x_104 },
435*4882a593Smuzhiyun 	{ "mcp4161-502", MCP416x_502 },
436*4882a593Smuzhiyun 	{ "mcp4161-103", MCP416x_103 },
437*4882a593Smuzhiyun 	{ "mcp4161-503", MCP416x_503 },
438*4882a593Smuzhiyun 	{ "mcp4161-104", MCP416x_104 },
439*4882a593Smuzhiyun 	{ "mcp4162-502", MCP416x_502 },
440*4882a593Smuzhiyun 	{ "mcp4162-103", MCP416x_103 },
441*4882a593Smuzhiyun 	{ "mcp4162-503", MCP416x_503 },
442*4882a593Smuzhiyun 	{ "mcp4162-104", MCP416x_104 },
443*4882a593Smuzhiyun 	{ "mcp4231-502", MCP423x_502 },
444*4882a593Smuzhiyun 	{ "mcp4231-103", MCP423x_103 },
445*4882a593Smuzhiyun 	{ "mcp4231-503", MCP423x_503 },
446*4882a593Smuzhiyun 	{ "mcp4231-104", MCP423x_104 },
447*4882a593Smuzhiyun 	{ "mcp4232-502", MCP423x_502 },
448*4882a593Smuzhiyun 	{ "mcp4232-103", MCP423x_103 },
449*4882a593Smuzhiyun 	{ "mcp4232-503", MCP423x_503 },
450*4882a593Smuzhiyun 	{ "mcp4232-104", MCP423x_104 },
451*4882a593Smuzhiyun 	{ "mcp4241-502", MCP424x_502 },
452*4882a593Smuzhiyun 	{ "mcp4241-103", MCP424x_103 },
453*4882a593Smuzhiyun 	{ "mcp4241-503", MCP424x_503 },
454*4882a593Smuzhiyun 	{ "mcp4241-104", MCP424x_104 },
455*4882a593Smuzhiyun 	{ "mcp4242-502", MCP424x_502 },
456*4882a593Smuzhiyun 	{ "mcp4242-103", MCP424x_103 },
457*4882a593Smuzhiyun 	{ "mcp4242-503", MCP424x_503 },
458*4882a593Smuzhiyun 	{ "mcp4242-104", MCP424x_104 },
459*4882a593Smuzhiyun 	{ "mcp4251-502", MCP425x_502 },
460*4882a593Smuzhiyun 	{ "mcp4251-103", MCP425x_103 },
461*4882a593Smuzhiyun 	{ "mcp4251-503", MCP425x_503 },
462*4882a593Smuzhiyun 	{ "mcp4251-104", MCP425x_104 },
463*4882a593Smuzhiyun 	{ "mcp4252-502", MCP425x_502 },
464*4882a593Smuzhiyun 	{ "mcp4252-103", MCP425x_103 },
465*4882a593Smuzhiyun 	{ "mcp4252-503", MCP425x_503 },
466*4882a593Smuzhiyun 	{ "mcp4252-104", MCP425x_104 },
467*4882a593Smuzhiyun 	{ "mcp4261-502", MCP426x_502 },
468*4882a593Smuzhiyun 	{ "mcp4261-103", MCP426x_103 },
469*4882a593Smuzhiyun 	{ "mcp4261-503", MCP426x_503 },
470*4882a593Smuzhiyun 	{ "mcp4261-104", MCP426x_104 },
471*4882a593Smuzhiyun 	{ "mcp4262-502", MCP426x_502 },
472*4882a593Smuzhiyun 	{ "mcp4262-103", MCP426x_103 },
473*4882a593Smuzhiyun 	{ "mcp4262-503", MCP426x_503 },
474*4882a593Smuzhiyun 	{ "mcp4262-104", MCP426x_104 },
475*4882a593Smuzhiyun 	{}
476*4882a593Smuzhiyun };
477*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, mcp4131_id);
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun static struct spi_driver mcp4131_driver = {
480*4882a593Smuzhiyun 	.driver = {
481*4882a593Smuzhiyun 		.name	= "mcp4131",
482*4882a593Smuzhiyun 		.of_match_table = mcp4131_dt_ids,
483*4882a593Smuzhiyun 	},
484*4882a593Smuzhiyun 	.probe		= mcp4131_probe,
485*4882a593Smuzhiyun 	.id_table	= mcp4131_id,
486*4882a593Smuzhiyun };
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun module_spi_driver(mcp4131_driver);
489*4882a593Smuzhiyun 
490*4882a593Smuzhiyun MODULE_AUTHOR("Slawomir Stepien <sst@poczta.fm>");
491*4882a593Smuzhiyun MODULE_DESCRIPTION("MCP4131 digital potentiometer");
492*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
493