xref: /OK3568_Linux_fs/kernel/drivers/iio/potentiometer/mcp41010.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Industrial I/O driver for Microchip digital potentiometers
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2018 Chris Coffey <cmc@babblebit.net>
6*4882a593Smuzhiyun  * Based on: Slawomir Stepien's code from mcp4131.c
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * Datasheet: https://ww1.microchip.com/downloads/en/devicedoc/11195c.pdf
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * DEVID	#Wipers	#Positions	Resistance (kOhm)
11*4882a593Smuzhiyun  * mcp41010	1	256		10
12*4882a593Smuzhiyun  * mcp41050	1	256		50
13*4882a593Smuzhiyun  * mcp41100	1	256		100
14*4882a593Smuzhiyun  * mcp42010	2	256		10
15*4882a593Smuzhiyun  * mcp42050	2	256		50
16*4882a593Smuzhiyun  * mcp42100	2	256		100
17*4882a593Smuzhiyun  */
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <linux/cache.h>
20*4882a593Smuzhiyun #include <linux/err.h>
21*4882a593Smuzhiyun #include <linux/iio/iio.h>
22*4882a593Smuzhiyun #include <linux/iio/types.h>
23*4882a593Smuzhiyun #include <linux/module.h>
24*4882a593Smuzhiyun #include <linux/mutex.h>
25*4882a593Smuzhiyun #include <linux/of.h>
26*4882a593Smuzhiyun #include <linux/of_device.h>
27*4882a593Smuzhiyun #include <linux/spi/spi.h>
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun #define MCP41010_MAX_WIPERS	2
30*4882a593Smuzhiyun #define MCP41010_WRITE		BIT(4)
31*4882a593Smuzhiyun #define MCP41010_WIPER_MAX	255
32*4882a593Smuzhiyun #define MCP41010_WIPER_CHANNEL	BIT(0)
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun struct mcp41010_cfg {
35*4882a593Smuzhiyun 	char name[16];
36*4882a593Smuzhiyun 	int wipers;
37*4882a593Smuzhiyun 	int kohms;
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun enum mcp41010_type {
41*4882a593Smuzhiyun 	MCP41010,
42*4882a593Smuzhiyun 	MCP41050,
43*4882a593Smuzhiyun 	MCP41100,
44*4882a593Smuzhiyun 	MCP42010,
45*4882a593Smuzhiyun 	MCP42050,
46*4882a593Smuzhiyun 	MCP42100,
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun 
49*4882a593Smuzhiyun static const struct mcp41010_cfg mcp41010_cfg[] = {
50*4882a593Smuzhiyun 	[MCP41010] = { .name = "mcp41010", .wipers = 1, .kohms =  10, },
51*4882a593Smuzhiyun 	[MCP41050] = { .name = "mcp41050", .wipers = 1, .kohms =  50, },
52*4882a593Smuzhiyun 	[MCP41100] = { .name = "mcp41100", .wipers = 1, .kohms = 100, },
53*4882a593Smuzhiyun 	[MCP42010] = { .name = "mcp42010", .wipers = 2, .kohms =  10, },
54*4882a593Smuzhiyun 	[MCP42050] = { .name = "mcp42050", .wipers = 2, .kohms =  50, },
55*4882a593Smuzhiyun 	[MCP42100] = { .name = "mcp42100", .wipers = 2, .kohms = 100, },
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun struct mcp41010_data {
59*4882a593Smuzhiyun 	struct spi_device *spi;
60*4882a593Smuzhiyun 	const struct mcp41010_cfg *cfg;
61*4882a593Smuzhiyun 	struct mutex lock; /* Protect write sequences */
62*4882a593Smuzhiyun 	unsigned int value[MCP41010_MAX_WIPERS]; /* Cache wiper values */
63*4882a593Smuzhiyun 	u8 buf[2] ____cacheline_aligned;
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun #define MCP41010_CHANNEL(ch) {					\
67*4882a593Smuzhiyun 	.type = IIO_RESISTANCE,					\
68*4882a593Smuzhiyun 	.indexed = 1,						\
69*4882a593Smuzhiyun 	.output = 1,						\
70*4882a593Smuzhiyun 	.channel = (ch),					\
71*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
72*4882a593Smuzhiyun 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun static const struct iio_chan_spec mcp41010_channels[] = {
76*4882a593Smuzhiyun 	MCP41010_CHANNEL(0),
77*4882a593Smuzhiyun 	MCP41010_CHANNEL(1),
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun 
mcp41010_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)80*4882a593Smuzhiyun static int mcp41010_read_raw(struct iio_dev *indio_dev,
81*4882a593Smuzhiyun 			    struct iio_chan_spec const *chan,
82*4882a593Smuzhiyun 			    int *val, int *val2, long mask)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 	struct mcp41010_data *data = iio_priv(indio_dev);
85*4882a593Smuzhiyun 	int channel = chan->channel;
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun 	switch (mask) {
88*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
89*4882a593Smuzhiyun 		*val = data->value[channel];
90*4882a593Smuzhiyun 		return IIO_VAL_INT;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
93*4882a593Smuzhiyun 		*val = 1000 * data->cfg->kohms;
94*4882a593Smuzhiyun 		*val2 = MCP41010_WIPER_MAX;
95*4882a593Smuzhiyun 		return IIO_VAL_FRACTIONAL;
96*4882a593Smuzhiyun 	}
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	return -EINVAL;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
mcp41010_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)101*4882a593Smuzhiyun static int mcp41010_write_raw(struct iio_dev *indio_dev,
102*4882a593Smuzhiyun 			     struct iio_chan_spec const *chan,
103*4882a593Smuzhiyun 			     int val, int val2, long mask)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun 	int err;
106*4882a593Smuzhiyun 	struct mcp41010_data *data = iio_priv(indio_dev);
107*4882a593Smuzhiyun 	int channel = chan->channel;
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun 	if (mask != IIO_CHAN_INFO_RAW)
110*4882a593Smuzhiyun 		return -EINVAL;
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun 	if (val > MCP41010_WIPER_MAX || val < 0)
113*4882a593Smuzhiyun 		return -EINVAL;
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	mutex_lock(&data->lock);
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	data->buf[0] = MCP41010_WIPER_CHANNEL << channel;
118*4882a593Smuzhiyun 	data->buf[0] |= MCP41010_WRITE;
119*4882a593Smuzhiyun 	data->buf[1] = val & 0xff;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	err = spi_write(data->spi, data->buf, sizeof(data->buf));
122*4882a593Smuzhiyun 	if (!err)
123*4882a593Smuzhiyun 		data->value[channel] = val;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun 	return err;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun static const struct iio_info mcp41010_info = {
131*4882a593Smuzhiyun 	.read_raw = mcp41010_read_raw,
132*4882a593Smuzhiyun 	.write_raw = mcp41010_write_raw,
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
mcp41010_probe(struct spi_device * spi)135*4882a593Smuzhiyun static int mcp41010_probe(struct spi_device *spi)
136*4882a593Smuzhiyun {
137*4882a593Smuzhiyun 	int err;
138*4882a593Smuzhiyun 	struct device *dev = &spi->dev;
139*4882a593Smuzhiyun 	struct mcp41010_data *data;
140*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
143*4882a593Smuzhiyun 	if (!indio_dev)
144*4882a593Smuzhiyun 		return -ENOMEM;
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	data = iio_priv(indio_dev);
147*4882a593Smuzhiyun 	spi_set_drvdata(spi, indio_dev);
148*4882a593Smuzhiyun 	data->spi = spi;
149*4882a593Smuzhiyun 	data->cfg = of_device_get_match_data(&spi->dev);
150*4882a593Smuzhiyun 	if (!data->cfg)
151*4882a593Smuzhiyun 		data->cfg = &mcp41010_cfg[spi_get_device_id(spi)->driver_data];
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun 	mutex_init(&data->lock);
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	indio_dev->info = &mcp41010_info;
156*4882a593Smuzhiyun 	indio_dev->channels = mcp41010_channels;
157*4882a593Smuzhiyun 	indio_dev->num_channels = data->cfg->wipers;
158*4882a593Smuzhiyun 	indio_dev->name = data->cfg->name;
159*4882a593Smuzhiyun 
160*4882a593Smuzhiyun 	err = devm_iio_device_register(dev, indio_dev);
161*4882a593Smuzhiyun 	if (err)
162*4882a593Smuzhiyun 		dev_info(&spi->dev, "Unable to register %s\n", indio_dev->name);
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	return err;
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun static const struct of_device_id mcp41010_match[] = {
168*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp41010", .data = &mcp41010_cfg[MCP41010] },
169*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp41050", .data = &mcp41010_cfg[MCP41050] },
170*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp41100", .data = &mcp41010_cfg[MCP41100] },
171*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp42010", .data = &mcp41010_cfg[MCP42010] },
172*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp42050", .data = &mcp41010_cfg[MCP42050] },
173*4882a593Smuzhiyun 	{ .compatible = "microchip,mcp42100", .data = &mcp41010_cfg[MCP42100] },
174*4882a593Smuzhiyun 	{}
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mcp41010_match);
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun static const struct spi_device_id mcp41010_id[] = {
179*4882a593Smuzhiyun 	{ "mcp41010", MCP41010 },
180*4882a593Smuzhiyun 	{ "mcp41050", MCP41050 },
181*4882a593Smuzhiyun 	{ "mcp41100", MCP41100 },
182*4882a593Smuzhiyun 	{ "mcp42010", MCP42010 },
183*4882a593Smuzhiyun 	{ "mcp42050", MCP42050 },
184*4882a593Smuzhiyun 	{ "mcp42100", MCP42100 },
185*4882a593Smuzhiyun 	{}
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, mcp41010_id);
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun static struct spi_driver mcp41010_driver = {
190*4882a593Smuzhiyun 	.driver = {
191*4882a593Smuzhiyun 		.name	= "mcp41010",
192*4882a593Smuzhiyun 		.of_match_table = mcp41010_match,
193*4882a593Smuzhiyun 	},
194*4882a593Smuzhiyun 	.probe		= mcp41010_probe,
195*4882a593Smuzhiyun 	.id_table	= mcp41010_id,
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun module_spi_driver(mcp41010_driver);
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun MODULE_AUTHOR("Chris Coffey <cmc@babblebit.net>");
201*4882a593Smuzhiyun MODULE_DESCRIPTION("MCP41010 digital potentiometer");
202*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
203