1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Maxim Integrated MAX5481-MAX5484 digital potentiometer driver
4*4882a593Smuzhiyun * Copyright 2016 Rockwell Collins
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Datasheet:
7*4882a593Smuzhiyun * https://datasheets.maximintegrated.com/en/ds/MAX5481-MAX5484.pdf
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/iio/iio.h>
11*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
14*4882a593Smuzhiyun #include <linux/property.h>
15*4882a593Smuzhiyun #include <linux/spi/spi.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* write wiper reg */
18*4882a593Smuzhiyun #define MAX5481_WRITE_WIPER (0 << 4)
19*4882a593Smuzhiyun /* copy wiper reg to NV reg */
20*4882a593Smuzhiyun #define MAX5481_COPY_AB_TO_NV (2 << 4)
21*4882a593Smuzhiyun /* copy NV reg to wiper reg */
22*4882a593Smuzhiyun #define MAX5481_COPY_NV_TO_AB (3 << 4)
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define MAX5481_MAX_POS 1023
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun enum max5481_variant {
27*4882a593Smuzhiyun max5481,
28*4882a593Smuzhiyun max5482,
29*4882a593Smuzhiyun max5483,
30*4882a593Smuzhiyun max5484,
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun struct max5481_cfg {
34*4882a593Smuzhiyun int kohms;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun static const struct max5481_cfg max5481_cfg[] = {
38*4882a593Smuzhiyun [max5481] = { .kohms = 10, },
39*4882a593Smuzhiyun [max5482] = { .kohms = 50, },
40*4882a593Smuzhiyun [max5483] = { .kohms = 10, },
41*4882a593Smuzhiyun [max5484] = { .kohms = 50, },
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun struct max5481_data {
45*4882a593Smuzhiyun struct spi_device *spi;
46*4882a593Smuzhiyun const struct max5481_cfg *cfg;
47*4882a593Smuzhiyun u8 msg[3] ____cacheline_aligned;
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define MAX5481_CHANNEL { \
51*4882a593Smuzhiyun .type = IIO_RESISTANCE, \
52*4882a593Smuzhiyun .indexed = 1, \
53*4882a593Smuzhiyun .output = 1, \
54*4882a593Smuzhiyun .channel = 0, \
55*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
56*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const struct iio_chan_spec max5481_channels[] = {
60*4882a593Smuzhiyun MAX5481_CHANNEL,
61*4882a593Smuzhiyun };
62*4882a593Smuzhiyun
max5481_write_cmd(struct max5481_data * data,u8 cmd,u16 val)63*4882a593Smuzhiyun static int max5481_write_cmd(struct max5481_data *data, u8 cmd, u16 val)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun struct spi_device *spi = data->spi;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun data->msg[0] = cmd;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun switch (cmd) {
70*4882a593Smuzhiyun case MAX5481_WRITE_WIPER:
71*4882a593Smuzhiyun data->msg[1] = val >> 2;
72*4882a593Smuzhiyun data->msg[2] = (val & 0x3) << 6;
73*4882a593Smuzhiyun return spi_write(spi, data->msg, 3);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun case MAX5481_COPY_AB_TO_NV:
76*4882a593Smuzhiyun case MAX5481_COPY_NV_TO_AB:
77*4882a593Smuzhiyun return spi_write(spi, data->msg, 1);
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun default:
80*4882a593Smuzhiyun return -EIO;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun
max5481_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)84*4882a593Smuzhiyun static int max5481_read_raw(struct iio_dev *indio_dev,
85*4882a593Smuzhiyun struct iio_chan_spec const *chan,
86*4882a593Smuzhiyun int *val, int *val2, long mask)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun struct max5481_data *data = iio_priv(indio_dev);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun if (mask != IIO_CHAN_INFO_SCALE)
91*4882a593Smuzhiyun return -EINVAL;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun *val = 1000 * data->cfg->kohms;
94*4882a593Smuzhiyun *val2 = MAX5481_MAX_POS;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
max5481_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)99*4882a593Smuzhiyun static int max5481_write_raw(struct iio_dev *indio_dev,
100*4882a593Smuzhiyun struct iio_chan_spec const *chan,
101*4882a593Smuzhiyun int val, int val2, long mask)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun struct max5481_data *data = iio_priv(indio_dev);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun if (mask != IIO_CHAN_INFO_RAW)
106*4882a593Smuzhiyun return -EINVAL;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun if (val < 0 || val > MAX5481_MAX_POS)
109*4882a593Smuzhiyun return -EINVAL;
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun return max5481_write_cmd(data, MAX5481_WRITE_WIPER, val);
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun static const struct iio_info max5481_info = {
115*4882a593Smuzhiyun .read_raw = max5481_read_raw,
116*4882a593Smuzhiyun .write_raw = max5481_write_raw,
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun static const struct of_device_id max5481_match[] = {
120*4882a593Smuzhiyun { .compatible = "maxim,max5481", .data = &max5481_cfg[max5481] },
121*4882a593Smuzhiyun { .compatible = "maxim,max5482", .data = &max5481_cfg[max5482] },
122*4882a593Smuzhiyun { .compatible = "maxim,max5483", .data = &max5481_cfg[max5483] },
123*4882a593Smuzhiyun { .compatible = "maxim,max5484", .data = &max5481_cfg[max5484] },
124*4882a593Smuzhiyun { }
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, max5481_match);
127*4882a593Smuzhiyun
max5481_probe(struct spi_device * spi)128*4882a593Smuzhiyun static int max5481_probe(struct spi_device *spi)
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun struct iio_dev *indio_dev;
131*4882a593Smuzhiyun struct max5481_data *data;
132*4882a593Smuzhiyun const struct spi_device_id *id = spi_get_device_id(spi);
133*4882a593Smuzhiyun int ret;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*data));
136*4882a593Smuzhiyun if (!indio_dev)
137*4882a593Smuzhiyun return -ENOMEM;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun dev_set_drvdata(&spi->dev, indio_dev);
140*4882a593Smuzhiyun data = iio_priv(indio_dev);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun data->spi = spi;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun data->cfg = device_get_match_data(&spi->dev);
145*4882a593Smuzhiyun if (!data->cfg)
146*4882a593Smuzhiyun data->cfg = &max5481_cfg[id->driver_data];
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun indio_dev->name = id->name;
149*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun /* variant specific configuration */
152*4882a593Smuzhiyun indio_dev->info = &max5481_info;
153*4882a593Smuzhiyun indio_dev->channels = max5481_channels;
154*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(max5481_channels);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun /* restore wiper from NV */
157*4882a593Smuzhiyun ret = max5481_write_cmd(data, MAX5481_COPY_NV_TO_AB, 0);
158*4882a593Smuzhiyun if (ret < 0)
159*4882a593Smuzhiyun return ret;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun return iio_device_register(indio_dev);
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
max5481_remove(struct spi_device * spi)164*4882a593Smuzhiyun static int max5481_remove(struct spi_device *spi)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_get_drvdata(&spi->dev);
167*4882a593Smuzhiyun struct max5481_data *data = iio_priv(indio_dev);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun iio_device_unregister(indio_dev);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun /* save wiper reg to NV reg */
172*4882a593Smuzhiyun return max5481_write_cmd(data, MAX5481_COPY_AB_TO_NV, 0);
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun static const struct spi_device_id max5481_id_table[] = {
176*4882a593Smuzhiyun { "max5481", max5481 },
177*4882a593Smuzhiyun { "max5482", max5482 },
178*4882a593Smuzhiyun { "max5483", max5483 },
179*4882a593Smuzhiyun { "max5484", max5484 },
180*4882a593Smuzhiyun { }
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, max5481_id_table);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun static struct spi_driver max5481_driver = {
185*4882a593Smuzhiyun .driver = {
186*4882a593Smuzhiyun .name = "max5481",
187*4882a593Smuzhiyun .of_match_table = max5481_match,
188*4882a593Smuzhiyun },
189*4882a593Smuzhiyun .probe = max5481_probe,
190*4882a593Smuzhiyun .remove = max5481_remove,
191*4882a593Smuzhiyun .id_table = max5481_id_table,
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun module_spi_driver(max5481_driver);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun MODULE_AUTHOR("Maury Anderson <maury.anderson@rockwellcollins.com>");
197*4882a593Smuzhiyun MODULE_DESCRIPTION("max5481 SPI driver");
198*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
199