xref: /OK3568_Linux_fs/kernel/drivers/iio/magnetometer/rm3100-core.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * PNI RM3100 3-axis geomagnetic sensor driver core.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2018 Song Qiang <songqiang1304521@gmail.com>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * User Manual available at
8*4882a593Smuzhiyun  * <https://www.pnicorp.com/download/rm3100-user-manual/>
9*4882a593Smuzhiyun  *
10*4882a593Smuzhiyun  * TODO: event generation, pm.
11*4882a593Smuzhiyun  */
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun #include <linux/iio/buffer.h>
19*4882a593Smuzhiyun #include <linux/iio/iio.h>
20*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
21*4882a593Smuzhiyun #include <linux/iio/trigger.h>
22*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
23*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #include <asm/unaligned.h>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include "rm3100.h"
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /* Cycle Count Registers. */
30*4882a593Smuzhiyun #define RM3100_REG_CC_X			0x05
31*4882a593Smuzhiyun #define RM3100_REG_CC_Y			0x07
32*4882a593Smuzhiyun #define RM3100_REG_CC_Z			0x09
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun /* Poll Measurement Mode register. */
35*4882a593Smuzhiyun #define RM3100_REG_POLL			0x00
36*4882a593Smuzhiyun #define		RM3100_POLL_X		BIT(4)
37*4882a593Smuzhiyun #define		RM3100_POLL_Y		BIT(5)
38*4882a593Smuzhiyun #define		RM3100_POLL_Z		BIT(6)
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun /* Continuous Measurement Mode register. */
41*4882a593Smuzhiyun #define RM3100_REG_CMM			0x01
42*4882a593Smuzhiyun #define		RM3100_CMM_START	BIT(0)
43*4882a593Smuzhiyun #define		RM3100_CMM_X		BIT(4)
44*4882a593Smuzhiyun #define		RM3100_CMM_Y		BIT(5)
45*4882a593Smuzhiyun #define		RM3100_CMM_Z		BIT(6)
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /* TiMe Rate Configuration register. */
48*4882a593Smuzhiyun #define RM3100_REG_TMRC			0x0B
49*4882a593Smuzhiyun #define RM3100_TMRC_OFFSET		0x92
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /* Result Status register. */
52*4882a593Smuzhiyun #define RM3100_REG_STATUS		0x34
53*4882a593Smuzhiyun #define		RM3100_STATUS_DRDY	BIT(7)
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun /* Measurement result registers. */
56*4882a593Smuzhiyun #define RM3100_REG_MX2			0x24
57*4882a593Smuzhiyun #define RM3100_REG_MY2			0x27
58*4882a593Smuzhiyun #define RM3100_REG_MZ2			0x2a
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun #define RM3100_W_REG_START		RM3100_REG_POLL
61*4882a593Smuzhiyun #define RM3100_W_REG_END		RM3100_REG_TMRC
62*4882a593Smuzhiyun #define RM3100_R_REG_START		RM3100_REG_POLL
63*4882a593Smuzhiyun #define RM3100_R_REG_END		RM3100_REG_STATUS
64*4882a593Smuzhiyun #define RM3100_V_REG_START		RM3100_REG_POLL
65*4882a593Smuzhiyun #define RM3100_V_REG_END		RM3100_REG_STATUS
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun /*
68*4882a593Smuzhiyun  * This is computed by hand, is the sum of channel storage bits and padding
69*4882a593Smuzhiyun  * bits, which is 4+4+4+12=24 in here.
70*4882a593Smuzhiyun  */
71*4882a593Smuzhiyun #define RM3100_SCAN_BYTES		24
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun #define RM3100_CMM_AXIS_SHIFT		4
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun struct rm3100_data {
76*4882a593Smuzhiyun 	struct regmap *regmap;
77*4882a593Smuzhiyun 	struct completion measuring_done;
78*4882a593Smuzhiyun 	bool use_interrupt;
79*4882a593Smuzhiyun 	int conversion_time;
80*4882a593Smuzhiyun 	int scale;
81*4882a593Smuzhiyun 	/* Ensure naturally aligned timestamp */
82*4882a593Smuzhiyun 	u8 buffer[RM3100_SCAN_BYTES] __aligned(8);
83*4882a593Smuzhiyun 	struct iio_trigger *drdy_trig;
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun 	/*
86*4882a593Smuzhiyun 	 * This lock is for protecting the consistency of series of i2c
87*4882a593Smuzhiyun 	 * operations, that is, to make sure a measurement process will
88*4882a593Smuzhiyun 	 * not be interrupted by a set frequency operation, which should
89*4882a593Smuzhiyun 	 * be taken where a series of i2c operation starts, released where
90*4882a593Smuzhiyun 	 * the operation ends.
91*4882a593Smuzhiyun 	 */
92*4882a593Smuzhiyun 	struct mutex lock;
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun static const struct regmap_range rm3100_readable_ranges[] = {
96*4882a593Smuzhiyun 	regmap_reg_range(RM3100_R_REG_START, RM3100_R_REG_END),
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun const struct regmap_access_table rm3100_readable_table = {
100*4882a593Smuzhiyun 	.yes_ranges = rm3100_readable_ranges,
101*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(rm3100_readable_ranges),
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rm3100_readable_table);
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun static const struct regmap_range rm3100_writable_ranges[] = {
106*4882a593Smuzhiyun 	regmap_reg_range(RM3100_W_REG_START, RM3100_W_REG_END),
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun const struct regmap_access_table rm3100_writable_table = {
110*4882a593Smuzhiyun 	.yes_ranges = rm3100_writable_ranges,
111*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(rm3100_writable_ranges),
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rm3100_writable_table);
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun static const struct regmap_range rm3100_volatile_ranges[] = {
116*4882a593Smuzhiyun 	regmap_reg_range(RM3100_V_REG_START, RM3100_V_REG_END),
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun const struct regmap_access_table rm3100_volatile_table = {
120*4882a593Smuzhiyun 	.yes_ranges = rm3100_volatile_ranges,
121*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(rm3100_volatile_ranges),
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rm3100_volatile_table);
124*4882a593Smuzhiyun 
rm3100_thread_fn(int irq,void * d)125*4882a593Smuzhiyun static irqreturn_t rm3100_thread_fn(int irq, void *d)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun 	struct iio_dev *indio_dev = d;
128*4882a593Smuzhiyun 	struct rm3100_data *data = iio_priv(indio_dev);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	/*
131*4882a593Smuzhiyun 	 * Write operation to any register or read operation
132*4882a593Smuzhiyun 	 * to first byte of results will clear the interrupt.
133*4882a593Smuzhiyun 	 */
134*4882a593Smuzhiyun 	regmap_write(data->regmap, RM3100_REG_POLL, 0);
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	return IRQ_HANDLED;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun 
rm3100_irq_handler(int irq,void * d)139*4882a593Smuzhiyun static irqreturn_t rm3100_irq_handler(int irq, void *d)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun 	struct iio_dev *indio_dev = d;
142*4882a593Smuzhiyun 	struct rm3100_data *data = iio_priv(indio_dev);
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	switch (indio_dev->currentmode) {
145*4882a593Smuzhiyun 	case INDIO_DIRECT_MODE:
146*4882a593Smuzhiyun 		complete(&data->measuring_done);
147*4882a593Smuzhiyun 		break;
148*4882a593Smuzhiyun 	case INDIO_BUFFER_TRIGGERED:
149*4882a593Smuzhiyun 		iio_trigger_poll(data->drdy_trig);
150*4882a593Smuzhiyun 		break;
151*4882a593Smuzhiyun 	default:
152*4882a593Smuzhiyun 		dev_err(indio_dev->dev.parent,
153*4882a593Smuzhiyun 			"device mode out of control, current mode: %d",
154*4882a593Smuzhiyun 			indio_dev->currentmode);
155*4882a593Smuzhiyun 	}
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	return IRQ_WAKE_THREAD;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun 
rm3100_wait_measurement(struct rm3100_data * data)160*4882a593Smuzhiyun static int rm3100_wait_measurement(struct rm3100_data *data)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun 	struct regmap *regmap = data->regmap;
163*4882a593Smuzhiyun 	unsigned int val;
164*4882a593Smuzhiyun 	int tries = 20;
165*4882a593Smuzhiyun 	int ret;
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun 	/*
168*4882a593Smuzhiyun 	 * A read cycle of 400kbits i2c bus is about 20us, plus the time
169*4882a593Smuzhiyun 	 * used for scheduling, a read cycle of fast mode of this device
170*4882a593Smuzhiyun 	 * can reach 1.7ms, it may be possible for data to arrive just
171*4882a593Smuzhiyun 	 * after we check the RM3100_REG_STATUS. In this case, irq_handler is
172*4882a593Smuzhiyun 	 * called before measuring_done is reinitialized, it will wait
173*4882a593Smuzhiyun 	 * forever for data that has already been ready.
174*4882a593Smuzhiyun 	 * Reinitialize measuring_done before looking up makes sure we
175*4882a593Smuzhiyun 	 * will always capture interrupt no matter when it happens.
176*4882a593Smuzhiyun 	 */
177*4882a593Smuzhiyun 	if (data->use_interrupt)
178*4882a593Smuzhiyun 		reinit_completion(&data->measuring_done);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	ret = regmap_read(regmap, RM3100_REG_STATUS, &val);
181*4882a593Smuzhiyun 	if (ret < 0)
182*4882a593Smuzhiyun 		return ret;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	if ((val & RM3100_STATUS_DRDY) != RM3100_STATUS_DRDY) {
185*4882a593Smuzhiyun 		if (data->use_interrupt) {
186*4882a593Smuzhiyun 			ret = wait_for_completion_timeout(&data->measuring_done,
187*4882a593Smuzhiyun 				msecs_to_jiffies(data->conversion_time));
188*4882a593Smuzhiyun 			if (!ret)
189*4882a593Smuzhiyun 				return -ETIMEDOUT;
190*4882a593Smuzhiyun 		} else {
191*4882a593Smuzhiyun 			do {
192*4882a593Smuzhiyun 				usleep_range(1000, 5000);
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 				ret = regmap_read(regmap, RM3100_REG_STATUS,
195*4882a593Smuzhiyun 						  &val);
196*4882a593Smuzhiyun 				if (ret < 0)
197*4882a593Smuzhiyun 					return ret;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 				if (val & RM3100_STATUS_DRDY)
200*4882a593Smuzhiyun 					break;
201*4882a593Smuzhiyun 			} while (--tries);
202*4882a593Smuzhiyun 			if (!tries)
203*4882a593Smuzhiyun 				return -ETIMEDOUT;
204*4882a593Smuzhiyun 		}
205*4882a593Smuzhiyun 	}
206*4882a593Smuzhiyun 	return 0;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun 
rm3100_read_mag(struct rm3100_data * data,int idx,int * val)209*4882a593Smuzhiyun static int rm3100_read_mag(struct rm3100_data *data, int idx, int *val)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun 	struct regmap *regmap = data->regmap;
212*4882a593Smuzhiyun 	u8 buffer[3];
213*4882a593Smuzhiyun 	int ret;
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	mutex_lock(&data->lock);
216*4882a593Smuzhiyun 	ret = regmap_write(regmap, RM3100_REG_POLL, BIT(4 + idx));
217*4882a593Smuzhiyun 	if (ret < 0)
218*4882a593Smuzhiyun 		goto unlock_return;
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	ret = rm3100_wait_measurement(data);
221*4882a593Smuzhiyun 	if (ret < 0)
222*4882a593Smuzhiyun 		goto unlock_return;
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	ret = regmap_bulk_read(regmap, RM3100_REG_MX2 + 3 * idx, buffer, 3);
225*4882a593Smuzhiyun 	if (ret < 0)
226*4882a593Smuzhiyun 		goto unlock_return;
227*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	*val = sign_extend32(get_unaligned_be24(&buffer[0]), 23);
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun 	return IIO_VAL_INT;
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun unlock_return:
234*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
235*4882a593Smuzhiyun 	return ret;
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun #define RM3100_CHANNEL(axis, idx)					\
239*4882a593Smuzhiyun 	{								\
240*4882a593Smuzhiyun 		.type = IIO_MAGN,					\
241*4882a593Smuzhiyun 		.modified = 1,						\
242*4882a593Smuzhiyun 		.channel2 = IIO_MOD_##axis,				\
243*4882a593Smuzhiyun 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
244*4882a593Smuzhiyun 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |	\
245*4882a593Smuzhiyun 			BIT(IIO_CHAN_INFO_SAMP_FREQ),			\
246*4882a593Smuzhiyun 		.scan_index = idx,					\
247*4882a593Smuzhiyun 		.scan_type = {						\
248*4882a593Smuzhiyun 			.sign = 's',					\
249*4882a593Smuzhiyun 			.realbits = 24,					\
250*4882a593Smuzhiyun 			.storagebits = 32,				\
251*4882a593Smuzhiyun 			.shift = 8,					\
252*4882a593Smuzhiyun 			.endianness = IIO_BE,				\
253*4882a593Smuzhiyun 		},							\
254*4882a593Smuzhiyun 	}
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun static const struct iio_chan_spec rm3100_channels[] = {
257*4882a593Smuzhiyun 	RM3100_CHANNEL(X, 0),
258*4882a593Smuzhiyun 	RM3100_CHANNEL(Y, 1),
259*4882a593Smuzhiyun 	RM3100_CHANNEL(Z, 2),
260*4882a593Smuzhiyun 	IIO_CHAN_SOFT_TIMESTAMP(3),
261*4882a593Smuzhiyun };
262*4882a593Smuzhiyun 
263*4882a593Smuzhiyun static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
264*4882a593Smuzhiyun 	"600 300 150 75 37 18 9 4.5 2.3 1.2 0.6 0.3 0.015 0.075"
265*4882a593Smuzhiyun );
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun static struct attribute *rm3100_attributes[] = {
268*4882a593Smuzhiyun 	&iio_const_attr_sampling_frequency_available.dev_attr.attr,
269*4882a593Smuzhiyun 	NULL,
270*4882a593Smuzhiyun };
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun static const struct attribute_group rm3100_attribute_group = {
273*4882a593Smuzhiyun 	.attrs = rm3100_attributes,
274*4882a593Smuzhiyun };
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun #define RM3100_SAMP_NUM			14
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun /*
279*4882a593Smuzhiyun  * Frequency : rm3100_samp_rates[][0].rm3100_samp_rates[][1]Hz.
280*4882a593Smuzhiyun  * Time between reading: rm3100_sam_rates[][2]ms.
281*4882a593Smuzhiyun  * The first one is actually 1.7ms.
282*4882a593Smuzhiyun  */
283*4882a593Smuzhiyun static const int rm3100_samp_rates[RM3100_SAMP_NUM][3] = {
284*4882a593Smuzhiyun 	{600, 0, 2}, {300, 0, 3}, {150, 0, 7}, {75, 0, 13}, {37, 0, 27},
285*4882a593Smuzhiyun 	{18, 0, 55}, {9, 0, 110}, {4, 500000, 220}, {2, 300000, 440},
286*4882a593Smuzhiyun 	{1, 200000, 800}, {0, 600000, 1600}, {0, 300000, 3300},
287*4882a593Smuzhiyun 	{0, 15000, 6700},  {0, 75000, 13000}
288*4882a593Smuzhiyun };
289*4882a593Smuzhiyun 
rm3100_get_samp_freq(struct rm3100_data * data,int * val,int * val2)290*4882a593Smuzhiyun static int rm3100_get_samp_freq(struct rm3100_data *data, int *val, int *val2)
291*4882a593Smuzhiyun {
292*4882a593Smuzhiyun 	unsigned int tmp;
293*4882a593Smuzhiyun 	int ret;
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	mutex_lock(&data->lock);
296*4882a593Smuzhiyun 	ret = regmap_read(data->regmap, RM3100_REG_TMRC, &tmp);
297*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
298*4882a593Smuzhiyun 	if (ret < 0)
299*4882a593Smuzhiyun 		return ret;
300*4882a593Smuzhiyun 	*val = rm3100_samp_rates[tmp - RM3100_TMRC_OFFSET][0];
301*4882a593Smuzhiyun 	*val2 = rm3100_samp_rates[tmp - RM3100_TMRC_OFFSET][1];
302*4882a593Smuzhiyun 
303*4882a593Smuzhiyun 	return IIO_VAL_INT_PLUS_MICRO;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun 
rm3100_set_cycle_count(struct rm3100_data * data,int val)306*4882a593Smuzhiyun static int rm3100_set_cycle_count(struct rm3100_data *data, int val)
307*4882a593Smuzhiyun {
308*4882a593Smuzhiyun 	int ret;
309*4882a593Smuzhiyun 	u8 i;
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	for (i = 0; i < 3; i++) {
312*4882a593Smuzhiyun 		ret = regmap_write(data->regmap, RM3100_REG_CC_X + 2 * i, val);
313*4882a593Smuzhiyun 		if (ret < 0)
314*4882a593Smuzhiyun 			return ret;
315*4882a593Smuzhiyun 	}
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	/*
318*4882a593Smuzhiyun 	 * The scale of this sensor depends on the cycle count value, these
319*4882a593Smuzhiyun 	 * three values are corresponding to the cycle count value 50, 100,
320*4882a593Smuzhiyun 	 * 200. scale = output / gain * 10^4.
321*4882a593Smuzhiyun 	 */
322*4882a593Smuzhiyun 	switch (val) {
323*4882a593Smuzhiyun 	case 50:
324*4882a593Smuzhiyun 		data->scale = 500;
325*4882a593Smuzhiyun 		break;
326*4882a593Smuzhiyun 	case 100:
327*4882a593Smuzhiyun 		data->scale = 263;
328*4882a593Smuzhiyun 		break;
329*4882a593Smuzhiyun 	/*
330*4882a593Smuzhiyun 	 * case 200:
331*4882a593Smuzhiyun 	 * This function will never be called by users' code, so here we
332*4882a593Smuzhiyun 	 * assume that it will never get a wrong parameter.
333*4882a593Smuzhiyun 	 */
334*4882a593Smuzhiyun 	default:
335*4882a593Smuzhiyun 		data->scale = 133;
336*4882a593Smuzhiyun 	}
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	return 0;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun 
rm3100_set_samp_freq(struct iio_dev * indio_dev,int val,int val2)341*4882a593Smuzhiyun static int rm3100_set_samp_freq(struct iio_dev *indio_dev, int val, int val2)
342*4882a593Smuzhiyun {
343*4882a593Smuzhiyun 	struct rm3100_data *data = iio_priv(indio_dev);
344*4882a593Smuzhiyun 	struct regmap *regmap = data->regmap;
345*4882a593Smuzhiyun 	unsigned int cycle_count;
346*4882a593Smuzhiyun 	int ret;
347*4882a593Smuzhiyun 	int i;
348*4882a593Smuzhiyun 
349*4882a593Smuzhiyun 	mutex_lock(&data->lock);
350*4882a593Smuzhiyun 	/* All cycle count registers use the same value. */
351*4882a593Smuzhiyun 	ret = regmap_read(regmap, RM3100_REG_CC_X, &cycle_count);
352*4882a593Smuzhiyun 	if (ret < 0)
353*4882a593Smuzhiyun 		goto unlock_return;
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun 	for (i = 0; i < RM3100_SAMP_NUM; i++) {
356*4882a593Smuzhiyun 		if (val == rm3100_samp_rates[i][0] &&
357*4882a593Smuzhiyun 		    val2 == rm3100_samp_rates[i][1])
358*4882a593Smuzhiyun 			break;
359*4882a593Smuzhiyun 	}
360*4882a593Smuzhiyun 	if (i == RM3100_SAMP_NUM) {
361*4882a593Smuzhiyun 		ret = -EINVAL;
362*4882a593Smuzhiyun 		goto unlock_return;
363*4882a593Smuzhiyun 	}
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun 	ret = regmap_write(regmap, RM3100_REG_TMRC, i + RM3100_TMRC_OFFSET);
366*4882a593Smuzhiyun 	if (ret < 0)
367*4882a593Smuzhiyun 		goto unlock_return;
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 	/* Checking if cycle count registers need changing. */
370*4882a593Smuzhiyun 	if (val == 600 && cycle_count == 200) {
371*4882a593Smuzhiyun 		ret = rm3100_set_cycle_count(data, 100);
372*4882a593Smuzhiyun 		if (ret < 0)
373*4882a593Smuzhiyun 			goto unlock_return;
374*4882a593Smuzhiyun 	} else if (val != 600 && cycle_count == 100) {
375*4882a593Smuzhiyun 		ret = rm3100_set_cycle_count(data, 200);
376*4882a593Smuzhiyun 		if (ret < 0)
377*4882a593Smuzhiyun 			goto unlock_return;
378*4882a593Smuzhiyun 	}
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 	if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) {
381*4882a593Smuzhiyun 		/* Writing TMRC registers requires CMM reset. */
382*4882a593Smuzhiyun 		ret = regmap_write(regmap, RM3100_REG_CMM, 0);
383*4882a593Smuzhiyun 		if (ret < 0)
384*4882a593Smuzhiyun 			goto unlock_return;
385*4882a593Smuzhiyun 		ret = regmap_write(data->regmap, RM3100_REG_CMM,
386*4882a593Smuzhiyun 			(*indio_dev->active_scan_mask & 0x7) <<
387*4882a593Smuzhiyun 			RM3100_CMM_AXIS_SHIFT | RM3100_CMM_START);
388*4882a593Smuzhiyun 		if (ret < 0)
389*4882a593Smuzhiyun 			goto unlock_return;
390*4882a593Smuzhiyun 	}
391*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	data->conversion_time = rm3100_samp_rates[i][2] * 2;
394*4882a593Smuzhiyun 	return 0;
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun unlock_return:
397*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
398*4882a593Smuzhiyun 	return ret;
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun 
rm3100_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long mask)401*4882a593Smuzhiyun static int rm3100_read_raw(struct iio_dev *indio_dev,
402*4882a593Smuzhiyun 			   const struct iio_chan_spec *chan,
403*4882a593Smuzhiyun 			   int *val, int *val2, long mask)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun 	struct rm3100_data *data = iio_priv(indio_dev);
406*4882a593Smuzhiyun 	int ret;
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	switch (mask) {
409*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
410*4882a593Smuzhiyun 		ret = iio_device_claim_direct_mode(indio_dev);
411*4882a593Smuzhiyun 		if (ret < 0)
412*4882a593Smuzhiyun 			return ret;
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 		ret = rm3100_read_mag(data, chan->scan_index, val);
415*4882a593Smuzhiyun 		iio_device_release_direct_mode(indio_dev);
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 		return ret;
418*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
419*4882a593Smuzhiyun 		*val = 0;
420*4882a593Smuzhiyun 		*val2 = data->scale;
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 		return IIO_VAL_INT_PLUS_MICRO;
423*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SAMP_FREQ:
424*4882a593Smuzhiyun 		return rm3100_get_samp_freq(data, val, val2);
425*4882a593Smuzhiyun 	default:
426*4882a593Smuzhiyun 		return -EINVAL;
427*4882a593Smuzhiyun 	}
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun 
rm3100_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)430*4882a593Smuzhiyun static int rm3100_write_raw(struct iio_dev *indio_dev,
431*4882a593Smuzhiyun 			    struct iio_chan_spec const *chan,
432*4882a593Smuzhiyun 			    int val, int val2, long mask)
433*4882a593Smuzhiyun {
434*4882a593Smuzhiyun 	switch (mask) {
435*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SAMP_FREQ:
436*4882a593Smuzhiyun 		return rm3100_set_samp_freq(indio_dev, val, val2);
437*4882a593Smuzhiyun 	default:
438*4882a593Smuzhiyun 		return -EINVAL;
439*4882a593Smuzhiyun 	}
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun 
442*4882a593Smuzhiyun static const struct iio_info rm3100_info = {
443*4882a593Smuzhiyun 	.attrs = &rm3100_attribute_group,
444*4882a593Smuzhiyun 	.read_raw = rm3100_read_raw,
445*4882a593Smuzhiyun 	.write_raw = rm3100_write_raw,
446*4882a593Smuzhiyun };
447*4882a593Smuzhiyun 
rm3100_buffer_preenable(struct iio_dev * indio_dev)448*4882a593Smuzhiyun static int rm3100_buffer_preenable(struct iio_dev *indio_dev)
449*4882a593Smuzhiyun {
450*4882a593Smuzhiyun 	struct rm3100_data *data = iio_priv(indio_dev);
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	/* Starting channels enabled. */
453*4882a593Smuzhiyun 	return regmap_write(data->regmap, RM3100_REG_CMM,
454*4882a593Smuzhiyun 		(*indio_dev->active_scan_mask & 0x7) << RM3100_CMM_AXIS_SHIFT |
455*4882a593Smuzhiyun 		RM3100_CMM_START);
456*4882a593Smuzhiyun }
457*4882a593Smuzhiyun 
rm3100_buffer_postdisable(struct iio_dev * indio_dev)458*4882a593Smuzhiyun static int rm3100_buffer_postdisable(struct iio_dev *indio_dev)
459*4882a593Smuzhiyun {
460*4882a593Smuzhiyun 	struct rm3100_data *data = iio_priv(indio_dev);
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun 	return regmap_write(data->regmap, RM3100_REG_CMM, 0);
463*4882a593Smuzhiyun }
464*4882a593Smuzhiyun 
465*4882a593Smuzhiyun static const struct iio_buffer_setup_ops rm3100_buffer_ops = {
466*4882a593Smuzhiyun 	.preenable = rm3100_buffer_preenable,
467*4882a593Smuzhiyun 	.postdisable = rm3100_buffer_postdisable,
468*4882a593Smuzhiyun };
469*4882a593Smuzhiyun 
rm3100_trigger_handler(int irq,void * p)470*4882a593Smuzhiyun static irqreturn_t rm3100_trigger_handler(int irq, void *p)
471*4882a593Smuzhiyun {
472*4882a593Smuzhiyun 	struct iio_poll_func *pf = p;
473*4882a593Smuzhiyun 	struct iio_dev *indio_dev = pf->indio_dev;
474*4882a593Smuzhiyun 	unsigned long scan_mask = *indio_dev->active_scan_mask;
475*4882a593Smuzhiyun 	unsigned int mask_len = indio_dev->masklength;
476*4882a593Smuzhiyun 	struct rm3100_data *data = iio_priv(indio_dev);
477*4882a593Smuzhiyun 	struct regmap *regmap = data->regmap;
478*4882a593Smuzhiyun 	int ret, i, bit;
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 	mutex_lock(&data->lock);
481*4882a593Smuzhiyun 	switch (scan_mask) {
482*4882a593Smuzhiyun 	case BIT(0) | BIT(1) | BIT(2):
483*4882a593Smuzhiyun 		ret = regmap_bulk_read(regmap, RM3100_REG_MX2, data->buffer, 9);
484*4882a593Smuzhiyun 		mutex_unlock(&data->lock);
485*4882a593Smuzhiyun 		if (ret < 0)
486*4882a593Smuzhiyun 			goto done;
487*4882a593Smuzhiyun 		/* Convert XXXYYYZZZxxx to XXXxYYYxZZZx. x for paddings. */
488*4882a593Smuzhiyun 		for (i = 2; i > 0; i--)
489*4882a593Smuzhiyun 			memmove(data->buffer + i * 4, data->buffer + i * 3, 3);
490*4882a593Smuzhiyun 		break;
491*4882a593Smuzhiyun 	case BIT(0) | BIT(1):
492*4882a593Smuzhiyun 		ret = regmap_bulk_read(regmap, RM3100_REG_MX2, data->buffer, 6);
493*4882a593Smuzhiyun 		mutex_unlock(&data->lock);
494*4882a593Smuzhiyun 		if (ret < 0)
495*4882a593Smuzhiyun 			goto done;
496*4882a593Smuzhiyun 		memmove(data->buffer + 4, data->buffer + 3, 3);
497*4882a593Smuzhiyun 		break;
498*4882a593Smuzhiyun 	case BIT(1) | BIT(2):
499*4882a593Smuzhiyun 		ret = regmap_bulk_read(regmap, RM3100_REG_MY2, data->buffer, 6);
500*4882a593Smuzhiyun 		mutex_unlock(&data->lock);
501*4882a593Smuzhiyun 		if (ret < 0)
502*4882a593Smuzhiyun 			goto done;
503*4882a593Smuzhiyun 		memmove(data->buffer + 4, data->buffer + 3, 3);
504*4882a593Smuzhiyun 		break;
505*4882a593Smuzhiyun 	case BIT(0) | BIT(2):
506*4882a593Smuzhiyun 		ret = regmap_bulk_read(regmap, RM3100_REG_MX2, data->buffer, 9);
507*4882a593Smuzhiyun 		mutex_unlock(&data->lock);
508*4882a593Smuzhiyun 		if (ret < 0)
509*4882a593Smuzhiyun 			goto done;
510*4882a593Smuzhiyun 		memmove(data->buffer + 4, data->buffer + 6, 3);
511*4882a593Smuzhiyun 		break;
512*4882a593Smuzhiyun 	default:
513*4882a593Smuzhiyun 		for_each_set_bit(bit, &scan_mask, mask_len) {
514*4882a593Smuzhiyun 			ret = regmap_bulk_read(regmap, RM3100_REG_MX2 + 3 * bit,
515*4882a593Smuzhiyun 					       data->buffer, 3);
516*4882a593Smuzhiyun 			if (ret < 0) {
517*4882a593Smuzhiyun 				mutex_unlock(&data->lock);
518*4882a593Smuzhiyun 				goto done;
519*4882a593Smuzhiyun 			}
520*4882a593Smuzhiyun 		}
521*4882a593Smuzhiyun 		mutex_unlock(&data->lock);
522*4882a593Smuzhiyun 	}
523*4882a593Smuzhiyun 	/*
524*4882a593Smuzhiyun 	 * Always using the same buffer so that we wouldn't need to set the
525*4882a593Smuzhiyun 	 * paddings to 0 in case of leaking any data.
526*4882a593Smuzhiyun 	 */
527*4882a593Smuzhiyun 	iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
528*4882a593Smuzhiyun 					   pf->timestamp);
529*4882a593Smuzhiyun done:
530*4882a593Smuzhiyun 	iio_trigger_notify_done(indio_dev->trig);
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 	return IRQ_HANDLED;
533*4882a593Smuzhiyun }
534*4882a593Smuzhiyun 
rm3100_common_probe(struct device * dev,struct regmap * regmap,int irq)535*4882a593Smuzhiyun int rm3100_common_probe(struct device *dev, struct regmap *regmap, int irq)
536*4882a593Smuzhiyun {
537*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
538*4882a593Smuzhiyun 	struct rm3100_data *data;
539*4882a593Smuzhiyun 	unsigned int tmp;
540*4882a593Smuzhiyun 	int ret;
541*4882a593Smuzhiyun 
542*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
543*4882a593Smuzhiyun 	if (!indio_dev)
544*4882a593Smuzhiyun 		return -ENOMEM;
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	data = iio_priv(indio_dev);
547*4882a593Smuzhiyun 	data->regmap = regmap;
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 	mutex_init(&data->lock);
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	indio_dev->name = "rm3100";
552*4882a593Smuzhiyun 	indio_dev->info = &rm3100_info;
553*4882a593Smuzhiyun 	indio_dev->channels = rm3100_channels;
554*4882a593Smuzhiyun 	indio_dev->num_channels = ARRAY_SIZE(rm3100_channels);
555*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_TRIGGERED;
556*4882a593Smuzhiyun 	indio_dev->currentmode = INDIO_DIRECT_MODE;
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	if (!irq)
559*4882a593Smuzhiyun 		data->use_interrupt = false;
560*4882a593Smuzhiyun 	else {
561*4882a593Smuzhiyun 		data->use_interrupt = true;
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun 		init_completion(&data->measuring_done);
564*4882a593Smuzhiyun 		ret = devm_request_threaded_irq(dev,
565*4882a593Smuzhiyun 						irq,
566*4882a593Smuzhiyun 						rm3100_irq_handler,
567*4882a593Smuzhiyun 						rm3100_thread_fn,
568*4882a593Smuzhiyun 						IRQF_TRIGGER_HIGH |
569*4882a593Smuzhiyun 						IRQF_ONESHOT,
570*4882a593Smuzhiyun 						indio_dev->name,
571*4882a593Smuzhiyun 						indio_dev);
572*4882a593Smuzhiyun 		if (ret < 0) {
573*4882a593Smuzhiyun 			dev_err(dev, "request irq line failed.\n");
574*4882a593Smuzhiyun 			return ret;
575*4882a593Smuzhiyun 		}
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun 		data->drdy_trig = devm_iio_trigger_alloc(dev, "%s-drdy%d",
578*4882a593Smuzhiyun 							 indio_dev->name,
579*4882a593Smuzhiyun 							 indio_dev->id);
580*4882a593Smuzhiyun 		if (!data->drdy_trig)
581*4882a593Smuzhiyun 			return -ENOMEM;
582*4882a593Smuzhiyun 
583*4882a593Smuzhiyun 		data->drdy_trig->dev.parent = dev;
584*4882a593Smuzhiyun 		ret = devm_iio_trigger_register(dev, data->drdy_trig);
585*4882a593Smuzhiyun 		if (ret < 0)
586*4882a593Smuzhiyun 			return ret;
587*4882a593Smuzhiyun 	}
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun 	ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
590*4882a593Smuzhiyun 					      &iio_pollfunc_store_time,
591*4882a593Smuzhiyun 					      rm3100_trigger_handler,
592*4882a593Smuzhiyun 					      &rm3100_buffer_ops);
593*4882a593Smuzhiyun 	if (ret < 0)
594*4882a593Smuzhiyun 		return ret;
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun 	ret = regmap_read(regmap, RM3100_REG_TMRC, &tmp);
597*4882a593Smuzhiyun 	if (ret < 0)
598*4882a593Smuzhiyun 		return ret;
599*4882a593Smuzhiyun 	/* Initializing max wait time, which is double conversion time. */
600*4882a593Smuzhiyun 	data->conversion_time = rm3100_samp_rates[tmp - RM3100_TMRC_OFFSET][2]
601*4882a593Smuzhiyun 				* 2;
602*4882a593Smuzhiyun 
603*4882a593Smuzhiyun 	/* Cycle count values may not be what we want. */
604*4882a593Smuzhiyun 	if ((tmp - RM3100_TMRC_OFFSET) == 0)
605*4882a593Smuzhiyun 		rm3100_set_cycle_count(data, 100);
606*4882a593Smuzhiyun 	else
607*4882a593Smuzhiyun 		rm3100_set_cycle_count(data, 200);
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	return devm_iio_device_register(dev, indio_dev);
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rm3100_common_probe);
612*4882a593Smuzhiyun 
613*4882a593Smuzhiyun MODULE_AUTHOR("Song Qiang <songqiang1304521@gmail.com>");
614*4882a593Smuzhiyun MODULE_DESCRIPTION("PNI RM3100 3-axis magnetometer i2c driver");
615*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
616