1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * MMC35240 - MEMSIC 3-axis Magnetic Sensor
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2015, Intel Corporation.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * IIO driver for MMC35240 (7-bit I2C slave address 0x30).
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * TODO: offset, ACPI, continuous measurement mode, PM
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/init.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/regmap.h>
17*4882a593Smuzhiyun #include <linux/acpi.h>
18*4882a593Smuzhiyun #include <linux/pm.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <linux/iio/iio.h>
21*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define MMC35240_DRV_NAME "mmc35240"
24*4882a593Smuzhiyun #define MMC35240_REGMAP_NAME "mmc35240_regmap"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define MMC35240_REG_XOUT_L 0x00
27*4882a593Smuzhiyun #define MMC35240_REG_XOUT_H 0x01
28*4882a593Smuzhiyun #define MMC35240_REG_YOUT_L 0x02
29*4882a593Smuzhiyun #define MMC35240_REG_YOUT_H 0x03
30*4882a593Smuzhiyun #define MMC35240_REG_ZOUT_L 0x04
31*4882a593Smuzhiyun #define MMC35240_REG_ZOUT_H 0x05
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun #define MMC35240_REG_STATUS 0x06
34*4882a593Smuzhiyun #define MMC35240_REG_CTRL0 0x07
35*4882a593Smuzhiyun #define MMC35240_REG_CTRL1 0x08
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define MMC35240_REG_ID 0x20
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define MMC35240_STATUS_MEAS_DONE_BIT BIT(0)
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define MMC35240_CTRL0_REFILL_BIT BIT(7)
42*4882a593Smuzhiyun #define MMC35240_CTRL0_RESET_BIT BIT(6)
43*4882a593Smuzhiyun #define MMC35240_CTRL0_SET_BIT BIT(5)
44*4882a593Smuzhiyun #define MMC35240_CTRL0_CMM_BIT BIT(1)
45*4882a593Smuzhiyun #define MMC35240_CTRL0_TM_BIT BIT(0)
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /* output resolution bits */
48*4882a593Smuzhiyun #define MMC35240_CTRL1_BW0_BIT BIT(0)
49*4882a593Smuzhiyun #define MMC35240_CTRL1_BW1_BIT BIT(1)
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #define MMC35240_CTRL1_BW_MASK (MMC35240_CTRL1_BW0_BIT | \
52*4882a593Smuzhiyun MMC35240_CTRL1_BW1_BIT)
53*4882a593Smuzhiyun #define MMC35240_CTRL1_BW_SHIFT 0
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun #define MMC35240_WAIT_CHARGE_PUMP 50000 /* us */
56*4882a593Smuzhiyun #define MMC35240_WAIT_SET_RESET 1000 /* us */
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /*
59*4882a593Smuzhiyun * Memsic OTP process code piece is put here for reference:
60*4882a593Smuzhiyun *
61*4882a593Smuzhiyun * #define OTP_CONVERT(REG) ((float)((REG) >=32 ? (32 - (REG)) : (REG)) * 0.006
62*4882a593Smuzhiyun * 1) For X axis, the COEFFICIENT is always 1.
63*4882a593Smuzhiyun * 2) For Y axis, the COEFFICIENT is as below:
64*4882a593Smuzhiyun * f_OTP_matrix[4] = OTP_CONVERT(((reg_data[1] & 0x03) << 4) |
65*4882a593Smuzhiyun * (reg_data[2] >> 4)) + 1.0;
66*4882a593Smuzhiyun * 3) For Z axis, the COEFFICIENT is as below:
67*4882a593Smuzhiyun * f_OTP_matrix[8] = (OTP_CONVERT(reg_data[3] & 0x3f) + 1) * 1.35;
68*4882a593Smuzhiyun * We implemented the OTP logic into driver.
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* scale = 1000 here for Y otp */
72*4882a593Smuzhiyun #define MMC35240_OTP_CONVERT_Y(REG) (((REG) >= 32 ? (32 - (REG)) : (REG)) * 6)
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* 0.6 * 1.35 = 0.81, scale 10000 for Z otp */
75*4882a593Smuzhiyun #define MMC35240_OTP_CONVERT_Z(REG) (((REG) >= 32 ? (32 - (REG)) : (REG)) * 81)
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #define MMC35240_X_COEFF(x) (x)
78*4882a593Smuzhiyun #define MMC35240_Y_COEFF(y) (y + 1000)
79*4882a593Smuzhiyun #define MMC35240_Z_COEFF(z) (z + 13500)
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define MMC35240_OTP_START_ADDR 0x1B
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun enum mmc35240_resolution {
84*4882a593Smuzhiyun MMC35240_16_BITS_SLOW = 0, /* 7.92 ms */
85*4882a593Smuzhiyun MMC35240_16_BITS_FAST, /* 4.08 ms */
86*4882a593Smuzhiyun MMC35240_14_BITS, /* 2.16 ms */
87*4882a593Smuzhiyun MMC35240_12_BITS, /* 1.20 ms */
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun enum mmc35240_axis {
91*4882a593Smuzhiyun AXIS_X = 0,
92*4882a593Smuzhiyun AXIS_Y,
93*4882a593Smuzhiyun AXIS_Z,
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun static const struct {
97*4882a593Smuzhiyun int sens[3]; /* sensitivity per X, Y, Z axis */
98*4882a593Smuzhiyun int nfo; /* null field output */
99*4882a593Smuzhiyun } mmc35240_props_table[] = {
100*4882a593Smuzhiyun /* 16 bits, 125Hz ODR */
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun {1024, 1024, 1024},
103*4882a593Smuzhiyun 32768,
104*4882a593Smuzhiyun },
105*4882a593Smuzhiyun /* 16 bits, 250Hz ODR */
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun {1024, 1024, 770},
108*4882a593Smuzhiyun 32768,
109*4882a593Smuzhiyun },
110*4882a593Smuzhiyun /* 14 bits, 450Hz ODR */
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun {256, 256, 193},
113*4882a593Smuzhiyun 8192,
114*4882a593Smuzhiyun },
115*4882a593Smuzhiyun /* 12 bits, 800Hz ODR */
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun {64, 64, 48},
118*4882a593Smuzhiyun 2048,
119*4882a593Smuzhiyun },
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun struct mmc35240_data {
123*4882a593Smuzhiyun struct i2c_client *client;
124*4882a593Smuzhiyun struct mutex mutex;
125*4882a593Smuzhiyun struct regmap *regmap;
126*4882a593Smuzhiyun enum mmc35240_resolution res;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun /* OTP compensation */
129*4882a593Smuzhiyun int axis_coef[3];
130*4882a593Smuzhiyun int axis_scale[3];
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun static const struct {
134*4882a593Smuzhiyun int val;
135*4882a593Smuzhiyun int val2;
136*4882a593Smuzhiyun } mmc35240_samp_freq[] = { {1, 500000},
137*4882a593Smuzhiyun {13, 0},
138*4882a593Smuzhiyun {25, 0},
139*4882a593Smuzhiyun {50, 0} };
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("1.5 13 25 50");
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun #define MMC35240_CHANNEL(_axis) { \
144*4882a593Smuzhiyun .type = IIO_MAGN, \
145*4882a593Smuzhiyun .modified = 1, \
146*4882a593Smuzhiyun .channel2 = IIO_MOD_ ## _axis, \
147*4882a593Smuzhiyun .address = AXIS_ ## _axis, \
148*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
149*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
150*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE), \
151*4882a593Smuzhiyun }
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun static const struct iio_chan_spec mmc35240_channels[] = {
154*4882a593Smuzhiyun MMC35240_CHANNEL(X),
155*4882a593Smuzhiyun MMC35240_CHANNEL(Y),
156*4882a593Smuzhiyun MMC35240_CHANNEL(Z),
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun static struct attribute *mmc35240_attributes[] = {
160*4882a593Smuzhiyun &iio_const_attr_sampling_frequency_available.dev_attr.attr,
161*4882a593Smuzhiyun NULL
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun static const struct attribute_group mmc35240_attribute_group = {
165*4882a593Smuzhiyun .attrs = mmc35240_attributes,
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun
mmc35240_get_samp_freq_index(struct mmc35240_data * data,int val,int val2)168*4882a593Smuzhiyun static int mmc35240_get_samp_freq_index(struct mmc35240_data *data,
169*4882a593Smuzhiyun int val, int val2)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun int i;
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(mmc35240_samp_freq); i++)
174*4882a593Smuzhiyun if (mmc35240_samp_freq[i].val == val &&
175*4882a593Smuzhiyun mmc35240_samp_freq[i].val2 == val2)
176*4882a593Smuzhiyun return i;
177*4882a593Smuzhiyun return -EINVAL;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
mmc35240_hw_set(struct mmc35240_data * data,bool set)180*4882a593Smuzhiyun static int mmc35240_hw_set(struct mmc35240_data *data, bool set)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun int ret;
183*4882a593Smuzhiyun u8 coil_bit;
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /*
186*4882a593Smuzhiyun * Recharge the capacitor at VCAP pin, requested to be issued
187*4882a593Smuzhiyun * before a SET/RESET command.
188*4882a593Smuzhiyun */
189*4882a593Smuzhiyun ret = regmap_update_bits(data->regmap, MMC35240_REG_CTRL0,
190*4882a593Smuzhiyun MMC35240_CTRL0_REFILL_BIT,
191*4882a593Smuzhiyun MMC35240_CTRL0_REFILL_BIT);
192*4882a593Smuzhiyun if (ret < 0)
193*4882a593Smuzhiyun return ret;
194*4882a593Smuzhiyun usleep_range(MMC35240_WAIT_CHARGE_PUMP, MMC35240_WAIT_CHARGE_PUMP + 1);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun if (set)
197*4882a593Smuzhiyun coil_bit = MMC35240_CTRL0_SET_BIT;
198*4882a593Smuzhiyun else
199*4882a593Smuzhiyun coil_bit = MMC35240_CTRL0_RESET_BIT;
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun return regmap_update_bits(data->regmap, MMC35240_REG_CTRL0,
202*4882a593Smuzhiyun coil_bit, coil_bit);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun
mmc35240_init(struct mmc35240_data * data)206*4882a593Smuzhiyun static int mmc35240_init(struct mmc35240_data *data)
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun int ret, y_convert, z_convert;
209*4882a593Smuzhiyun unsigned int reg_id;
210*4882a593Smuzhiyun u8 otp_data[6];
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun ret = regmap_read(data->regmap, MMC35240_REG_ID, ®_id);
213*4882a593Smuzhiyun if (ret < 0) {
214*4882a593Smuzhiyun dev_err(&data->client->dev, "Error reading product id\n");
215*4882a593Smuzhiyun return ret;
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun dev_dbg(&data->client->dev, "MMC35240 chip id %x\n", reg_id);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun /*
221*4882a593Smuzhiyun * make sure we restore sensor characteristics, by doing
222*4882a593Smuzhiyun * a SET/RESET sequence, the axis polarity being naturally
223*4882a593Smuzhiyun * aligned after RESET
224*4882a593Smuzhiyun */
225*4882a593Smuzhiyun ret = mmc35240_hw_set(data, true);
226*4882a593Smuzhiyun if (ret < 0)
227*4882a593Smuzhiyun return ret;
228*4882a593Smuzhiyun usleep_range(MMC35240_WAIT_SET_RESET, MMC35240_WAIT_SET_RESET + 1);
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun ret = mmc35240_hw_set(data, false);
231*4882a593Smuzhiyun if (ret < 0)
232*4882a593Smuzhiyun return ret;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun /* set default sampling frequency */
235*4882a593Smuzhiyun ret = regmap_update_bits(data->regmap, MMC35240_REG_CTRL1,
236*4882a593Smuzhiyun MMC35240_CTRL1_BW_MASK,
237*4882a593Smuzhiyun data->res << MMC35240_CTRL1_BW_SHIFT);
238*4882a593Smuzhiyun if (ret < 0)
239*4882a593Smuzhiyun return ret;
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun ret = regmap_bulk_read(data->regmap, MMC35240_OTP_START_ADDR,
242*4882a593Smuzhiyun otp_data, sizeof(otp_data));
243*4882a593Smuzhiyun if (ret < 0)
244*4882a593Smuzhiyun return ret;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun y_convert = MMC35240_OTP_CONVERT_Y(((otp_data[1] & 0x03) << 4) |
247*4882a593Smuzhiyun (otp_data[2] >> 4));
248*4882a593Smuzhiyun z_convert = MMC35240_OTP_CONVERT_Z(otp_data[3] & 0x3f);
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun data->axis_coef[0] = MMC35240_X_COEFF(1);
251*4882a593Smuzhiyun data->axis_coef[1] = MMC35240_Y_COEFF(y_convert);
252*4882a593Smuzhiyun data->axis_coef[2] = MMC35240_Z_COEFF(z_convert);
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun data->axis_scale[0] = 1;
255*4882a593Smuzhiyun data->axis_scale[1] = 1000;
256*4882a593Smuzhiyun data->axis_scale[2] = 10000;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun return 0;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
mmc35240_take_measurement(struct mmc35240_data * data)261*4882a593Smuzhiyun static int mmc35240_take_measurement(struct mmc35240_data *data)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun int ret, tries = 100;
264*4882a593Smuzhiyun unsigned int reg_status;
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun ret = regmap_write(data->regmap, MMC35240_REG_CTRL0,
267*4882a593Smuzhiyun MMC35240_CTRL0_TM_BIT);
268*4882a593Smuzhiyun if (ret < 0)
269*4882a593Smuzhiyun return ret;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun while (tries-- > 0) {
272*4882a593Smuzhiyun ret = regmap_read(data->regmap, MMC35240_REG_STATUS,
273*4882a593Smuzhiyun ®_status);
274*4882a593Smuzhiyun if (ret < 0)
275*4882a593Smuzhiyun return ret;
276*4882a593Smuzhiyun if (reg_status & MMC35240_STATUS_MEAS_DONE_BIT)
277*4882a593Smuzhiyun break;
278*4882a593Smuzhiyun /* minimum wait time to complete measurement is 10 ms */
279*4882a593Smuzhiyun usleep_range(10000, 11000);
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun if (tries < 0) {
283*4882a593Smuzhiyun dev_err(&data->client->dev, "data not ready\n");
284*4882a593Smuzhiyun return -EIO;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun return 0;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun
mmc35240_read_measurement(struct mmc35240_data * data,__le16 buf[3])290*4882a593Smuzhiyun static int mmc35240_read_measurement(struct mmc35240_data *data, __le16 buf[3])
291*4882a593Smuzhiyun {
292*4882a593Smuzhiyun int ret;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun ret = mmc35240_take_measurement(data);
295*4882a593Smuzhiyun if (ret < 0)
296*4882a593Smuzhiyun return ret;
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun return regmap_bulk_read(data->regmap, MMC35240_REG_XOUT_L, buf,
299*4882a593Smuzhiyun 3 * sizeof(__le16));
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun /**
303*4882a593Smuzhiyun * mmc35240_raw_to_mgauss - convert raw readings to milli gauss. Also apply
304*4882a593Smuzhiyun * compensation for output value.
305*4882a593Smuzhiyun *
306*4882a593Smuzhiyun * @data: device private data
307*4882a593Smuzhiyun * @index: axis index for which we want the conversion
308*4882a593Smuzhiyun * @buf: raw data to be converted, 2 bytes in little endian format
309*4882a593Smuzhiyun * @val: compensated output reading (unit is milli gauss)
310*4882a593Smuzhiyun *
311*4882a593Smuzhiyun * Returns: 0 in case of success, -EINVAL when @index is not valid
312*4882a593Smuzhiyun */
mmc35240_raw_to_mgauss(struct mmc35240_data * data,int index,__le16 buf[],int * val)313*4882a593Smuzhiyun static int mmc35240_raw_to_mgauss(struct mmc35240_data *data, int index,
314*4882a593Smuzhiyun __le16 buf[], int *val)
315*4882a593Smuzhiyun {
316*4882a593Smuzhiyun int raw[3];
317*4882a593Smuzhiyun int sens[3];
318*4882a593Smuzhiyun int nfo;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun raw[AXIS_X] = le16_to_cpu(buf[AXIS_X]);
321*4882a593Smuzhiyun raw[AXIS_Y] = le16_to_cpu(buf[AXIS_Y]);
322*4882a593Smuzhiyun raw[AXIS_Z] = le16_to_cpu(buf[AXIS_Z]);
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun sens[AXIS_X] = mmc35240_props_table[data->res].sens[AXIS_X];
325*4882a593Smuzhiyun sens[AXIS_Y] = mmc35240_props_table[data->res].sens[AXIS_Y];
326*4882a593Smuzhiyun sens[AXIS_Z] = mmc35240_props_table[data->res].sens[AXIS_Z];
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun nfo = mmc35240_props_table[data->res].nfo;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun switch (index) {
331*4882a593Smuzhiyun case AXIS_X:
332*4882a593Smuzhiyun *val = (raw[AXIS_X] - nfo) * 1000 / sens[AXIS_X];
333*4882a593Smuzhiyun break;
334*4882a593Smuzhiyun case AXIS_Y:
335*4882a593Smuzhiyun *val = (raw[AXIS_Y] - nfo) * 1000 / sens[AXIS_Y] -
336*4882a593Smuzhiyun (raw[AXIS_Z] - nfo) * 1000 / sens[AXIS_Z];
337*4882a593Smuzhiyun break;
338*4882a593Smuzhiyun case AXIS_Z:
339*4882a593Smuzhiyun *val = (raw[AXIS_Y] - nfo) * 1000 / sens[AXIS_Y] +
340*4882a593Smuzhiyun (raw[AXIS_Z] - nfo) * 1000 / sens[AXIS_Z];
341*4882a593Smuzhiyun break;
342*4882a593Smuzhiyun default:
343*4882a593Smuzhiyun return -EINVAL;
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun /* apply OTP compensation */
346*4882a593Smuzhiyun *val = (*val) * data->axis_coef[index] / data->axis_scale[index];
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun return 0;
349*4882a593Smuzhiyun }
350*4882a593Smuzhiyun
mmc35240_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)351*4882a593Smuzhiyun static int mmc35240_read_raw(struct iio_dev *indio_dev,
352*4882a593Smuzhiyun struct iio_chan_spec const *chan, int *val,
353*4882a593Smuzhiyun int *val2, long mask)
354*4882a593Smuzhiyun {
355*4882a593Smuzhiyun struct mmc35240_data *data = iio_priv(indio_dev);
356*4882a593Smuzhiyun int ret, i;
357*4882a593Smuzhiyun unsigned int reg;
358*4882a593Smuzhiyun __le16 buf[3];
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun switch (mask) {
361*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
362*4882a593Smuzhiyun mutex_lock(&data->mutex);
363*4882a593Smuzhiyun ret = mmc35240_read_measurement(data, buf);
364*4882a593Smuzhiyun mutex_unlock(&data->mutex);
365*4882a593Smuzhiyun if (ret < 0)
366*4882a593Smuzhiyun return ret;
367*4882a593Smuzhiyun ret = mmc35240_raw_to_mgauss(data, chan->address, buf, val);
368*4882a593Smuzhiyun if (ret < 0)
369*4882a593Smuzhiyun return ret;
370*4882a593Smuzhiyun return IIO_VAL_INT;
371*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
372*4882a593Smuzhiyun *val = 0;
373*4882a593Smuzhiyun *val2 = 1000;
374*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
375*4882a593Smuzhiyun case IIO_CHAN_INFO_SAMP_FREQ:
376*4882a593Smuzhiyun mutex_lock(&data->mutex);
377*4882a593Smuzhiyun ret = regmap_read(data->regmap, MMC35240_REG_CTRL1, ®);
378*4882a593Smuzhiyun mutex_unlock(&data->mutex);
379*4882a593Smuzhiyun if (ret < 0)
380*4882a593Smuzhiyun return ret;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun i = (reg & MMC35240_CTRL1_BW_MASK) >> MMC35240_CTRL1_BW_SHIFT;
383*4882a593Smuzhiyun if (i < 0 || i >= ARRAY_SIZE(mmc35240_samp_freq))
384*4882a593Smuzhiyun return -EINVAL;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun *val = mmc35240_samp_freq[i].val;
387*4882a593Smuzhiyun *val2 = mmc35240_samp_freq[i].val2;
388*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
389*4882a593Smuzhiyun default:
390*4882a593Smuzhiyun return -EINVAL;
391*4882a593Smuzhiyun }
392*4882a593Smuzhiyun }
393*4882a593Smuzhiyun
mmc35240_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)394*4882a593Smuzhiyun static int mmc35240_write_raw(struct iio_dev *indio_dev,
395*4882a593Smuzhiyun struct iio_chan_spec const *chan, int val,
396*4882a593Smuzhiyun int val2, long mask)
397*4882a593Smuzhiyun {
398*4882a593Smuzhiyun struct mmc35240_data *data = iio_priv(indio_dev);
399*4882a593Smuzhiyun int i, ret;
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun switch (mask) {
402*4882a593Smuzhiyun case IIO_CHAN_INFO_SAMP_FREQ:
403*4882a593Smuzhiyun i = mmc35240_get_samp_freq_index(data, val, val2);
404*4882a593Smuzhiyun if (i < 0)
405*4882a593Smuzhiyun return -EINVAL;
406*4882a593Smuzhiyun mutex_lock(&data->mutex);
407*4882a593Smuzhiyun ret = regmap_update_bits(data->regmap, MMC35240_REG_CTRL1,
408*4882a593Smuzhiyun MMC35240_CTRL1_BW_MASK,
409*4882a593Smuzhiyun i << MMC35240_CTRL1_BW_SHIFT);
410*4882a593Smuzhiyun mutex_unlock(&data->mutex);
411*4882a593Smuzhiyun return ret;
412*4882a593Smuzhiyun default:
413*4882a593Smuzhiyun return -EINVAL;
414*4882a593Smuzhiyun }
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun static const struct iio_info mmc35240_info = {
418*4882a593Smuzhiyun .read_raw = mmc35240_read_raw,
419*4882a593Smuzhiyun .write_raw = mmc35240_write_raw,
420*4882a593Smuzhiyun .attrs = &mmc35240_attribute_group,
421*4882a593Smuzhiyun };
422*4882a593Smuzhiyun
mmc35240_is_writeable_reg(struct device * dev,unsigned int reg)423*4882a593Smuzhiyun static bool mmc35240_is_writeable_reg(struct device *dev, unsigned int reg)
424*4882a593Smuzhiyun {
425*4882a593Smuzhiyun switch (reg) {
426*4882a593Smuzhiyun case MMC35240_REG_CTRL0:
427*4882a593Smuzhiyun case MMC35240_REG_CTRL1:
428*4882a593Smuzhiyun return true;
429*4882a593Smuzhiyun default:
430*4882a593Smuzhiyun return false;
431*4882a593Smuzhiyun }
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun
mmc35240_is_readable_reg(struct device * dev,unsigned int reg)434*4882a593Smuzhiyun static bool mmc35240_is_readable_reg(struct device *dev, unsigned int reg)
435*4882a593Smuzhiyun {
436*4882a593Smuzhiyun switch (reg) {
437*4882a593Smuzhiyun case MMC35240_REG_XOUT_L:
438*4882a593Smuzhiyun case MMC35240_REG_XOUT_H:
439*4882a593Smuzhiyun case MMC35240_REG_YOUT_L:
440*4882a593Smuzhiyun case MMC35240_REG_YOUT_H:
441*4882a593Smuzhiyun case MMC35240_REG_ZOUT_L:
442*4882a593Smuzhiyun case MMC35240_REG_ZOUT_H:
443*4882a593Smuzhiyun case MMC35240_REG_STATUS:
444*4882a593Smuzhiyun case MMC35240_REG_ID:
445*4882a593Smuzhiyun return true;
446*4882a593Smuzhiyun default:
447*4882a593Smuzhiyun return false;
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun
mmc35240_is_volatile_reg(struct device * dev,unsigned int reg)451*4882a593Smuzhiyun static bool mmc35240_is_volatile_reg(struct device *dev, unsigned int reg)
452*4882a593Smuzhiyun {
453*4882a593Smuzhiyun switch (reg) {
454*4882a593Smuzhiyun case MMC35240_REG_CTRL0:
455*4882a593Smuzhiyun case MMC35240_REG_CTRL1:
456*4882a593Smuzhiyun return false;
457*4882a593Smuzhiyun default:
458*4882a593Smuzhiyun return true;
459*4882a593Smuzhiyun }
460*4882a593Smuzhiyun }
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun static const struct reg_default mmc35240_reg_defaults[] = {
463*4882a593Smuzhiyun { MMC35240_REG_CTRL0, 0x00 },
464*4882a593Smuzhiyun { MMC35240_REG_CTRL1, 0x00 },
465*4882a593Smuzhiyun };
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun static const struct regmap_config mmc35240_regmap_config = {
468*4882a593Smuzhiyun .name = MMC35240_REGMAP_NAME,
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun .reg_bits = 8,
471*4882a593Smuzhiyun .val_bits = 8,
472*4882a593Smuzhiyun
473*4882a593Smuzhiyun .max_register = MMC35240_REG_ID,
474*4882a593Smuzhiyun .cache_type = REGCACHE_FLAT,
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun .writeable_reg = mmc35240_is_writeable_reg,
477*4882a593Smuzhiyun .readable_reg = mmc35240_is_readable_reg,
478*4882a593Smuzhiyun .volatile_reg = mmc35240_is_volatile_reg,
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun .reg_defaults = mmc35240_reg_defaults,
481*4882a593Smuzhiyun .num_reg_defaults = ARRAY_SIZE(mmc35240_reg_defaults),
482*4882a593Smuzhiyun };
483*4882a593Smuzhiyun
mmc35240_probe(struct i2c_client * client,const struct i2c_device_id * id)484*4882a593Smuzhiyun static int mmc35240_probe(struct i2c_client *client,
485*4882a593Smuzhiyun const struct i2c_device_id *id)
486*4882a593Smuzhiyun {
487*4882a593Smuzhiyun struct mmc35240_data *data;
488*4882a593Smuzhiyun struct iio_dev *indio_dev;
489*4882a593Smuzhiyun struct regmap *regmap;
490*4882a593Smuzhiyun int ret;
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
493*4882a593Smuzhiyun if (!indio_dev)
494*4882a593Smuzhiyun return -ENOMEM;
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun regmap = devm_regmap_init_i2c(client, &mmc35240_regmap_config);
497*4882a593Smuzhiyun if (IS_ERR(regmap)) {
498*4882a593Smuzhiyun dev_err(&client->dev, "regmap initialization failed\n");
499*4882a593Smuzhiyun return PTR_ERR(regmap);
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun data = iio_priv(indio_dev);
503*4882a593Smuzhiyun i2c_set_clientdata(client, indio_dev);
504*4882a593Smuzhiyun data->client = client;
505*4882a593Smuzhiyun data->regmap = regmap;
506*4882a593Smuzhiyun data->res = MMC35240_16_BITS_SLOW;
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun mutex_init(&data->mutex);
509*4882a593Smuzhiyun
510*4882a593Smuzhiyun indio_dev->info = &mmc35240_info;
511*4882a593Smuzhiyun indio_dev->name = MMC35240_DRV_NAME;
512*4882a593Smuzhiyun indio_dev->channels = mmc35240_channels;
513*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(mmc35240_channels);
514*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun ret = mmc35240_init(data);
517*4882a593Smuzhiyun if (ret < 0) {
518*4882a593Smuzhiyun dev_err(&client->dev, "mmc35240 chip init failed\n");
519*4882a593Smuzhiyun return ret;
520*4882a593Smuzhiyun }
521*4882a593Smuzhiyun return devm_iio_device_register(&client->dev, indio_dev);
522*4882a593Smuzhiyun }
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
mmc35240_suspend(struct device * dev)525*4882a593Smuzhiyun static int mmc35240_suspend(struct device *dev)
526*4882a593Smuzhiyun {
527*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
528*4882a593Smuzhiyun struct mmc35240_data *data = iio_priv(indio_dev);
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun regcache_cache_only(data->regmap, true);
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun return 0;
533*4882a593Smuzhiyun }
534*4882a593Smuzhiyun
mmc35240_resume(struct device * dev)535*4882a593Smuzhiyun static int mmc35240_resume(struct device *dev)
536*4882a593Smuzhiyun {
537*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
538*4882a593Smuzhiyun struct mmc35240_data *data = iio_priv(indio_dev);
539*4882a593Smuzhiyun int ret;
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun regcache_mark_dirty(data->regmap);
542*4882a593Smuzhiyun ret = regcache_sync_region(data->regmap, MMC35240_REG_CTRL0,
543*4882a593Smuzhiyun MMC35240_REG_CTRL1);
544*4882a593Smuzhiyun if (ret < 0)
545*4882a593Smuzhiyun dev_err(dev, "Failed to restore control registers\n");
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun regcache_cache_only(data->regmap, false);
548*4882a593Smuzhiyun
549*4882a593Smuzhiyun return 0;
550*4882a593Smuzhiyun }
551*4882a593Smuzhiyun #endif
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun static const struct dev_pm_ops mmc35240_pm_ops = {
554*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(mmc35240_suspend, mmc35240_resume)
555*4882a593Smuzhiyun };
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun static const struct of_device_id mmc35240_of_match[] = {
558*4882a593Smuzhiyun { .compatible = "memsic,mmc35240", },
559*4882a593Smuzhiyun { }
560*4882a593Smuzhiyun };
561*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, mmc35240_of_match);
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun static const struct acpi_device_id mmc35240_acpi_match[] = {
564*4882a593Smuzhiyun {"MMC35240", 0},
565*4882a593Smuzhiyun { },
566*4882a593Smuzhiyun };
567*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, mmc35240_acpi_match);
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun static const struct i2c_device_id mmc35240_id[] = {
570*4882a593Smuzhiyun {"mmc35240", 0},
571*4882a593Smuzhiyun {}
572*4882a593Smuzhiyun };
573*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, mmc35240_id);
574*4882a593Smuzhiyun
575*4882a593Smuzhiyun static struct i2c_driver mmc35240_driver = {
576*4882a593Smuzhiyun .driver = {
577*4882a593Smuzhiyun .name = MMC35240_DRV_NAME,
578*4882a593Smuzhiyun .of_match_table = mmc35240_of_match,
579*4882a593Smuzhiyun .pm = &mmc35240_pm_ops,
580*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(mmc35240_acpi_match),
581*4882a593Smuzhiyun },
582*4882a593Smuzhiyun .probe = mmc35240_probe,
583*4882a593Smuzhiyun .id_table = mmc35240_id,
584*4882a593Smuzhiyun };
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun module_i2c_driver(mmc35240_driver);
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
589*4882a593Smuzhiyun MODULE_DESCRIPTION("MEMSIC MMC35240 magnetic sensor driver");
590*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
591