1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Bosch BMC150 three-axis magnetic field sensor driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2015, Intel Corporation.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * This code is based on bmm050_api.c authored by contact@bosch.sensortec.com:
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * (C) Copyright 2011~2014 Bosch Sensortec GmbH All Rights Reserved
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun #include <linux/delay.h>
16*4882a593Smuzhiyun #include <linux/slab.h>
17*4882a593Smuzhiyun #include <linux/acpi.h>
18*4882a593Smuzhiyun #include <linux/pm.h>
19*4882a593Smuzhiyun #include <linux/pm_runtime.h>
20*4882a593Smuzhiyun #include <linux/iio/iio.h>
21*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
22*4882a593Smuzhiyun #include <linux/iio/buffer.h>
23*4882a593Smuzhiyun #include <linux/iio/events.h>
24*4882a593Smuzhiyun #include <linux/iio/trigger.h>
25*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
26*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
27*4882a593Smuzhiyun #include <linux/regmap.h>
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #include "bmc150_magn.h"
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define BMC150_MAGN_DRV_NAME "bmc150_magn"
32*4882a593Smuzhiyun #define BMC150_MAGN_IRQ_NAME "bmc150_magn_event"
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun #define BMC150_MAGN_REG_CHIP_ID 0x40
35*4882a593Smuzhiyun #define BMC150_MAGN_CHIP_ID_VAL 0x32
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define BMC150_MAGN_REG_X_L 0x42
38*4882a593Smuzhiyun #define BMC150_MAGN_REG_X_M 0x43
39*4882a593Smuzhiyun #define BMC150_MAGN_REG_Y_L 0x44
40*4882a593Smuzhiyun #define BMC150_MAGN_REG_Y_M 0x45
41*4882a593Smuzhiyun #define BMC150_MAGN_SHIFT_XY_L 3
42*4882a593Smuzhiyun #define BMC150_MAGN_REG_Z_L 0x46
43*4882a593Smuzhiyun #define BMC150_MAGN_REG_Z_M 0x47
44*4882a593Smuzhiyun #define BMC150_MAGN_SHIFT_Z_L 1
45*4882a593Smuzhiyun #define BMC150_MAGN_REG_RHALL_L 0x48
46*4882a593Smuzhiyun #define BMC150_MAGN_REG_RHALL_M 0x49
47*4882a593Smuzhiyun #define BMC150_MAGN_SHIFT_RHALL_L 2
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #define BMC150_MAGN_REG_INT_STATUS 0x4A
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #define BMC150_MAGN_REG_POWER 0x4B
52*4882a593Smuzhiyun #define BMC150_MAGN_MASK_POWER_CTL BIT(0)
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define BMC150_MAGN_REG_OPMODE_ODR 0x4C
55*4882a593Smuzhiyun #define BMC150_MAGN_MASK_OPMODE GENMASK(2, 1)
56*4882a593Smuzhiyun #define BMC150_MAGN_SHIFT_OPMODE 1
57*4882a593Smuzhiyun #define BMC150_MAGN_MODE_NORMAL 0x00
58*4882a593Smuzhiyun #define BMC150_MAGN_MODE_FORCED 0x01
59*4882a593Smuzhiyun #define BMC150_MAGN_MODE_SLEEP 0x03
60*4882a593Smuzhiyun #define BMC150_MAGN_MASK_ODR GENMASK(5, 3)
61*4882a593Smuzhiyun #define BMC150_MAGN_SHIFT_ODR 3
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun #define BMC150_MAGN_REG_INT 0x4D
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #define BMC150_MAGN_REG_INT_DRDY 0x4E
66*4882a593Smuzhiyun #define BMC150_MAGN_MASK_DRDY_EN BIT(7)
67*4882a593Smuzhiyun #define BMC150_MAGN_SHIFT_DRDY_EN 7
68*4882a593Smuzhiyun #define BMC150_MAGN_MASK_DRDY_INT3 BIT(6)
69*4882a593Smuzhiyun #define BMC150_MAGN_MASK_DRDY_Z_EN BIT(5)
70*4882a593Smuzhiyun #define BMC150_MAGN_MASK_DRDY_Y_EN BIT(4)
71*4882a593Smuzhiyun #define BMC150_MAGN_MASK_DRDY_X_EN BIT(3)
72*4882a593Smuzhiyun #define BMC150_MAGN_MASK_DRDY_DR_POLARITY BIT(2)
73*4882a593Smuzhiyun #define BMC150_MAGN_MASK_DRDY_LATCHING BIT(1)
74*4882a593Smuzhiyun #define BMC150_MAGN_MASK_DRDY_INT3_POLARITY BIT(0)
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define BMC150_MAGN_REG_LOW_THRESH 0x4F
77*4882a593Smuzhiyun #define BMC150_MAGN_REG_HIGH_THRESH 0x50
78*4882a593Smuzhiyun #define BMC150_MAGN_REG_REP_XY 0x51
79*4882a593Smuzhiyun #define BMC150_MAGN_REG_REP_Z 0x52
80*4882a593Smuzhiyun #define BMC150_MAGN_REG_REP_DATAMASK GENMASK(7, 0)
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun #define BMC150_MAGN_REG_TRIM_START 0x5D
83*4882a593Smuzhiyun #define BMC150_MAGN_REG_TRIM_END 0x71
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #define BMC150_MAGN_XY_OVERFLOW_VAL -4096
86*4882a593Smuzhiyun #define BMC150_MAGN_Z_OVERFLOW_VAL -16384
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* Time from SUSPEND to SLEEP */
89*4882a593Smuzhiyun #define BMC150_MAGN_START_UP_TIME_MS 3
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun #define BMC150_MAGN_AUTO_SUSPEND_DELAY_MS 2000
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun #define BMC150_MAGN_REGVAL_TO_REPXY(regval) (((regval) * 2) + 1)
94*4882a593Smuzhiyun #define BMC150_MAGN_REGVAL_TO_REPZ(regval) ((regval) + 1)
95*4882a593Smuzhiyun #define BMC150_MAGN_REPXY_TO_REGVAL(rep) (((rep) - 1) / 2)
96*4882a593Smuzhiyun #define BMC150_MAGN_REPZ_TO_REGVAL(rep) ((rep) - 1)
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun enum bmc150_magn_axis {
99*4882a593Smuzhiyun AXIS_X,
100*4882a593Smuzhiyun AXIS_Y,
101*4882a593Smuzhiyun AXIS_Z,
102*4882a593Smuzhiyun RHALL,
103*4882a593Smuzhiyun AXIS_XYZ_MAX = RHALL,
104*4882a593Smuzhiyun AXIS_XYZR_MAX,
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun enum bmc150_magn_power_modes {
108*4882a593Smuzhiyun BMC150_MAGN_POWER_MODE_SUSPEND,
109*4882a593Smuzhiyun BMC150_MAGN_POWER_MODE_SLEEP,
110*4882a593Smuzhiyun BMC150_MAGN_POWER_MODE_NORMAL,
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun struct bmc150_magn_trim_regs {
114*4882a593Smuzhiyun s8 x1;
115*4882a593Smuzhiyun s8 y1;
116*4882a593Smuzhiyun __le16 reserved1;
117*4882a593Smuzhiyun u8 reserved2;
118*4882a593Smuzhiyun __le16 z4;
119*4882a593Smuzhiyun s8 x2;
120*4882a593Smuzhiyun s8 y2;
121*4882a593Smuzhiyun __le16 reserved3;
122*4882a593Smuzhiyun __le16 z2;
123*4882a593Smuzhiyun __le16 z1;
124*4882a593Smuzhiyun __le16 xyz1;
125*4882a593Smuzhiyun __le16 z3;
126*4882a593Smuzhiyun s8 xy2;
127*4882a593Smuzhiyun u8 xy1;
128*4882a593Smuzhiyun } __packed;
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun struct bmc150_magn_data {
131*4882a593Smuzhiyun struct device *dev;
132*4882a593Smuzhiyun /*
133*4882a593Smuzhiyun * 1. Protect this structure.
134*4882a593Smuzhiyun * 2. Serialize sequences that power on/off the device and access HW.
135*4882a593Smuzhiyun */
136*4882a593Smuzhiyun struct mutex mutex;
137*4882a593Smuzhiyun struct regmap *regmap;
138*4882a593Smuzhiyun struct iio_mount_matrix orientation;
139*4882a593Smuzhiyun /* Ensure timestamp is naturally aligned */
140*4882a593Smuzhiyun struct {
141*4882a593Smuzhiyun s32 chans[3];
142*4882a593Smuzhiyun s64 timestamp __aligned(8);
143*4882a593Smuzhiyun } scan;
144*4882a593Smuzhiyun struct iio_trigger *dready_trig;
145*4882a593Smuzhiyun bool dready_trigger_on;
146*4882a593Smuzhiyun int max_odr;
147*4882a593Smuzhiyun int irq;
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun static const struct {
151*4882a593Smuzhiyun int freq;
152*4882a593Smuzhiyun u8 reg_val;
153*4882a593Smuzhiyun } bmc150_magn_samp_freq_table[] = { {2, 0x01},
154*4882a593Smuzhiyun {6, 0x02},
155*4882a593Smuzhiyun {8, 0x03},
156*4882a593Smuzhiyun {10, 0x00},
157*4882a593Smuzhiyun {15, 0x04},
158*4882a593Smuzhiyun {20, 0x05},
159*4882a593Smuzhiyun {25, 0x06},
160*4882a593Smuzhiyun {30, 0x07} };
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun enum bmc150_magn_presets {
163*4882a593Smuzhiyun LOW_POWER_PRESET,
164*4882a593Smuzhiyun REGULAR_PRESET,
165*4882a593Smuzhiyun ENHANCED_REGULAR_PRESET,
166*4882a593Smuzhiyun HIGH_ACCURACY_PRESET
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun static const struct bmc150_magn_preset {
170*4882a593Smuzhiyun u8 rep_xy;
171*4882a593Smuzhiyun u8 rep_z;
172*4882a593Smuzhiyun u8 odr;
173*4882a593Smuzhiyun } bmc150_magn_presets_table[] = {
174*4882a593Smuzhiyun [LOW_POWER_PRESET] = {3, 3, 10},
175*4882a593Smuzhiyun [REGULAR_PRESET] = {9, 15, 10},
176*4882a593Smuzhiyun [ENHANCED_REGULAR_PRESET] = {15, 27, 10},
177*4882a593Smuzhiyun [HIGH_ACCURACY_PRESET] = {47, 83, 20},
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun #define BMC150_MAGN_DEFAULT_PRESET REGULAR_PRESET
181*4882a593Smuzhiyun
bmc150_magn_is_writeable_reg(struct device * dev,unsigned int reg)182*4882a593Smuzhiyun static bool bmc150_magn_is_writeable_reg(struct device *dev, unsigned int reg)
183*4882a593Smuzhiyun {
184*4882a593Smuzhiyun switch (reg) {
185*4882a593Smuzhiyun case BMC150_MAGN_REG_POWER:
186*4882a593Smuzhiyun case BMC150_MAGN_REG_OPMODE_ODR:
187*4882a593Smuzhiyun case BMC150_MAGN_REG_INT:
188*4882a593Smuzhiyun case BMC150_MAGN_REG_INT_DRDY:
189*4882a593Smuzhiyun case BMC150_MAGN_REG_LOW_THRESH:
190*4882a593Smuzhiyun case BMC150_MAGN_REG_HIGH_THRESH:
191*4882a593Smuzhiyun case BMC150_MAGN_REG_REP_XY:
192*4882a593Smuzhiyun case BMC150_MAGN_REG_REP_Z:
193*4882a593Smuzhiyun return true;
194*4882a593Smuzhiyun default:
195*4882a593Smuzhiyun return false;
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
bmc150_magn_is_volatile_reg(struct device * dev,unsigned int reg)199*4882a593Smuzhiyun static bool bmc150_magn_is_volatile_reg(struct device *dev, unsigned int reg)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun switch (reg) {
202*4882a593Smuzhiyun case BMC150_MAGN_REG_X_L:
203*4882a593Smuzhiyun case BMC150_MAGN_REG_X_M:
204*4882a593Smuzhiyun case BMC150_MAGN_REG_Y_L:
205*4882a593Smuzhiyun case BMC150_MAGN_REG_Y_M:
206*4882a593Smuzhiyun case BMC150_MAGN_REG_Z_L:
207*4882a593Smuzhiyun case BMC150_MAGN_REG_Z_M:
208*4882a593Smuzhiyun case BMC150_MAGN_REG_RHALL_L:
209*4882a593Smuzhiyun case BMC150_MAGN_REG_RHALL_M:
210*4882a593Smuzhiyun case BMC150_MAGN_REG_INT_STATUS:
211*4882a593Smuzhiyun return true;
212*4882a593Smuzhiyun default:
213*4882a593Smuzhiyun return false;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun const struct regmap_config bmc150_magn_regmap_config = {
218*4882a593Smuzhiyun .reg_bits = 8,
219*4882a593Smuzhiyun .val_bits = 8,
220*4882a593Smuzhiyun
221*4882a593Smuzhiyun .max_register = BMC150_MAGN_REG_TRIM_END,
222*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun .writeable_reg = bmc150_magn_is_writeable_reg,
225*4882a593Smuzhiyun .volatile_reg = bmc150_magn_is_volatile_reg,
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun EXPORT_SYMBOL(bmc150_magn_regmap_config);
228*4882a593Smuzhiyun
bmc150_magn_set_power_mode(struct bmc150_magn_data * data,enum bmc150_magn_power_modes mode,bool state)229*4882a593Smuzhiyun static int bmc150_magn_set_power_mode(struct bmc150_magn_data *data,
230*4882a593Smuzhiyun enum bmc150_magn_power_modes mode,
231*4882a593Smuzhiyun bool state)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun int ret;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun switch (mode) {
236*4882a593Smuzhiyun case BMC150_MAGN_POWER_MODE_SUSPEND:
237*4882a593Smuzhiyun ret = regmap_update_bits(data->regmap, BMC150_MAGN_REG_POWER,
238*4882a593Smuzhiyun BMC150_MAGN_MASK_POWER_CTL, !state);
239*4882a593Smuzhiyun if (ret < 0)
240*4882a593Smuzhiyun return ret;
241*4882a593Smuzhiyun usleep_range(BMC150_MAGN_START_UP_TIME_MS * 1000, 20000);
242*4882a593Smuzhiyun return 0;
243*4882a593Smuzhiyun case BMC150_MAGN_POWER_MODE_SLEEP:
244*4882a593Smuzhiyun return regmap_update_bits(data->regmap,
245*4882a593Smuzhiyun BMC150_MAGN_REG_OPMODE_ODR,
246*4882a593Smuzhiyun BMC150_MAGN_MASK_OPMODE,
247*4882a593Smuzhiyun BMC150_MAGN_MODE_SLEEP <<
248*4882a593Smuzhiyun BMC150_MAGN_SHIFT_OPMODE);
249*4882a593Smuzhiyun case BMC150_MAGN_POWER_MODE_NORMAL:
250*4882a593Smuzhiyun return regmap_update_bits(data->regmap,
251*4882a593Smuzhiyun BMC150_MAGN_REG_OPMODE_ODR,
252*4882a593Smuzhiyun BMC150_MAGN_MASK_OPMODE,
253*4882a593Smuzhiyun BMC150_MAGN_MODE_NORMAL <<
254*4882a593Smuzhiyun BMC150_MAGN_SHIFT_OPMODE);
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun return -EINVAL;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
bmc150_magn_set_power_state(struct bmc150_magn_data * data,bool on)260*4882a593Smuzhiyun static int bmc150_magn_set_power_state(struct bmc150_magn_data *data, bool on)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun #ifdef CONFIG_PM
263*4882a593Smuzhiyun int ret;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun if (on) {
266*4882a593Smuzhiyun ret = pm_runtime_resume_and_get(data->dev);
267*4882a593Smuzhiyun } else {
268*4882a593Smuzhiyun pm_runtime_mark_last_busy(data->dev);
269*4882a593Smuzhiyun ret = pm_runtime_put_autosuspend(data->dev);
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun if (ret < 0) {
273*4882a593Smuzhiyun dev_err(data->dev,
274*4882a593Smuzhiyun "failed to change power state to %d\n", on);
275*4882a593Smuzhiyun return ret;
276*4882a593Smuzhiyun }
277*4882a593Smuzhiyun #endif
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun return 0;
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
bmc150_magn_get_odr(struct bmc150_magn_data * data,int * val)282*4882a593Smuzhiyun static int bmc150_magn_get_odr(struct bmc150_magn_data *data, int *val)
283*4882a593Smuzhiyun {
284*4882a593Smuzhiyun int ret, reg_val;
285*4882a593Smuzhiyun u8 i, odr_val;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun ret = regmap_read(data->regmap, BMC150_MAGN_REG_OPMODE_ODR, ®_val);
288*4882a593Smuzhiyun if (ret < 0)
289*4882a593Smuzhiyun return ret;
290*4882a593Smuzhiyun odr_val = (reg_val & BMC150_MAGN_MASK_ODR) >> BMC150_MAGN_SHIFT_ODR;
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(bmc150_magn_samp_freq_table); i++)
293*4882a593Smuzhiyun if (bmc150_magn_samp_freq_table[i].reg_val == odr_val) {
294*4882a593Smuzhiyun *val = bmc150_magn_samp_freq_table[i].freq;
295*4882a593Smuzhiyun return 0;
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun return -EINVAL;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
bmc150_magn_set_odr(struct bmc150_magn_data * data,int val)301*4882a593Smuzhiyun static int bmc150_magn_set_odr(struct bmc150_magn_data *data, int val)
302*4882a593Smuzhiyun {
303*4882a593Smuzhiyun int ret;
304*4882a593Smuzhiyun u8 i;
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(bmc150_magn_samp_freq_table); i++) {
307*4882a593Smuzhiyun if (bmc150_magn_samp_freq_table[i].freq == val) {
308*4882a593Smuzhiyun ret = regmap_update_bits(data->regmap,
309*4882a593Smuzhiyun BMC150_MAGN_REG_OPMODE_ODR,
310*4882a593Smuzhiyun BMC150_MAGN_MASK_ODR,
311*4882a593Smuzhiyun bmc150_magn_samp_freq_table[i].
312*4882a593Smuzhiyun reg_val <<
313*4882a593Smuzhiyun BMC150_MAGN_SHIFT_ODR);
314*4882a593Smuzhiyun if (ret < 0)
315*4882a593Smuzhiyun return ret;
316*4882a593Smuzhiyun return 0;
317*4882a593Smuzhiyun }
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun return -EINVAL;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
bmc150_magn_set_max_odr(struct bmc150_magn_data * data,int rep_xy,int rep_z,int odr)323*4882a593Smuzhiyun static int bmc150_magn_set_max_odr(struct bmc150_magn_data *data, int rep_xy,
324*4882a593Smuzhiyun int rep_z, int odr)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun int ret, reg_val, max_odr;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun if (rep_xy <= 0) {
329*4882a593Smuzhiyun ret = regmap_read(data->regmap, BMC150_MAGN_REG_REP_XY,
330*4882a593Smuzhiyun ®_val);
331*4882a593Smuzhiyun if (ret < 0)
332*4882a593Smuzhiyun return ret;
333*4882a593Smuzhiyun rep_xy = BMC150_MAGN_REGVAL_TO_REPXY(reg_val);
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun if (rep_z <= 0) {
336*4882a593Smuzhiyun ret = regmap_read(data->regmap, BMC150_MAGN_REG_REP_Z,
337*4882a593Smuzhiyun ®_val);
338*4882a593Smuzhiyun if (ret < 0)
339*4882a593Smuzhiyun return ret;
340*4882a593Smuzhiyun rep_z = BMC150_MAGN_REGVAL_TO_REPZ(reg_val);
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun if (odr <= 0) {
343*4882a593Smuzhiyun ret = bmc150_magn_get_odr(data, &odr);
344*4882a593Smuzhiyun if (ret < 0)
345*4882a593Smuzhiyun return ret;
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun /* the maximum selectable read-out frequency from datasheet */
348*4882a593Smuzhiyun max_odr = 1000000 / (145 * rep_xy + 500 * rep_z + 980);
349*4882a593Smuzhiyun if (odr > max_odr) {
350*4882a593Smuzhiyun dev_err(data->dev,
351*4882a593Smuzhiyun "Can't set oversampling with sampling freq %d\n",
352*4882a593Smuzhiyun odr);
353*4882a593Smuzhiyun return -EINVAL;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun data->max_odr = max_odr;
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun return 0;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun
bmc150_magn_compensate_x(struct bmc150_magn_trim_regs * tregs,s16 x,u16 rhall)360*4882a593Smuzhiyun static s32 bmc150_magn_compensate_x(struct bmc150_magn_trim_regs *tregs, s16 x,
361*4882a593Smuzhiyun u16 rhall)
362*4882a593Smuzhiyun {
363*4882a593Smuzhiyun s16 val;
364*4882a593Smuzhiyun u16 xyz1 = le16_to_cpu(tregs->xyz1);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun if (x == BMC150_MAGN_XY_OVERFLOW_VAL)
367*4882a593Smuzhiyun return S32_MIN;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun if (!rhall)
370*4882a593Smuzhiyun rhall = xyz1;
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun val = ((s16)(((u16)((((s32)xyz1) << 14) / rhall)) - ((u16)0x4000)));
373*4882a593Smuzhiyun val = ((s16)((((s32)x) * ((((((((s32)tregs->xy2) * ((((s32)val) *
374*4882a593Smuzhiyun ((s32)val)) >> 7)) + (((s32)val) *
375*4882a593Smuzhiyun ((s32)(((s16)tregs->xy1) << 7)))) >> 9) + ((s32)0x100000)) *
376*4882a593Smuzhiyun ((s32)(((s16)tregs->x2) + ((s16)0xA0)))) >> 12)) >> 13)) +
377*4882a593Smuzhiyun (((s16)tregs->x1) << 3);
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun return (s32)val;
380*4882a593Smuzhiyun }
381*4882a593Smuzhiyun
bmc150_magn_compensate_y(struct bmc150_magn_trim_regs * tregs,s16 y,u16 rhall)382*4882a593Smuzhiyun static s32 bmc150_magn_compensate_y(struct bmc150_magn_trim_regs *tregs, s16 y,
383*4882a593Smuzhiyun u16 rhall)
384*4882a593Smuzhiyun {
385*4882a593Smuzhiyun s16 val;
386*4882a593Smuzhiyun u16 xyz1 = le16_to_cpu(tregs->xyz1);
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun if (y == BMC150_MAGN_XY_OVERFLOW_VAL)
389*4882a593Smuzhiyun return S32_MIN;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun if (!rhall)
392*4882a593Smuzhiyun rhall = xyz1;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun val = ((s16)(((u16)((((s32)xyz1) << 14) / rhall)) - ((u16)0x4000)));
395*4882a593Smuzhiyun val = ((s16)((((s32)y) * ((((((((s32)tregs->xy2) * ((((s32)val) *
396*4882a593Smuzhiyun ((s32)val)) >> 7)) + (((s32)val) *
397*4882a593Smuzhiyun ((s32)(((s16)tregs->xy1) << 7)))) >> 9) + ((s32)0x100000)) *
398*4882a593Smuzhiyun ((s32)(((s16)tregs->y2) + ((s16)0xA0)))) >> 12)) >> 13)) +
399*4882a593Smuzhiyun (((s16)tregs->y1) << 3);
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun return (s32)val;
402*4882a593Smuzhiyun }
403*4882a593Smuzhiyun
bmc150_magn_compensate_z(struct bmc150_magn_trim_regs * tregs,s16 z,u16 rhall)404*4882a593Smuzhiyun static s32 bmc150_magn_compensate_z(struct bmc150_magn_trim_regs *tregs, s16 z,
405*4882a593Smuzhiyun u16 rhall)
406*4882a593Smuzhiyun {
407*4882a593Smuzhiyun s32 val;
408*4882a593Smuzhiyun u16 xyz1 = le16_to_cpu(tregs->xyz1);
409*4882a593Smuzhiyun u16 z1 = le16_to_cpu(tregs->z1);
410*4882a593Smuzhiyun s16 z2 = le16_to_cpu(tregs->z2);
411*4882a593Smuzhiyun s16 z3 = le16_to_cpu(tregs->z3);
412*4882a593Smuzhiyun s16 z4 = le16_to_cpu(tregs->z4);
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun if (z == BMC150_MAGN_Z_OVERFLOW_VAL)
415*4882a593Smuzhiyun return S32_MIN;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun val = (((((s32)(z - z4)) << 15) - ((((s32)z3) * ((s32)(((s16)rhall) -
418*4882a593Smuzhiyun ((s16)xyz1)))) >> 2)) / (z2 + ((s16)(((((s32)z1) *
419*4882a593Smuzhiyun ((((s16)rhall) << 1))) + (1 << 15)) >> 16))));
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun return val;
422*4882a593Smuzhiyun }
423*4882a593Smuzhiyun
bmc150_magn_read_xyz(struct bmc150_magn_data * data,s32 * buffer)424*4882a593Smuzhiyun static int bmc150_magn_read_xyz(struct bmc150_magn_data *data, s32 *buffer)
425*4882a593Smuzhiyun {
426*4882a593Smuzhiyun int ret;
427*4882a593Smuzhiyun __le16 values[AXIS_XYZR_MAX];
428*4882a593Smuzhiyun s16 raw_x, raw_y, raw_z;
429*4882a593Smuzhiyun u16 rhall;
430*4882a593Smuzhiyun struct bmc150_magn_trim_regs tregs;
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun ret = regmap_bulk_read(data->regmap, BMC150_MAGN_REG_X_L,
433*4882a593Smuzhiyun values, sizeof(values));
434*4882a593Smuzhiyun if (ret < 0)
435*4882a593Smuzhiyun return ret;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun raw_x = (s16)le16_to_cpu(values[AXIS_X]) >> BMC150_MAGN_SHIFT_XY_L;
438*4882a593Smuzhiyun raw_y = (s16)le16_to_cpu(values[AXIS_Y]) >> BMC150_MAGN_SHIFT_XY_L;
439*4882a593Smuzhiyun raw_z = (s16)le16_to_cpu(values[AXIS_Z]) >> BMC150_MAGN_SHIFT_Z_L;
440*4882a593Smuzhiyun rhall = le16_to_cpu(values[RHALL]) >> BMC150_MAGN_SHIFT_RHALL_L;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun ret = regmap_bulk_read(data->regmap, BMC150_MAGN_REG_TRIM_START,
443*4882a593Smuzhiyun &tregs, sizeof(tregs));
444*4882a593Smuzhiyun if (ret < 0)
445*4882a593Smuzhiyun return ret;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun buffer[AXIS_X] = bmc150_magn_compensate_x(&tregs, raw_x, rhall);
448*4882a593Smuzhiyun buffer[AXIS_Y] = bmc150_magn_compensate_y(&tregs, raw_y, rhall);
449*4882a593Smuzhiyun buffer[AXIS_Z] = bmc150_magn_compensate_z(&tregs, raw_z, rhall);
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun return 0;
452*4882a593Smuzhiyun }
453*4882a593Smuzhiyun
bmc150_magn_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)454*4882a593Smuzhiyun static int bmc150_magn_read_raw(struct iio_dev *indio_dev,
455*4882a593Smuzhiyun struct iio_chan_spec const *chan,
456*4882a593Smuzhiyun int *val, int *val2, long mask)
457*4882a593Smuzhiyun {
458*4882a593Smuzhiyun struct bmc150_magn_data *data = iio_priv(indio_dev);
459*4882a593Smuzhiyun int ret, tmp;
460*4882a593Smuzhiyun s32 values[AXIS_XYZ_MAX];
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun switch (mask) {
463*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
464*4882a593Smuzhiyun if (iio_buffer_enabled(indio_dev))
465*4882a593Smuzhiyun return -EBUSY;
466*4882a593Smuzhiyun mutex_lock(&data->mutex);
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun ret = bmc150_magn_set_power_state(data, true);
469*4882a593Smuzhiyun if (ret < 0) {
470*4882a593Smuzhiyun mutex_unlock(&data->mutex);
471*4882a593Smuzhiyun return ret;
472*4882a593Smuzhiyun }
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun ret = bmc150_magn_read_xyz(data, values);
475*4882a593Smuzhiyun if (ret < 0) {
476*4882a593Smuzhiyun bmc150_magn_set_power_state(data, false);
477*4882a593Smuzhiyun mutex_unlock(&data->mutex);
478*4882a593Smuzhiyun return ret;
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun *val = values[chan->scan_index];
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun ret = bmc150_magn_set_power_state(data, false);
483*4882a593Smuzhiyun if (ret < 0) {
484*4882a593Smuzhiyun mutex_unlock(&data->mutex);
485*4882a593Smuzhiyun return ret;
486*4882a593Smuzhiyun }
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun mutex_unlock(&data->mutex);
489*4882a593Smuzhiyun return IIO_VAL_INT;
490*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
491*4882a593Smuzhiyun /*
492*4882a593Smuzhiyun * The API/driver performs an off-chip temperature
493*4882a593Smuzhiyun * compensation and outputs x/y/z magnetic field data in
494*4882a593Smuzhiyun * 16 LSB/uT to the upper application layer.
495*4882a593Smuzhiyun */
496*4882a593Smuzhiyun *val = 0;
497*4882a593Smuzhiyun *val2 = 625;
498*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
499*4882a593Smuzhiyun case IIO_CHAN_INFO_SAMP_FREQ:
500*4882a593Smuzhiyun ret = bmc150_magn_get_odr(data, val);
501*4882a593Smuzhiyun if (ret < 0)
502*4882a593Smuzhiyun return ret;
503*4882a593Smuzhiyun return IIO_VAL_INT;
504*4882a593Smuzhiyun case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
505*4882a593Smuzhiyun switch (chan->channel2) {
506*4882a593Smuzhiyun case IIO_MOD_X:
507*4882a593Smuzhiyun case IIO_MOD_Y:
508*4882a593Smuzhiyun ret = regmap_read(data->regmap, BMC150_MAGN_REG_REP_XY,
509*4882a593Smuzhiyun &tmp);
510*4882a593Smuzhiyun if (ret < 0)
511*4882a593Smuzhiyun return ret;
512*4882a593Smuzhiyun *val = BMC150_MAGN_REGVAL_TO_REPXY(tmp);
513*4882a593Smuzhiyun return IIO_VAL_INT;
514*4882a593Smuzhiyun case IIO_MOD_Z:
515*4882a593Smuzhiyun ret = regmap_read(data->regmap, BMC150_MAGN_REG_REP_Z,
516*4882a593Smuzhiyun &tmp);
517*4882a593Smuzhiyun if (ret < 0)
518*4882a593Smuzhiyun return ret;
519*4882a593Smuzhiyun *val = BMC150_MAGN_REGVAL_TO_REPZ(tmp);
520*4882a593Smuzhiyun return IIO_VAL_INT;
521*4882a593Smuzhiyun default:
522*4882a593Smuzhiyun return -EINVAL;
523*4882a593Smuzhiyun }
524*4882a593Smuzhiyun default:
525*4882a593Smuzhiyun return -EINVAL;
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun
bmc150_magn_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)529*4882a593Smuzhiyun static int bmc150_magn_write_raw(struct iio_dev *indio_dev,
530*4882a593Smuzhiyun struct iio_chan_spec const *chan,
531*4882a593Smuzhiyun int val, int val2, long mask)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun struct bmc150_magn_data *data = iio_priv(indio_dev);
534*4882a593Smuzhiyun int ret;
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun switch (mask) {
537*4882a593Smuzhiyun case IIO_CHAN_INFO_SAMP_FREQ:
538*4882a593Smuzhiyun if (val > data->max_odr)
539*4882a593Smuzhiyun return -EINVAL;
540*4882a593Smuzhiyun mutex_lock(&data->mutex);
541*4882a593Smuzhiyun ret = bmc150_magn_set_odr(data, val);
542*4882a593Smuzhiyun mutex_unlock(&data->mutex);
543*4882a593Smuzhiyun return ret;
544*4882a593Smuzhiyun case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
545*4882a593Smuzhiyun switch (chan->channel2) {
546*4882a593Smuzhiyun case IIO_MOD_X:
547*4882a593Smuzhiyun case IIO_MOD_Y:
548*4882a593Smuzhiyun if (val < 1 || val > 511)
549*4882a593Smuzhiyun return -EINVAL;
550*4882a593Smuzhiyun mutex_lock(&data->mutex);
551*4882a593Smuzhiyun ret = bmc150_magn_set_max_odr(data, val, 0, 0);
552*4882a593Smuzhiyun if (ret < 0) {
553*4882a593Smuzhiyun mutex_unlock(&data->mutex);
554*4882a593Smuzhiyun return ret;
555*4882a593Smuzhiyun }
556*4882a593Smuzhiyun ret = regmap_update_bits(data->regmap,
557*4882a593Smuzhiyun BMC150_MAGN_REG_REP_XY,
558*4882a593Smuzhiyun BMC150_MAGN_REG_REP_DATAMASK,
559*4882a593Smuzhiyun BMC150_MAGN_REPXY_TO_REGVAL
560*4882a593Smuzhiyun (val));
561*4882a593Smuzhiyun mutex_unlock(&data->mutex);
562*4882a593Smuzhiyun return ret;
563*4882a593Smuzhiyun case IIO_MOD_Z:
564*4882a593Smuzhiyun if (val < 1 || val > 256)
565*4882a593Smuzhiyun return -EINVAL;
566*4882a593Smuzhiyun mutex_lock(&data->mutex);
567*4882a593Smuzhiyun ret = bmc150_magn_set_max_odr(data, 0, val, 0);
568*4882a593Smuzhiyun if (ret < 0) {
569*4882a593Smuzhiyun mutex_unlock(&data->mutex);
570*4882a593Smuzhiyun return ret;
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun ret = regmap_update_bits(data->regmap,
573*4882a593Smuzhiyun BMC150_MAGN_REG_REP_Z,
574*4882a593Smuzhiyun BMC150_MAGN_REG_REP_DATAMASK,
575*4882a593Smuzhiyun BMC150_MAGN_REPZ_TO_REGVAL
576*4882a593Smuzhiyun (val));
577*4882a593Smuzhiyun mutex_unlock(&data->mutex);
578*4882a593Smuzhiyun return ret;
579*4882a593Smuzhiyun default:
580*4882a593Smuzhiyun return -EINVAL;
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun default:
583*4882a593Smuzhiyun return -EINVAL;
584*4882a593Smuzhiyun }
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun
bmc150_magn_show_samp_freq_avail(struct device * dev,struct device_attribute * attr,char * buf)587*4882a593Smuzhiyun static ssize_t bmc150_magn_show_samp_freq_avail(struct device *dev,
588*4882a593Smuzhiyun struct device_attribute *attr,
589*4882a593Smuzhiyun char *buf)
590*4882a593Smuzhiyun {
591*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_to_iio_dev(dev);
592*4882a593Smuzhiyun struct bmc150_magn_data *data = iio_priv(indio_dev);
593*4882a593Smuzhiyun size_t len = 0;
594*4882a593Smuzhiyun u8 i;
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(bmc150_magn_samp_freq_table); i++) {
597*4882a593Smuzhiyun if (bmc150_magn_samp_freq_table[i].freq > data->max_odr)
598*4882a593Smuzhiyun break;
599*4882a593Smuzhiyun len += scnprintf(buf + len, PAGE_SIZE - len, "%d ",
600*4882a593Smuzhiyun bmc150_magn_samp_freq_table[i].freq);
601*4882a593Smuzhiyun }
602*4882a593Smuzhiyun /* replace last space with a newline */
603*4882a593Smuzhiyun buf[len - 1] = '\n';
604*4882a593Smuzhiyun
605*4882a593Smuzhiyun return len;
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun
608*4882a593Smuzhiyun static const struct iio_mount_matrix *
bmc150_magn_get_mount_matrix(const struct iio_dev * indio_dev,const struct iio_chan_spec * chan)609*4882a593Smuzhiyun bmc150_magn_get_mount_matrix(const struct iio_dev *indio_dev,
610*4882a593Smuzhiyun const struct iio_chan_spec *chan)
611*4882a593Smuzhiyun {
612*4882a593Smuzhiyun struct bmc150_magn_data *data = iio_priv(indio_dev);
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun return &data->orientation;
615*4882a593Smuzhiyun }
616*4882a593Smuzhiyun
617*4882a593Smuzhiyun static const struct iio_chan_spec_ext_info bmc150_magn_ext_info[] = {
618*4882a593Smuzhiyun IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmc150_magn_get_mount_matrix),
619*4882a593Smuzhiyun { }
620*4882a593Smuzhiyun };
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(bmc150_magn_show_samp_freq_avail);
623*4882a593Smuzhiyun
624*4882a593Smuzhiyun static struct attribute *bmc150_magn_attributes[] = {
625*4882a593Smuzhiyun &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
626*4882a593Smuzhiyun NULL,
627*4882a593Smuzhiyun };
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun static const struct attribute_group bmc150_magn_attrs_group = {
630*4882a593Smuzhiyun .attrs = bmc150_magn_attributes,
631*4882a593Smuzhiyun };
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun #define BMC150_MAGN_CHANNEL(_axis) { \
634*4882a593Smuzhiyun .type = IIO_MAGN, \
635*4882a593Smuzhiyun .modified = 1, \
636*4882a593Smuzhiyun .channel2 = IIO_MOD_##_axis, \
637*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
638*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
639*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
640*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE), \
641*4882a593Smuzhiyun .scan_index = AXIS_##_axis, \
642*4882a593Smuzhiyun .scan_type = { \
643*4882a593Smuzhiyun .sign = 's', \
644*4882a593Smuzhiyun .realbits = 32, \
645*4882a593Smuzhiyun .storagebits = 32, \
646*4882a593Smuzhiyun .endianness = IIO_LE \
647*4882a593Smuzhiyun }, \
648*4882a593Smuzhiyun .ext_info = bmc150_magn_ext_info, \
649*4882a593Smuzhiyun }
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun static const struct iio_chan_spec bmc150_magn_channels[] = {
652*4882a593Smuzhiyun BMC150_MAGN_CHANNEL(X),
653*4882a593Smuzhiyun BMC150_MAGN_CHANNEL(Y),
654*4882a593Smuzhiyun BMC150_MAGN_CHANNEL(Z),
655*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(3),
656*4882a593Smuzhiyun };
657*4882a593Smuzhiyun
658*4882a593Smuzhiyun static const struct iio_info bmc150_magn_info = {
659*4882a593Smuzhiyun .attrs = &bmc150_magn_attrs_group,
660*4882a593Smuzhiyun .read_raw = bmc150_magn_read_raw,
661*4882a593Smuzhiyun .write_raw = bmc150_magn_write_raw,
662*4882a593Smuzhiyun };
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun static const unsigned long bmc150_magn_scan_masks[] = {
665*4882a593Smuzhiyun BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
666*4882a593Smuzhiyun 0};
667*4882a593Smuzhiyun
bmc150_magn_trigger_handler(int irq,void * p)668*4882a593Smuzhiyun static irqreturn_t bmc150_magn_trigger_handler(int irq, void *p)
669*4882a593Smuzhiyun {
670*4882a593Smuzhiyun struct iio_poll_func *pf = p;
671*4882a593Smuzhiyun struct iio_dev *indio_dev = pf->indio_dev;
672*4882a593Smuzhiyun struct bmc150_magn_data *data = iio_priv(indio_dev);
673*4882a593Smuzhiyun int ret;
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun mutex_lock(&data->mutex);
676*4882a593Smuzhiyun ret = bmc150_magn_read_xyz(data, data->scan.chans);
677*4882a593Smuzhiyun if (ret < 0)
678*4882a593Smuzhiyun goto err;
679*4882a593Smuzhiyun
680*4882a593Smuzhiyun iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
681*4882a593Smuzhiyun pf->timestamp);
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun err:
684*4882a593Smuzhiyun mutex_unlock(&data->mutex);
685*4882a593Smuzhiyun iio_trigger_notify_done(indio_dev->trig);
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun return IRQ_HANDLED;
688*4882a593Smuzhiyun }
689*4882a593Smuzhiyun
bmc150_magn_init(struct bmc150_magn_data * data)690*4882a593Smuzhiyun static int bmc150_magn_init(struct bmc150_magn_data *data)
691*4882a593Smuzhiyun {
692*4882a593Smuzhiyun int ret, chip_id;
693*4882a593Smuzhiyun struct bmc150_magn_preset preset;
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SUSPEND,
696*4882a593Smuzhiyun false);
697*4882a593Smuzhiyun if (ret < 0) {
698*4882a593Smuzhiyun dev_err(data->dev,
699*4882a593Smuzhiyun "Failed to bring up device from suspend mode\n");
700*4882a593Smuzhiyun return ret;
701*4882a593Smuzhiyun }
702*4882a593Smuzhiyun
703*4882a593Smuzhiyun ret = regmap_read(data->regmap, BMC150_MAGN_REG_CHIP_ID, &chip_id);
704*4882a593Smuzhiyun if (ret < 0) {
705*4882a593Smuzhiyun dev_err(data->dev, "Failed reading chip id\n");
706*4882a593Smuzhiyun goto err_poweroff;
707*4882a593Smuzhiyun }
708*4882a593Smuzhiyun if (chip_id != BMC150_MAGN_CHIP_ID_VAL) {
709*4882a593Smuzhiyun dev_err(data->dev, "Invalid chip id 0x%x\n", chip_id);
710*4882a593Smuzhiyun ret = -ENODEV;
711*4882a593Smuzhiyun goto err_poweroff;
712*4882a593Smuzhiyun }
713*4882a593Smuzhiyun dev_dbg(data->dev, "Chip id %x\n", chip_id);
714*4882a593Smuzhiyun
715*4882a593Smuzhiyun preset = bmc150_magn_presets_table[BMC150_MAGN_DEFAULT_PRESET];
716*4882a593Smuzhiyun ret = bmc150_magn_set_odr(data, preset.odr);
717*4882a593Smuzhiyun if (ret < 0) {
718*4882a593Smuzhiyun dev_err(data->dev, "Failed to set ODR to %d\n",
719*4882a593Smuzhiyun preset.odr);
720*4882a593Smuzhiyun goto err_poweroff;
721*4882a593Smuzhiyun }
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun ret = regmap_write(data->regmap, BMC150_MAGN_REG_REP_XY,
724*4882a593Smuzhiyun BMC150_MAGN_REPXY_TO_REGVAL(preset.rep_xy));
725*4882a593Smuzhiyun if (ret < 0) {
726*4882a593Smuzhiyun dev_err(data->dev, "Failed to set REP XY to %d\n",
727*4882a593Smuzhiyun preset.rep_xy);
728*4882a593Smuzhiyun goto err_poweroff;
729*4882a593Smuzhiyun }
730*4882a593Smuzhiyun
731*4882a593Smuzhiyun ret = regmap_write(data->regmap, BMC150_MAGN_REG_REP_Z,
732*4882a593Smuzhiyun BMC150_MAGN_REPZ_TO_REGVAL(preset.rep_z));
733*4882a593Smuzhiyun if (ret < 0) {
734*4882a593Smuzhiyun dev_err(data->dev, "Failed to set REP Z to %d\n",
735*4882a593Smuzhiyun preset.rep_z);
736*4882a593Smuzhiyun goto err_poweroff;
737*4882a593Smuzhiyun }
738*4882a593Smuzhiyun
739*4882a593Smuzhiyun ret = bmc150_magn_set_max_odr(data, preset.rep_xy, preset.rep_z,
740*4882a593Smuzhiyun preset.odr);
741*4882a593Smuzhiyun if (ret < 0)
742*4882a593Smuzhiyun goto err_poweroff;
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_NORMAL,
745*4882a593Smuzhiyun true);
746*4882a593Smuzhiyun if (ret < 0) {
747*4882a593Smuzhiyun dev_err(data->dev, "Failed to power on device\n");
748*4882a593Smuzhiyun goto err_poweroff;
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun return 0;
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun err_poweroff:
754*4882a593Smuzhiyun bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SUSPEND, true);
755*4882a593Smuzhiyun return ret;
756*4882a593Smuzhiyun }
757*4882a593Smuzhiyun
bmc150_magn_reset_intr(struct bmc150_magn_data * data)758*4882a593Smuzhiyun static int bmc150_magn_reset_intr(struct bmc150_magn_data *data)
759*4882a593Smuzhiyun {
760*4882a593Smuzhiyun int tmp;
761*4882a593Smuzhiyun
762*4882a593Smuzhiyun /*
763*4882a593Smuzhiyun * Data Ready (DRDY) is always cleared after
764*4882a593Smuzhiyun * readout of data registers ends.
765*4882a593Smuzhiyun */
766*4882a593Smuzhiyun return regmap_read(data->regmap, BMC150_MAGN_REG_X_L, &tmp);
767*4882a593Smuzhiyun }
768*4882a593Smuzhiyun
bmc150_magn_trig_try_reen(struct iio_trigger * trig)769*4882a593Smuzhiyun static int bmc150_magn_trig_try_reen(struct iio_trigger *trig)
770*4882a593Smuzhiyun {
771*4882a593Smuzhiyun struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
772*4882a593Smuzhiyun struct bmc150_magn_data *data = iio_priv(indio_dev);
773*4882a593Smuzhiyun int ret;
774*4882a593Smuzhiyun
775*4882a593Smuzhiyun if (!data->dready_trigger_on)
776*4882a593Smuzhiyun return 0;
777*4882a593Smuzhiyun
778*4882a593Smuzhiyun mutex_lock(&data->mutex);
779*4882a593Smuzhiyun ret = bmc150_magn_reset_intr(data);
780*4882a593Smuzhiyun mutex_unlock(&data->mutex);
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun return ret;
783*4882a593Smuzhiyun }
784*4882a593Smuzhiyun
bmc150_magn_data_rdy_trigger_set_state(struct iio_trigger * trig,bool state)785*4882a593Smuzhiyun static int bmc150_magn_data_rdy_trigger_set_state(struct iio_trigger *trig,
786*4882a593Smuzhiyun bool state)
787*4882a593Smuzhiyun {
788*4882a593Smuzhiyun struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
789*4882a593Smuzhiyun struct bmc150_magn_data *data = iio_priv(indio_dev);
790*4882a593Smuzhiyun int ret = 0;
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun mutex_lock(&data->mutex);
793*4882a593Smuzhiyun if (state == data->dready_trigger_on)
794*4882a593Smuzhiyun goto err_unlock;
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun ret = regmap_update_bits(data->regmap, BMC150_MAGN_REG_INT_DRDY,
797*4882a593Smuzhiyun BMC150_MAGN_MASK_DRDY_EN,
798*4882a593Smuzhiyun state << BMC150_MAGN_SHIFT_DRDY_EN);
799*4882a593Smuzhiyun if (ret < 0)
800*4882a593Smuzhiyun goto err_unlock;
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun data->dready_trigger_on = state;
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun if (state) {
805*4882a593Smuzhiyun ret = bmc150_magn_reset_intr(data);
806*4882a593Smuzhiyun if (ret < 0)
807*4882a593Smuzhiyun goto err_unlock;
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun mutex_unlock(&data->mutex);
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun return 0;
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun err_unlock:
814*4882a593Smuzhiyun mutex_unlock(&data->mutex);
815*4882a593Smuzhiyun return ret;
816*4882a593Smuzhiyun }
817*4882a593Smuzhiyun
818*4882a593Smuzhiyun static const struct iio_trigger_ops bmc150_magn_trigger_ops = {
819*4882a593Smuzhiyun .set_trigger_state = bmc150_magn_data_rdy_trigger_set_state,
820*4882a593Smuzhiyun .try_reenable = bmc150_magn_trig_try_reen,
821*4882a593Smuzhiyun };
822*4882a593Smuzhiyun
bmc150_magn_buffer_preenable(struct iio_dev * indio_dev)823*4882a593Smuzhiyun static int bmc150_magn_buffer_preenable(struct iio_dev *indio_dev)
824*4882a593Smuzhiyun {
825*4882a593Smuzhiyun struct bmc150_magn_data *data = iio_priv(indio_dev);
826*4882a593Smuzhiyun
827*4882a593Smuzhiyun return bmc150_magn_set_power_state(data, true);
828*4882a593Smuzhiyun }
829*4882a593Smuzhiyun
bmc150_magn_buffer_postdisable(struct iio_dev * indio_dev)830*4882a593Smuzhiyun static int bmc150_magn_buffer_postdisable(struct iio_dev *indio_dev)
831*4882a593Smuzhiyun {
832*4882a593Smuzhiyun struct bmc150_magn_data *data = iio_priv(indio_dev);
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun return bmc150_magn_set_power_state(data, false);
835*4882a593Smuzhiyun }
836*4882a593Smuzhiyun
837*4882a593Smuzhiyun static const struct iio_buffer_setup_ops bmc150_magn_buffer_setup_ops = {
838*4882a593Smuzhiyun .preenable = bmc150_magn_buffer_preenable,
839*4882a593Smuzhiyun .postdisable = bmc150_magn_buffer_postdisable,
840*4882a593Smuzhiyun };
841*4882a593Smuzhiyun
bmc150_magn_match_acpi_device(struct device * dev)842*4882a593Smuzhiyun static const char *bmc150_magn_match_acpi_device(struct device *dev)
843*4882a593Smuzhiyun {
844*4882a593Smuzhiyun const struct acpi_device_id *id;
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun id = acpi_match_device(dev->driver->acpi_match_table, dev);
847*4882a593Smuzhiyun if (!id)
848*4882a593Smuzhiyun return NULL;
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun return dev_name(dev);
851*4882a593Smuzhiyun }
852*4882a593Smuzhiyun
bmc150_magn_probe(struct device * dev,struct regmap * regmap,int irq,const char * name)853*4882a593Smuzhiyun int bmc150_magn_probe(struct device *dev, struct regmap *regmap,
854*4882a593Smuzhiyun int irq, const char *name)
855*4882a593Smuzhiyun {
856*4882a593Smuzhiyun struct bmc150_magn_data *data;
857*4882a593Smuzhiyun struct iio_dev *indio_dev;
858*4882a593Smuzhiyun int ret;
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
861*4882a593Smuzhiyun if (!indio_dev)
862*4882a593Smuzhiyun return -ENOMEM;
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun data = iio_priv(indio_dev);
865*4882a593Smuzhiyun dev_set_drvdata(dev, indio_dev);
866*4882a593Smuzhiyun data->regmap = regmap;
867*4882a593Smuzhiyun data->irq = irq;
868*4882a593Smuzhiyun data->dev = dev;
869*4882a593Smuzhiyun
870*4882a593Smuzhiyun ret = iio_read_mount_matrix(dev, "mount-matrix",
871*4882a593Smuzhiyun &data->orientation);
872*4882a593Smuzhiyun if (ret)
873*4882a593Smuzhiyun return ret;
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun if (!name && ACPI_HANDLE(dev))
876*4882a593Smuzhiyun name = bmc150_magn_match_acpi_device(dev);
877*4882a593Smuzhiyun
878*4882a593Smuzhiyun mutex_init(&data->mutex);
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun ret = bmc150_magn_init(data);
881*4882a593Smuzhiyun if (ret < 0)
882*4882a593Smuzhiyun return ret;
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun indio_dev->channels = bmc150_magn_channels;
885*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(bmc150_magn_channels);
886*4882a593Smuzhiyun indio_dev->available_scan_masks = bmc150_magn_scan_masks;
887*4882a593Smuzhiyun indio_dev->name = name;
888*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
889*4882a593Smuzhiyun indio_dev->info = &bmc150_magn_info;
890*4882a593Smuzhiyun
891*4882a593Smuzhiyun if (irq > 0) {
892*4882a593Smuzhiyun data->dready_trig = devm_iio_trigger_alloc(dev,
893*4882a593Smuzhiyun "%s-dev%d",
894*4882a593Smuzhiyun indio_dev->name,
895*4882a593Smuzhiyun indio_dev->id);
896*4882a593Smuzhiyun if (!data->dready_trig) {
897*4882a593Smuzhiyun ret = -ENOMEM;
898*4882a593Smuzhiyun dev_err(dev, "iio trigger alloc failed\n");
899*4882a593Smuzhiyun goto err_poweroff;
900*4882a593Smuzhiyun }
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun data->dready_trig->dev.parent = dev;
903*4882a593Smuzhiyun data->dready_trig->ops = &bmc150_magn_trigger_ops;
904*4882a593Smuzhiyun iio_trigger_set_drvdata(data->dready_trig, indio_dev);
905*4882a593Smuzhiyun ret = iio_trigger_register(data->dready_trig);
906*4882a593Smuzhiyun if (ret) {
907*4882a593Smuzhiyun dev_err(dev, "iio trigger register failed\n");
908*4882a593Smuzhiyun goto err_poweroff;
909*4882a593Smuzhiyun }
910*4882a593Smuzhiyun
911*4882a593Smuzhiyun ret = request_threaded_irq(irq,
912*4882a593Smuzhiyun iio_trigger_generic_data_rdy_poll,
913*4882a593Smuzhiyun NULL,
914*4882a593Smuzhiyun IRQF_TRIGGER_RISING | IRQF_ONESHOT,
915*4882a593Smuzhiyun BMC150_MAGN_IRQ_NAME,
916*4882a593Smuzhiyun data->dready_trig);
917*4882a593Smuzhiyun if (ret < 0) {
918*4882a593Smuzhiyun dev_err(dev, "request irq %d failed\n", irq);
919*4882a593Smuzhiyun goto err_trigger_unregister;
920*4882a593Smuzhiyun }
921*4882a593Smuzhiyun }
922*4882a593Smuzhiyun
923*4882a593Smuzhiyun ret = iio_triggered_buffer_setup(indio_dev,
924*4882a593Smuzhiyun iio_pollfunc_store_time,
925*4882a593Smuzhiyun bmc150_magn_trigger_handler,
926*4882a593Smuzhiyun &bmc150_magn_buffer_setup_ops);
927*4882a593Smuzhiyun if (ret < 0) {
928*4882a593Smuzhiyun dev_err(dev, "iio triggered buffer setup failed\n");
929*4882a593Smuzhiyun goto err_free_irq;
930*4882a593Smuzhiyun }
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun ret = pm_runtime_set_active(dev);
933*4882a593Smuzhiyun if (ret)
934*4882a593Smuzhiyun goto err_buffer_cleanup;
935*4882a593Smuzhiyun
936*4882a593Smuzhiyun pm_runtime_enable(dev);
937*4882a593Smuzhiyun pm_runtime_set_autosuspend_delay(dev,
938*4882a593Smuzhiyun BMC150_MAGN_AUTO_SUSPEND_DELAY_MS);
939*4882a593Smuzhiyun pm_runtime_use_autosuspend(dev);
940*4882a593Smuzhiyun
941*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
942*4882a593Smuzhiyun if (ret < 0) {
943*4882a593Smuzhiyun dev_err(dev, "unable to register iio device\n");
944*4882a593Smuzhiyun goto err_pm_cleanup;
945*4882a593Smuzhiyun }
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun dev_dbg(dev, "Registered device %s\n", name);
948*4882a593Smuzhiyun return 0;
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun err_pm_cleanup:
951*4882a593Smuzhiyun pm_runtime_dont_use_autosuspend(dev);
952*4882a593Smuzhiyun pm_runtime_disable(dev);
953*4882a593Smuzhiyun err_buffer_cleanup:
954*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
955*4882a593Smuzhiyun err_free_irq:
956*4882a593Smuzhiyun if (irq > 0)
957*4882a593Smuzhiyun free_irq(irq, data->dready_trig);
958*4882a593Smuzhiyun err_trigger_unregister:
959*4882a593Smuzhiyun if (data->dready_trig)
960*4882a593Smuzhiyun iio_trigger_unregister(data->dready_trig);
961*4882a593Smuzhiyun err_poweroff:
962*4882a593Smuzhiyun bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SUSPEND, true);
963*4882a593Smuzhiyun return ret;
964*4882a593Smuzhiyun }
965*4882a593Smuzhiyun EXPORT_SYMBOL(bmc150_magn_probe);
966*4882a593Smuzhiyun
bmc150_magn_remove(struct device * dev)967*4882a593Smuzhiyun int bmc150_magn_remove(struct device *dev)
968*4882a593Smuzhiyun {
969*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_get_drvdata(dev);
970*4882a593Smuzhiyun struct bmc150_magn_data *data = iio_priv(indio_dev);
971*4882a593Smuzhiyun
972*4882a593Smuzhiyun iio_device_unregister(indio_dev);
973*4882a593Smuzhiyun
974*4882a593Smuzhiyun pm_runtime_disable(dev);
975*4882a593Smuzhiyun pm_runtime_set_suspended(dev);
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun iio_triggered_buffer_cleanup(indio_dev);
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun if (data->irq > 0)
980*4882a593Smuzhiyun free_irq(data->irq, data->dready_trig);
981*4882a593Smuzhiyun
982*4882a593Smuzhiyun if (data->dready_trig)
983*4882a593Smuzhiyun iio_trigger_unregister(data->dready_trig);
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun mutex_lock(&data->mutex);
986*4882a593Smuzhiyun bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SUSPEND, true);
987*4882a593Smuzhiyun mutex_unlock(&data->mutex);
988*4882a593Smuzhiyun
989*4882a593Smuzhiyun return 0;
990*4882a593Smuzhiyun }
991*4882a593Smuzhiyun EXPORT_SYMBOL(bmc150_magn_remove);
992*4882a593Smuzhiyun
993*4882a593Smuzhiyun #ifdef CONFIG_PM
bmc150_magn_runtime_suspend(struct device * dev)994*4882a593Smuzhiyun static int bmc150_magn_runtime_suspend(struct device *dev)
995*4882a593Smuzhiyun {
996*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_get_drvdata(dev);
997*4882a593Smuzhiyun struct bmc150_magn_data *data = iio_priv(indio_dev);
998*4882a593Smuzhiyun int ret;
999*4882a593Smuzhiyun
1000*4882a593Smuzhiyun mutex_lock(&data->mutex);
1001*4882a593Smuzhiyun ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SLEEP,
1002*4882a593Smuzhiyun true);
1003*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1004*4882a593Smuzhiyun if (ret < 0) {
1005*4882a593Smuzhiyun dev_err(dev, "powering off device failed\n");
1006*4882a593Smuzhiyun return ret;
1007*4882a593Smuzhiyun }
1008*4882a593Smuzhiyun return 0;
1009*4882a593Smuzhiyun }
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun /*
1012*4882a593Smuzhiyun * Should be called with data->mutex held.
1013*4882a593Smuzhiyun */
bmc150_magn_runtime_resume(struct device * dev)1014*4882a593Smuzhiyun static int bmc150_magn_runtime_resume(struct device *dev)
1015*4882a593Smuzhiyun {
1016*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_get_drvdata(dev);
1017*4882a593Smuzhiyun struct bmc150_magn_data *data = iio_priv(indio_dev);
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun return bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_NORMAL,
1020*4882a593Smuzhiyun true);
1021*4882a593Smuzhiyun }
1022*4882a593Smuzhiyun #endif
1023*4882a593Smuzhiyun
1024*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
bmc150_magn_suspend(struct device * dev)1025*4882a593Smuzhiyun static int bmc150_magn_suspend(struct device *dev)
1026*4882a593Smuzhiyun {
1027*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_get_drvdata(dev);
1028*4882a593Smuzhiyun struct bmc150_magn_data *data = iio_priv(indio_dev);
1029*4882a593Smuzhiyun int ret;
1030*4882a593Smuzhiyun
1031*4882a593Smuzhiyun mutex_lock(&data->mutex);
1032*4882a593Smuzhiyun ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_SLEEP,
1033*4882a593Smuzhiyun true);
1034*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1035*4882a593Smuzhiyun
1036*4882a593Smuzhiyun return ret;
1037*4882a593Smuzhiyun }
1038*4882a593Smuzhiyun
bmc150_magn_resume(struct device * dev)1039*4882a593Smuzhiyun static int bmc150_magn_resume(struct device *dev)
1040*4882a593Smuzhiyun {
1041*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_get_drvdata(dev);
1042*4882a593Smuzhiyun struct bmc150_magn_data *data = iio_priv(indio_dev);
1043*4882a593Smuzhiyun int ret;
1044*4882a593Smuzhiyun
1045*4882a593Smuzhiyun mutex_lock(&data->mutex);
1046*4882a593Smuzhiyun ret = bmc150_magn_set_power_mode(data, BMC150_MAGN_POWER_MODE_NORMAL,
1047*4882a593Smuzhiyun true);
1048*4882a593Smuzhiyun mutex_unlock(&data->mutex);
1049*4882a593Smuzhiyun
1050*4882a593Smuzhiyun return ret;
1051*4882a593Smuzhiyun }
1052*4882a593Smuzhiyun #endif
1053*4882a593Smuzhiyun
1054*4882a593Smuzhiyun const struct dev_pm_ops bmc150_magn_pm_ops = {
1055*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(bmc150_magn_suspend, bmc150_magn_resume)
1056*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(bmc150_magn_runtime_suspend,
1057*4882a593Smuzhiyun bmc150_magn_runtime_resume, NULL)
1058*4882a593Smuzhiyun };
1059*4882a593Smuzhiyun EXPORT_SYMBOL(bmc150_magn_pm_ops);
1060*4882a593Smuzhiyun
1061*4882a593Smuzhiyun MODULE_AUTHOR("Irina Tirdea <irina.tirdea@intel.com>");
1062*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1063*4882a593Smuzhiyun MODULE_DESCRIPTION("BMC150 magnetometer core driver");
1064