1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Device driver for monitoring ambient light intensity in (lux) and proximity
4*4882a593Smuzhiyun * detection (prox) within the TAOS TSL2571, TSL2671, TMD2671, TSL2771, TMD2771,
5*4882a593Smuzhiyun * TSL2572, TSL2672, TMD2672, TSL2772, and TMD2772 devices.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (c) 2012, TAOS Corporation.
8*4882a593Smuzhiyun * Copyright (c) 2017-2018 Brian Masney <masneyb@onstation.org>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/delay.h>
12*4882a593Smuzhiyun #include <linux/errno.h>
13*4882a593Smuzhiyun #include <linux/i2c.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun #include <linux/kernel.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/mutex.h>
18*4882a593Smuzhiyun #include <linux/slab.h>
19*4882a593Smuzhiyun #include <linux/iio/events.h>
20*4882a593Smuzhiyun #include <linux/iio/iio.h>
21*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
22*4882a593Smuzhiyun #include <linux/platform_data/tsl2772.h>
23*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Cal defs */
26*4882a593Smuzhiyun #define PROX_STAT_CAL 0
27*4882a593Smuzhiyun #define PROX_STAT_SAMP 1
28*4882a593Smuzhiyun #define MAX_SAMPLES_CAL 200
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun /* TSL2772 Device ID */
31*4882a593Smuzhiyun #define TRITON_ID 0x00
32*4882a593Smuzhiyun #define SWORDFISH_ID 0x30
33*4882a593Smuzhiyun #define HALIBUT_ID 0x20
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Lux calculation constants */
36*4882a593Smuzhiyun #define TSL2772_LUX_CALC_OVER_FLOW 65535
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /*
39*4882a593Smuzhiyun * TAOS Register definitions - Note: depending on device, some of these register
40*4882a593Smuzhiyun * are not used and the register address is benign.
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* Register offsets */
44*4882a593Smuzhiyun #define TSL2772_MAX_CONFIG_REG 16
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Device Registers and Masks */
47*4882a593Smuzhiyun #define TSL2772_CNTRL 0x00
48*4882a593Smuzhiyun #define TSL2772_ALS_TIME 0X01
49*4882a593Smuzhiyun #define TSL2772_PRX_TIME 0x02
50*4882a593Smuzhiyun #define TSL2772_WAIT_TIME 0x03
51*4882a593Smuzhiyun #define TSL2772_ALS_MINTHRESHLO 0X04
52*4882a593Smuzhiyun #define TSL2772_ALS_MINTHRESHHI 0X05
53*4882a593Smuzhiyun #define TSL2772_ALS_MAXTHRESHLO 0X06
54*4882a593Smuzhiyun #define TSL2772_ALS_MAXTHRESHHI 0X07
55*4882a593Smuzhiyun #define TSL2772_PRX_MINTHRESHLO 0X08
56*4882a593Smuzhiyun #define TSL2772_PRX_MINTHRESHHI 0X09
57*4882a593Smuzhiyun #define TSL2772_PRX_MAXTHRESHLO 0X0A
58*4882a593Smuzhiyun #define TSL2772_PRX_MAXTHRESHHI 0X0B
59*4882a593Smuzhiyun #define TSL2772_PERSISTENCE 0x0C
60*4882a593Smuzhiyun #define TSL2772_ALS_PRX_CONFIG 0x0D
61*4882a593Smuzhiyun #define TSL2772_PRX_COUNT 0x0E
62*4882a593Smuzhiyun #define TSL2772_GAIN 0x0F
63*4882a593Smuzhiyun #define TSL2772_NOTUSED 0x10
64*4882a593Smuzhiyun #define TSL2772_REVID 0x11
65*4882a593Smuzhiyun #define TSL2772_CHIPID 0x12
66*4882a593Smuzhiyun #define TSL2772_STATUS 0x13
67*4882a593Smuzhiyun #define TSL2772_ALS_CHAN0LO 0x14
68*4882a593Smuzhiyun #define TSL2772_ALS_CHAN0HI 0x15
69*4882a593Smuzhiyun #define TSL2772_ALS_CHAN1LO 0x16
70*4882a593Smuzhiyun #define TSL2772_ALS_CHAN1HI 0x17
71*4882a593Smuzhiyun #define TSL2772_PRX_LO 0x18
72*4882a593Smuzhiyun #define TSL2772_PRX_HI 0x19
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* tsl2772 cmd reg masks */
75*4882a593Smuzhiyun #define TSL2772_CMD_REG 0x80
76*4882a593Smuzhiyun #define TSL2772_CMD_SPL_FN 0x60
77*4882a593Smuzhiyun #define TSL2772_CMD_REPEAT_PROTO 0x00
78*4882a593Smuzhiyun #define TSL2772_CMD_AUTOINC_PROTO 0x20
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun #define TSL2772_CMD_PROX_INT_CLR 0X05
81*4882a593Smuzhiyun #define TSL2772_CMD_ALS_INT_CLR 0x06
82*4882a593Smuzhiyun #define TSL2772_CMD_PROXALS_INT_CLR 0X07
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* tsl2772 cntrl reg masks */
85*4882a593Smuzhiyun #define TSL2772_CNTL_ADC_ENBL 0x02
86*4882a593Smuzhiyun #define TSL2772_CNTL_PWR_ON 0x01
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* tsl2772 status reg masks */
89*4882a593Smuzhiyun #define TSL2772_STA_ADC_VALID 0x01
90*4882a593Smuzhiyun #define TSL2772_STA_PRX_VALID 0x02
91*4882a593Smuzhiyun #define TSL2772_STA_ADC_PRX_VALID (TSL2772_STA_ADC_VALID | \
92*4882a593Smuzhiyun TSL2772_STA_PRX_VALID)
93*4882a593Smuzhiyun #define TSL2772_STA_ALS_INTR 0x10
94*4882a593Smuzhiyun #define TSL2772_STA_PRX_INTR 0x20
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* tsl2772 cntrl reg masks */
97*4882a593Smuzhiyun #define TSL2772_CNTL_REG_CLEAR 0x00
98*4882a593Smuzhiyun #define TSL2772_CNTL_PROX_INT_ENBL 0X20
99*4882a593Smuzhiyun #define TSL2772_CNTL_ALS_INT_ENBL 0X10
100*4882a593Smuzhiyun #define TSL2772_CNTL_WAIT_TMR_ENBL 0X08
101*4882a593Smuzhiyun #define TSL2772_CNTL_PROX_DET_ENBL 0X04
102*4882a593Smuzhiyun #define TSL2772_CNTL_PWRON 0x01
103*4882a593Smuzhiyun #define TSL2772_CNTL_ALSPON_ENBL 0x03
104*4882a593Smuzhiyun #define TSL2772_CNTL_INTALSPON_ENBL 0x13
105*4882a593Smuzhiyun #define TSL2772_CNTL_PROXPON_ENBL 0x0F
106*4882a593Smuzhiyun #define TSL2772_CNTL_INTPROXPON_ENBL 0x2F
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun #define TSL2772_ALS_GAIN_TRIM_MIN 250
109*4882a593Smuzhiyun #define TSL2772_ALS_GAIN_TRIM_MAX 4000
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun #define TSL2772_MAX_PROX_LEDS 2
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun #define TSL2772_BOOT_MIN_SLEEP_TIME 10000
114*4882a593Smuzhiyun #define TSL2772_BOOT_MAX_SLEEP_TIME 28000
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /* Device family members */
117*4882a593Smuzhiyun enum {
118*4882a593Smuzhiyun tsl2571,
119*4882a593Smuzhiyun tsl2671,
120*4882a593Smuzhiyun tmd2671,
121*4882a593Smuzhiyun tsl2771,
122*4882a593Smuzhiyun tmd2771,
123*4882a593Smuzhiyun tsl2572,
124*4882a593Smuzhiyun tsl2672,
125*4882a593Smuzhiyun tmd2672,
126*4882a593Smuzhiyun tsl2772,
127*4882a593Smuzhiyun tmd2772,
128*4882a593Smuzhiyun apds9930,
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun enum {
132*4882a593Smuzhiyun TSL2772_CHIP_UNKNOWN = 0,
133*4882a593Smuzhiyun TSL2772_CHIP_WORKING = 1,
134*4882a593Smuzhiyun TSL2772_CHIP_SUSPENDED = 2
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun enum {
138*4882a593Smuzhiyun TSL2772_SUPPLY_VDD = 0,
139*4882a593Smuzhiyun TSL2772_SUPPLY_VDDIO = 1,
140*4882a593Smuzhiyun TSL2772_NUM_SUPPLIES = 2
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun /* Per-device data */
144*4882a593Smuzhiyun struct tsl2772_als_info {
145*4882a593Smuzhiyun u16 als_ch0;
146*4882a593Smuzhiyun u16 als_ch1;
147*4882a593Smuzhiyun u16 lux;
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun struct tsl2772_chip_info {
151*4882a593Smuzhiyun int chan_table_elements;
152*4882a593Smuzhiyun struct iio_chan_spec channel_with_events[4];
153*4882a593Smuzhiyun struct iio_chan_spec channel_without_events[4];
154*4882a593Smuzhiyun const struct iio_info *info;
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun static const int tsl2772_led_currents[][2] = {
158*4882a593Smuzhiyun { 100000, TSL2772_100_mA },
159*4882a593Smuzhiyun { 50000, TSL2772_50_mA },
160*4882a593Smuzhiyun { 25000, TSL2772_25_mA },
161*4882a593Smuzhiyun { 13000, TSL2772_13_mA },
162*4882a593Smuzhiyun { 0, 0 }
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun struct tsl2772_chip {
166*4882a593Smuzhiyun kernel_ulong_t id;
167*4882a593Smuzhiyun struct mutex prox_mutex;
168*4882a593Smuzhiyun struct mutex als_mutex;
169*4882a593Smuzhiyun struct i2c_client *client;
170*4882a593Smuzhiyun struct regulator_bulk_data supplies[TSL2772_NUM_SUPPLIES];
171*4882a593Smuzhiyun u16 prox_data;
172*4882a593Smuzhiyun struct tsl2772_als_info als_cur_info;
173*4882a593Smuzhiyun struct tsl2772_settings settings;
174*4882a593Smuzhiyun struct tsl2772_platform_data *pdata;
175*4882a593Smuzhiyun int als_gain_time_scale;
176*4882a593Smuzhiyun int als_saturation;
177*4882a593Smuzhiyun int tsl2772_chip_status;
178*4882a593Smuzhiyun u8 tsl2772_config[TSL2772_MAX_CONFIG_REG];
179*4882a593Smuzhiyun const struct tsl2772_chip_info *chip_info;
180*4882a593Smuzhiyun const struct iio_info *info;
181*4882a593Smuzhiyun s64 event_timestamp;
182*4882a593Smuzhiyun /*
183*4882a593Smuzhiyun * This structure is intentionally large to accommodate
184*4882a593Smuzhiyun * updates via sysfs.
185*4882a593Smuzhiyun * Sized to 9 = max 8 segments + 1 termination segment
186*4882a593Smuzhiyun */
187*4882a593Smuzhiyun struct tsl2772_lux tsl2772_device_lux[TSL2772_MAX_LUX_TABLE_SIZE];
188*4882a593Smuzhiyun };
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun /*
191*4882a593Smuzhiyun * Different devices require different coefficents, and these numbers were
192*4882a593Smuzhiyun * derived from the 'Lux Equation' section of the various device datasheets.
193*4882a593Smuzhiyun * All of these coefficients assume a Glass Attenuation (GA) factor of 1.
194*4882a593Smuzhiyun * The coefficients are multiplied by 1000 to avoid floating point operations.
195*4882a593Smuzhiyun * The two rows in each table correspond to the Lux1 and Lux2 equations from
196*4882a593Smuzhiyun * the datasheets.
197*4882a593Smuzhiyun */
198*4882a593Smuzhiyun static const struct tsl2772_lux tsl2x71_lux_table[TSL2772_DEF_LUX_TABLE_SZ] = {
199*4882a593Smuzhiyun { 53000, 106000 },
200*4882a593Smuzhiyun { 31800, 53000 },
201*4882a593Smuzhiyun { 0, 0 },
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun static const struct tsl2772_lux tmd2x71_lux_table[TSL2772_DEF_LUX_TABLE_SZ] = {
205*4882a593Smuzhiyun { 24000, 48000 },
206*4882a593Smuzhiyun { 14400, 24000 },
207*4882a593Smuzhiyun { 0, 0 },
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun static const struct tsl2772_lux tsl2x72_lux_table[TSL2772_DEF_LUX_TABLE_SZ] = {
211*4882a593Smuzhiyun { 60000, 112200 },
212*4882a593Smuzhiyun { 37800, 60000 },
213*4882a593Smuzhiyun { 0, 0 },
214*4882a593Smuzhiyun };
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun static const struct tsl2772_lux tmd2x72_lux_table[TSL2772_DEF_LUX_TABLE_SZ] = {
217*4882a593Smuzhiyun { 20000, 35000 },
218*4882a593Smuzhiyun { 12600, 20000 },
219*4882a593Smuzhiyun { 0, 0 },
220*4882a593Smuzhiyun };
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun static const struct tsl2772_lux apds9930_lux_table[TSL2772_DEF_LUX_TABLE_SZ] = {
223*4882a593Smuzhiyun { 52000, 96824 },
224*4882a593Smuzhiyun { 38792, 67132 },
225*4882a593Smuzhiyun { 0, 0 },
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun static const struct tsl2772_lux *tsl2772_default_lux_table_group[] = {
229*4882a593Smuzhiyun [tsl2571] = tsl2x71_lux_table,
230*4882a593Smuzhiyun [tsl2671] = tsl2x71_lux_table,
231*4882a593Smuzhiyun [tmd2671] = tmd2x71_lux_table,
232*4882a593Smuzhiyun [tsl2771] = tsl2x71_lux_table,
233*4882a593Smuzhiyun [tmd2771] = tmd2x71_lux_table,
234*4882a593Smuzhiyun [tsl2572] = tsl2x72_lux_table,
235*4882a593Smuzhiyun [tsl2672] = tsl2x72_lux_table,
236*4882a593Smuzhiyun [tmd2672] = tmd2x72_lux_table,
237*4882a593Smuzhiyun [tsl2772] = tsl2x72_lux_table,
238*4882a593Smuzhiyun [tmd2772] = tmd2x72_lux_table,
239*4882a593Smuzhiyun [apds9930] = apds9930_lux_table,
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun static const struct tsl2772_settings tsl2772_default_settings = {
243*4882a593Smuzhiyun .als_time = 255, /* 2.72 / 2.73 ms */
244*4882a593Smuzhiyun .als_gain = 0,
245*4882a593Smuzhiyun .prox_time = 255, /* 2.72 / 2.73 ms */
246*4882a593Smuzhiyun .prox_gain = 0,
247*4882a593Smuzhiyun .wait_time = 255,
248*4882a593Smuzhiyun .als_prox_config = 0,
249*4882a593Smuzhiyun .als_gain_trim = 1000,
250*4882a593Smuzhiyun .als_cal_target = 150,
251*4882a593Smuzhiyun .als_persistence = 1,
252*4882a593Smuzhiyun .als_interrupt_en = false,
253*4882a593Smuzhiyun .als_thresh_low = 200,
254*4882a593Smuzhiyun .als_thresh_high = 256,
255*4882a593Smuzhiyun .prox_persistence = 1,
256*4882a593Smuzhiyun .prox_interrupt_en = false,
257*4882a593Smuzhiyun .prox_thres_low = 0,
258*4882a593Smuzhiyun .prox_thres_high = 512,
259*4882a593Smuzhiyun .prox_max_samples_cal = 30,
260*4882a593Smuzhiyun .prox_pulse_count = 8,
261*4882a593Smuzhiyun .prox_diode = TSL2772_DIODE1,
262*4882a593Smuzhiyun .prox_power = TSL2772_100_mA
263*4882a593Smuzhiyun };
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun static const s16 tsl2772_als_gain[] = {
266*4882a593Smuzhiyun 1,
267*4882a593Smuzhiyun 8,
268*4882a593Smuzhiyun 16,
269*4882a593Smuzhiyun 120
270*4882a593Smuzhiyun };
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun static const s16 tsl2772_prox_gain[] = {
273*4882a593Smuzhiyun 1,
274*4882a593Smuzhiyun 2,
275*4882a593Smuzhiyun 4,
276*4882a593Smuzhiyun 8
277*4882a593Smuzhiyun };
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun static const int tsl2772_int_time_avail[][6] = {
280*4882a593Smuzhiyun [tsl2571] = { 0, 2720, 0, 2720, 0, 696000 },
281*4882a593Smuzhiyun [tsl2671] = { 0, 2720, 0, 2720, 0, 696000 },
282*4882a593Smuzhiyun [tmd2671] = { 0, 2720, 0, 2720, 0, 696000 },
283*4882a593Smuzhiyun [tsl2771] = { 0, 2720, 0, 2720, 0, 696000 },
284*4882a593Smuzhiyun [tmd2771] = { 0, 2720, 0, 2720, 0, 696000 },
285*4882a593Smuzhiyun [tsl2572] = { 0, 2730, 0, 2730, 0, 699000 },
286*4882a593Smuzhiyun [tsl2672] = { 0, 2730, 0, 2730, 0, 699000 },
287*4882a593Smuzhiyun [tmd2672] = { 0, 2730, 0, 2730, 0, 699000 },
288*4882a593Smuzhiyun [tsl2772] = { 0, 2730, 0, 2730, 0, 699000 },
289*4882a593Smuzhiyun [tmd2772] = { 0, 2730, 0, 2730, 0, 699000 },
290*4882a593Smuzhiyun [apds9930] = { 0, 2730, 0, 2730, 0, 699000 },
291*4882a593Smuzhiyun };
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun static int tsl2772_int_calibscale_avail[] = { 1, 8, 16, 120 };
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun static int tsl2772_prox_calibscale_avail[] = { 1, 2, 4, 8 };
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun /* Channel variations */
298*4882a593Smuzhiyun enum {
299*4882a593Smuzhiyun ALS,
300*4882a593Smuzhiyun PRX,
301*4882a593Smuzhiyun ALSPRX,
302*4882a593Smuzhiyun PRX2,
303*4882a593Smuzhiyun ALSPRX2,
304*4882a593Smuzhiyun };
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun static const u8 device_channel_config[] = {
307*4882a593Smuzhiyun [tsl2571] = ALS,
308*4882a593Smuzhiyun [tsl2671] = PRX,
309*4882a593Smuzhiyun [tmd2671] = PRX,
310*4882a593Smuzhiyun [tsl2771] = ALSPRX,
311*4882a593Smuzhiyun [tmd2771] = ALSPRX,
312*4882a593Smuzhiyun [tsl2572] = ALS,
313*4882a593Smuzhiyun [tsl2672] = PRX2,
314*4882a593Smuzhiyun [tmd2672] = PRX2,
315*4882a593Smuzhiyun [tsl2772] = ALSPRX2,
316*4882a593Smuzhiyun [tmd2772] = ALSPRX2,
317*4882a593Smuzhiyun [apds9930] = ALSPRX2,
318*4882a593Smuzhiyun };
319*4882a593Smuzhiyun
tsl2772_read_status(struct tsl2772_chip * chip)320*4882a593Smuzhiyun static int tsl2772_read_status(struct tsl2772_chip *chip)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun int ret;
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(chip->client,
325*4882a593Smuzhiyun TSL2772_CMD_REG | TSL2772_STATUS);
326*4882a593Smuzhiyun if (ret < 0)
327*4882a593Smuzhiyun dev_err(&chip->client->dev,
328*4882a593Smuzhiyun "%s: failed to read STATUS register: %d\n", __func__,
329*4882a593Smuzhiyun ret);
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun return ret;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
tsl2772_write_control_reg(struct tsl2772_chip * chip,u8 data)334*4882a593Smuzhiyun static int tsl2772_write_control_reg(struct tsl2772_chip *chip, u8 data)
335*4882a593Smuzhiyun {
336*4882a593Smuzhiyun int ret;
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(chip->client,
339*4882a593Smuzhiyun TSL2772_CMD_REG | TSL2772_CNTRL, data);
340*4882a593Smuzhiyun if (ret < 0) {
341*4882a593Smuzhiyun dev_err(&chip->client->dev,
342*4882a593Smuzhiyun "%s: failed to write to control register %x: %d\n",
343*4882a593Smuzhiyun __func__, data, ret);
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun return ret;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
tsl2772_read_autoinc_regs(struct tsl2772_chip * chip,int lower_reg,int upper_reg)349*4882a593Smuzhiyun static int tsl2772_read_autoinc_regs(struct tsl2772_chip *chip, int lower_reg,
350*4882a593Smuzhiyun int upper_reg)
351*4882a593Smuzhiyun {
352*4882a593Smuzhiyun u8 buf[2];
353*4882a593Smuzhiyun int ret;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun ret = i2c_smbus_write_byte(chip->client,
356*4882a593Smuzhiyun TSL2772_CMD_REG | TSL2772_CMD_AUTOINC_PROTO |
357*4882a593Smuzhiyun lower_reg);
358*4882a593Smuzhiyun if (ret < 0) {
359*4882a593Smuzhiyun dev_err(&chip->client->dev,
360*4882a593Smuzhiyun "%s: failed to enable auto increment protocol: %d\n",
361*4882a593Smuzhiyun __func__, ret);
362*4882a593Smuzhiyun return ret;
363*4882a593Smuzhiyun }
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(chip->client,
366*4882a593Smuzhiyun TSL2772_CMD_REG | lower_reg);
367*4882a593Smuzhiyun if (ret < 0) {
368*4882a593Smuzhiyun dev_err(&chip->client->dev,
369*4882a593Smuzhiyun "%s: failed to read from register %x: %d\n", __func__,
370*4882a593Smuzhiyun lower_reg, ret);
371*4882a593Smuzhiyun return ret;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun buf[0] = ret;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(chip->client,
376*4882a593Smuzhiyun TSL2772_CMD_REG | upper_reg);
377*4882a593Smuzhiyun if (ret < 0) {
378*4882a593Smuzhiyun dev_err(&chip->client->dev,
379*4882a593Smuzhiyun "%s: failed to read from register %x: %d\n", __func__,
380*4882a593Smuzhiyun upper_reg, ret);
381*4882a593Smuzhiyun return ret;
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun buf[1] = ret;
384*4882a593Smuzhiyun
385*4882a593Smuzhiyun ret = i2c_smbus_write_byte(chip->client,
386*4882a593Smuzhiyun TSL2772_CMD_REG | TSL2772_CMD_REPEAT_PROTO |
387*4882a593Smuzhiyun lower_reg);
388*4882a593Smuzhiyun if (ret < 0) {
389*4882a593Smuzhiyun dev_err(&chip->client->dev,
390*4882a593Smuzhiyun "%s: failed to enable repeated byte protocol: %d\n",
391*4882a593Smuzhiyun __func__, ret);
392*4882a593Smuzhiyun return ret;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun return le16_to_cpup((const __le16 *)&buf[0]);
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun /**
399*4882a593Smuzhiyun * tsl2772_get_lux() - Reads and calculates current lux value.
400*4882a593Smuzhiyun * @indio_dev: pointer to IIO device
401*4882a593Smuzhiyun *
402*4882a593Smuzhiyun * The raw ch0 and ch1 values of the ambient light sensed in the last
403*4882a593Smuzhiyun * integration cycle are read from the device. The raw values are multiplied
404*4882a593Smuzhiyun * by a device-specific scale factor, and divided by the integration time and
405*4882a593Smuzhiyun * device gain. The code supports multiple lux equations through the lux table
406*4882a593Smuzhiyun * coefficients. A lux gain trim is applied to each lux equation, and then the
407*4882a593Smuzhiyun * maximum lux within the interval 0..65535 is selected.
408*4882a593Smuzhiyun */
tsl2772_get_lux(struct iio_dev * indio_dev)409*4882a593Smuzhiyun static int tsl2772_get_lux(struct iio_dev *indio_dev)
410*4882a593Smuzhiyun {
411*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
412*4882a593Smuzhiyun struct tsl2772_lux *p;
413*4882a593Smuzhiyun int max_lux, ret;
414*4882a593Smuzhiyun bool overflow;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun mutex_lock(&chip->als_mutex);
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun if (chip->tsl2772_chip_status != TSL2772_CHIP_WORKING) {
419*4882a593Smuzhiyun dev_err(&chip->client->dev, "%s: device is not enabled\n",
420*4882a593Smuzhiyun __func__);
421*4882a593Smuzhiyun ret = -EBUSY;
422*4882a593Smuzhiyun goto out_unlock;
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun ret = tsl2772_read_status(chip);
426*4882a593Smuzhiyun if (ret < 0)
427*4882a593Smuzhiyun goto out_unlock;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun if (!(ret & TSL2772_STA_ADC_VALID)) {
430*4882a593Smuzhiyun dev_err(&chip->client->dev,
431*4882a593Smuzhiyun "%s: data not valid yet\n", __func__);
432*4882a593Smuzhiyun ret = chip->als_cur_info.lux; /* return LAST VALUE */
433*4882a593Smuzhiyun goto out_unlock;
434*4882a593Smuzhiyun }
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun ret = tsl2772_read_autoinc_regs(chip, TSL2772_ALS_CHAN0LO,
437*4882a593Smuzhiyun TSL2772_ALS_CHAN0HI);
438*4882a593Smuzhiyun if (ret < 0)
439*4882a593Smuzhiyun goto out_unlock;
440*4882a593Smuzhiyun chip->als_cur_info.als_ch0 = ret;
441*4882a593Smuzhiyun
442*4882a593Smuzhiyun ret = tsl2772_read_autoinc_regs(chip, TSL2772_ALS_CHAN1LO,
443*4882a593Smuzhiyun TSL2772_ALS_CHAN1HI);
444*4882a593Smuzhiyun if (ret < 0)
445*4882a593Smuzhiyun goto out_unlock;
446*4882a593Smuzhiyun chip->als_cur_info.als_ch1 = ret;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun if (chip->als_cur_info.als_ch0 >= chip->als_saturation) {
449*4882a593Smuzhiyun max_lux = TSL2772_LUX_CALC_OVER_FLOW;
450*4882a593Smuzhiyun goto update_struct_with_max_lux;
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun if (!chip->als_cur_info.als_ch0) {
454*4882a593Smuzhiyun /* have no data, so return LAST VALUE */
455*4882a593Smuzhiyun ret = chip->als_cur_info.lux;
456*4882a593Smuzhiyun goto out_unlock;
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun max_lux = 0;
460*4882a593Smuzhiyun overflow = false;
461*4882a593Smuzhiyun for (p = (struct tsl2772_lux *)chip->tsl2772_device_lux; p->ch0 != 0;
462*4882a593Smuzhiyun p++) {
463*4882a593Smuzhiyun int lux;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun lux = ((chip->als_cur_info.als_ch0 * p->ch0) -
466*4882a593Smuzhiyun (chip->als_cur_info.als_ch1 * p->ch1)) /
467*4882a593Smuzhiyun chip->als_gain_time_scale;
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun /*
470*4882a593Smuzhiyun * The als_gain_trim can have a value within the range 250..4000
471*4882a593Smuzhiyun * and is a multiplier for the lux. A trim of 1000 makes no
472*4882a593Smuzhiyun * changes to the lux, less than 1000 scales it down, and
473*4882a593Smuzhiyun * greater than 1000 scales it up.
474*4882a593Smuzhiyun */
475*4882a593Smuzhiyun lux = (lux * chip->settings.als_gain_trim) / 1000;
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun if (lux > TSL2772_LUX_CALC_OVER_FLOW) {
478*4882a593Smuzhiyun overflow = true;
479*4882a593Smuzhiyun continue;
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun max_lux = max(max_lux, lux);
483*4882a593Smuzhiyun }
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun if (overflow && max_lux == 0)
486*4882a593Smuzhiyun max_lux = TSL2772_LUX_CALC_OVER_FLOW;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun update_struct_with_max_lux:
489*4882a593Smuzhiyun chip->als_cur_info.lux = max_lux;
490*4882a593Smuzhiyun ret = max_lux;
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun out_unlock:
493*4882a593Smuzhiyun mutex_unlock(&chip->als_mutex);
494*4882a593Smuzhiyun
495*4882a593Smuzhiyun return ret;
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun /**
499*4882a593Smuzhiyun * tsl2772_get_prox() - Reads proximity data registers and updates
500*4882a593Smuzhiyun * chip->prox_data.
501*4882a593Smuzhiyun *
502*4882a593Smuzhiyun * @indio_dev: pointer to IIO device
503*4882a593Smuzhiyun */
tsl2772_get_prox(struct iio_dev * indio_dev)504*4882a593Smuzhiyun static int tsl2772_get_prox(struct iio_dev *indio_dev)
505*4882a593Smuzhiyun {
506*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
507*4882a593Smuzhiyun int ret;
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun mutex_lock(&chip->prox_mutex);
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun ret = tsl2772_read_status(chip);
512*4882a593Smuzhiyun if (ret < 0)
513*4882a593Smuzhiyun goto prox_poll_err;
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun switch (chip->id) {
516*4882a593Smuzhiyun case tsl2571:
517*4882a593Smuzhiyun case tsl2671:
518*4882a593Smuzhiyun case tmd2671:
519*4882a593Smuzhiyun case tsl2771:
520*4882a593Smuzhiyun case tmd2771:
521*4882a593Smuzhiyun if (!(ret & TSL2772_STA_ADC_VALID)) {
522*4882a593Smuzhiyun ret = -EINVAL;
523*4882a593Smuzhiyun goto prox_poll_err;
524*4882a593Smuzhiyun }
525*4882a593Smuzhiyun break;
526*4882a593Smuzhiyun case tsl2572:
527*4882a593Smuzhiyun case tsl2672:
528*4882a593Smuzhiyun case tmd2672:
529*4882a593Smuzhiyun case tsl2772:
530*4882a593Smuzhiyun case tmd2772:
531*4882a593Smuzhiyun case apds9930:
532*4882a593Smuzhiyun if (!(ret & TSL2772_STA_PRX_VALID)) {
533*4882a593Smuzhiyun ret = -EINVAL;
534*4882a593Smuzhiyun goto prox_poll_err;
535*4882a593Smuzhiyun }
536*4882a593Smuzhiyun break;
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun ret = tsl2772_read_autoinc_regs(chip, TSL2772_PRX_LO, TSL2772_PRX_HI);
540*4882a593Smuzhiyun if (ret < 0)
541*4882a593Smuzhiyun goto prox_poll_err;
542*4882a593Smuzhiyun chip->prox_data = ret;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun prox_poll_err:
545*4882a593Smuzhiyun mutex_unlock(&chip->prox_mutex);
546*4882a593Smuzhiyun
547*4882a593Smuzhiyun return ret;
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun
tsl2772_read_prox_led_current(struct tsl2772_chip * chip)550*4882a593Smuzhiyun static int tsl2772_read_prox_led_current(struct tsl2772_chip *chip)
551*4882a593Smuzhiyun {
552*4882a593Smuzhiyun struct device_node *of_node = chip->client->dev.of_node;
553*4882a593Smuzhiyun int ret, tmp, i;
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun ret = of_property_read_u32(of_node, "led-max-microamp", &tmp);
556*4882a593Smuzhiyun if (ret < 0)
557*4882a593Smuzhiyun return ret;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun for (i = 0; tsl2772_led_currents[i][0] != 0; i++) {
560*4882a593Smuzhiyun if (tmp == tsl2772_led_currents[i][0]) {
561*4882a593Smuzhiyun chip->settings.prox_power = tsl2772_led_currents[i][1];
562*4882a593Smuzhiyun return 0;
563*4882a593Smuzhiyun }
564*4882a593Smuzhiyun }
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun dev_err(&chip->client->dev, "Invalid value %d for led-max-microamp\n",
567*4882a593Smuzhiyun tmp);
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun return -EINVAL;
570*4882a593Smuzhiyun
571*4882a593Smuzhiyun }
572*4882a593Smuzhiyun
tsl2772_read_prox_diodes(struct tsl2772_chip * chip)573*4882a593Smuzhiyun static int tsl2772_read_prox_diodes(struct tsl2772_chip *chip)
574*4882a593Smuzhiyun {
575*4882a593Smuzhiyun struct device_node *of_node = chip->client->dev.of_node;
576*4882a593Smuzhiyun int i, ret, num_leds, prox_diode_mask;
577*4882a593Smuzhiyun u32 leds[TSL2772_MAX_PROX_LEDS];
578*4882a593Smuzhiyun
579*4882a593Smuzhiyun ret = of_property_count_u32_elems(of_node, "amstaos,proximity-diodes");
580*4882a593Smuzhiyun if (ret < 0)
581*4882a593Smuzhiyun return ret;
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun num_leds = ret;
584*4882a593Smuzhiyun if (num_leds > TSL2772_MAX_PROX_LEDS)
585*4882a593Smuzhiyun num_leds = TSL2772_MAX_PROX_LEDS;
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun ret = of_property_read_u32_array(of_node, "amstaos,proximity-diodes",
588*4882a593Smuzhiyun leds, num_leds);
589*4882a593Smuzhiyun if (ret < 0) {
590*4882a593Smuzhiyun dev_err(&chip->client->dev,
591*4882a593Smuzhiyun "Invalid value for amstaos,proximity-diodes: %d.\n",
592*4882a593Smuzhiyun ret);
593*4882a593Smuzhiyun return ret;
594*4882a593Smuzhiyun }
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun prox_diode_mask = 0;
597*4882a593Smuzhiyun for (i = 0; i < num_leds; i++) {
598*4882a593Smuzhiyun if (leds[i] == 0)
599*4882a593Smuzhiyun prox_diode_mask |= TSL2772_DIODE0;
600*4882a593Smuzhiyun else if (leds[i] == 1)
601*4882a593Smuzhiyun prox_diode_mask |= TSL2772_DIODE1;
602*4882a593Smuzhiyun else {
603*4882a593Smuzhiyun dev_err(&chip->client->dev,
604*4882a593Smuzhiyun "Invalid value %d in amstaos,proximity-diodes.\n",
605*4882a593Smuzhiyun leds[i]);
606*4882a593Smuzhiyun return -EINVAL;
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun
610*4882a593Smuzhiyun return 0;
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun
tsl2772_parse_dt(struct tsl2772_chip * chip)613*4882a593Smuzhiyun static void tsl2772_parse_dt(struct tsl2772_chip *chip)
614*4882a593Smuzhiyun {
615*4882a593Smuzhiyun tsl2772_read_prox_led_current(chip);
616*4882a593Smuzhiyun tsl2772_read_prox_diodes(chip);
617*4882a593Smuzhiyun }
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun /**
620*4882a593Smuzhiyun * tsl2772_defaults() - Populates the device nominal operating parameters
621*4882a593Smuzhiyun * with those provided by a 'platform' data struct or
622*4882a593Smuzhiyun * with prefined defaults.
623*4882a593Smuzhiyun *
624*4882a593Smuzhiyun * @chip: pointer to device structure.
625*4882a593Smuzhiyun */
tsl2772_defaults(struct tsl2772_chip * chip)626*4882a593Smuzhiyun static void tsl2772_defaults(struct tsl2772_chip *chip)
627*4882a593Smuzhiyun {
628*4882a593Smuzhiyun /* If Operational settings defined elsewhere.. */
629*4882a593Smuzhiyun if (chip->pdata && chip->pdata->platform_default_settings)
630*4882a593Smuzhiyun memcpy(&chip->settings, chip->pdata->platform_default_settings,
631*4882a593Smuzhiyun sizeof(tsl2772_default_settings));
632*4882a593Smuzhiyun else
633*4882a593Smuzhiyun memcpy(&chip->settings, &tsl2772_default_settings,
634*4882a593Smuzhiyun sizeof(tsl2772_default_settings));
635*4882a593Smuzhiyun
636*4882a593Smuzhiyun /* Load up the proper lux table. */
637*4882a593Smuzhiyun if (chip->pdata && chip->pdata->platform_lux_table[0].ch0 != 0)
638*4882a593Smuzhiyun memcpy(chip->tsl2772_device_lux,
639*4882a593Smuzhiyun chip->pdata->platform_lux_table,
640*4882a593Smuzhiyun sizeof(chip->pdata->platform_lux_table));
641*4882a593Smuzhiyun else
642*4882a593Smuzhiyun memcpy(chip->tsl2772_device_lux,
643*4882a593Smuzhiyun tsl2772_default_lux_table_group[chip->id],
644*4882a593Smuzhiyun TSL2772_DEFAULT_TABLE_BYTES);
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun tsl2772_parse_dt(chip);
647*4882a593Smuzhiyun }
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun /**
650*4882a593Smuzhiyun * tsl2772_als_calibrate() - Obtain single reading and calculate
651*4882a593Smuzhiyun * the als_gain_trim.
652*4882a593Smuzhiyun *
653*4882a593Smuzhiyun * @indio_dev: pointer to IIO device
654*4882a593Smuzhiyun */
tsl2772_als_calibrate(struct iio_dev * indio_dev)655*4882a593Smuzhiyun static int tsl2772_als_calibrate(struct iio_dev *indio_dev)
656*4882a593Smuzhiyun {
657*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
658*4882a593Smuzhiyun int ret, lux_val;
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(chip->client,
661*4882a593Smuzhiyun TSL2772_CMD_REG | TSL2772_CNTRL);
662*4882a593Smuzhiyun if (ret < 0) {
663*4882a593Smuzhiyun dev_err(&chip->client->dev,
664*4882a593Smuzhiyun "%s: failed to read from the CNTRL register\n",
665*4882a593Smuzhiyun __func__);
666*4882a593Smuzhiyun return ret;
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun if ((ret & (TSL2772_CNTL_ADC_ENBL | TSL2772_CNTL_PWR_ON))
670*4882a593Smuzhiyun != (TSL2772_CNTL_ADC_ENBL | TSL2772_CNTL_PWR_ON)) {
671*4882a593Smuzhiyun dev_err(&chip->client->dev,
672*4882a593Smuzhiyun "%s: Device is not powered on and/or ADC is not enabled\n",
673*4882a593Smuzhiyun __func__);
674*4882a593Smuzhiyun return -EINVAL;
675*4882a593Smuzhiyun } else if ((ret & TSL2772_STA_ADC_VALID) != TSL2772_STA_ADC_VALID) {
676*4882a593Smuzhiyun dev_err(&chip->client->dev,
677*4882a593Smuzhiyun "%s: The two ADC channels have not completed an integration cycle\n",
678*4882a593Smuzhiyun __func__);
679*4882a593Smuzhiyun return -ENODATA;
680*4882a593Smuzhiyun }
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun lux_val = tsl2772_get_lux(indio_dev);
683*4882a593Smuzhiyun if (lux_val < 0) {
684*4882a593Smuzhiyun dev_err(&chip->client->dev,
685*4882a593Smuzhiyun "%s: failed to get lux\n", __func__);
686*4882a593Smuzhiyun return lux_val;
687*4882a593Smuzhiyun }
688*4882a593Smuzhiyun if (lux_val == 0)
689*4882a593Smuzhiyun return -ERANGE;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun ret = (chip->settings.als_cal_target * chip->settings.als_gain_trim) /
692*4882a593Smuzhiyun lux_val;
693*4882a593Smuzhiyun if (ret < TSL2772_ALS_GAIN_TRIM_MIN || ret > TSL2772_ALS_GAIN_TRIM_MAX)
694*4882a593Smuzhiyun return -ERANGE;
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun chip->settings.als_gain_trim = ret;
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun return ret;
699*4882a593Smuzhiyun }
700*4882a593Smuzhiyun
tsl2772_disable_regulators_action(void * _data)701*4882a593Smuzhiyun static void tsl2772_disable_regulators_action(void *_data)
702*4882a593Smuzhiyun {
703*4882a593Smuzhiyun struct tsl2772_chip *chip = _data;
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun regulator_bulk_disable(ARRAY_SIZE(chip->supplies), chip->supplies);
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun
tsl2772_chip_on(struct iio_dev * indio_dev)708*4882a593Smuzhiyun static int tsl2772_chip_on(struct iio_dev *indio_dev)
709*4882a593Smuzhiyun {
710*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
711*4882a593Smuzhiyun int ret, i, als_count, als_time_us;
712*4882a593Smuzhiyun u8 *dev_reg, reg_val;
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun /* Non calculated parameters */
715*4882a593Smuzhiyun chip->tsl2772_config[TSL2772_ALS_TIME] = chip->settings.als_time;
716*4882a593Smuzhiyun chip->tsl2772_config[TSL2772_PRX_TIME] = chip->settings.prox_time;
717*4882a593Smuzhiyun chip->tsl2772_config[TSL2772_WAIT_TIME] = chip->settings.wait_time;
718*4882a593Smuzhiyun chip->tsl2772_config[TSL2772_ALS_PRX_CONFIG] =
719*4882a593Smuzhiyun chip->settings.als_prox_config;
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun chip->tsl2772_config[TSL2772_ALS_MINTHRESHLO] =
722*4882a593Smuzhiyun (chip->settings.als_thresh_low) & 0xFF;
723*4882a593Smuzhiyun chip->tsl2772_config[TSL2772_ALS_MINTHRESHHI] =
724*4882a593Smuzhiyun (chip->settings.als_thresh_low >> 8) & 0xFF;
725*4882a593Smuzhiyun chip->tsl2772_config[TSL2772_ALS_MAXTHRESHLO] =
726*4882a593Smuzhiyun (chip->settings.als_thresh_high) & 0xFF;
727*4882a593Smuzhiyun chip->tsl2772_config[TSL2772_ALS_MAXTHRESHHI] =
728*4882a593Smuzhiyun (chip->settings.als_thresh_high >> 8) & 0xFF;
729*4882a593Smuzhiyun chip->tsl2772_config[TSL2772_PERSISTENCE] =
730*4882a593Smuzhiyun (chip->settings.prox_persistence & 0xFF) << 4 |
731*4882a593Smuzhiyun (chip->settings.als_persistence & 0xFF);
732*4882a593Smuzhiyun
733*4882a593Smuzhiyun chip->tsl2772_config[TSL2772_PRX_COUNT] =
734*4882a593Smuzhiyun chip->settings.prox_pulse_count;
735*4882a593Smuzhiyun chip->tsl2772_config[TSL2772_PRX_MINTHRESHLO] =
736*4882a593Smuzhiyun (chip->settings.prox_thres_low) & 0xFF;
737*4882a593Smuzhiyun chip->tsl2772_config[TSL2772_PRX_MINTHRESHHI] =
738*4882a593Smuzhiyun (chip->settings.prox_thres_low >> 8) & 0xFF;
739*4882a593Smuzhiyun chip->tsl2772_config[TSL2772_PRX_MAXTHRESHLO] =
740*4882a593Smuzhiyun (chip->settings.prox_thres_high) & 0xFF;
741*4882a593Smuzhiyun chip->tsl2772_config[TSL2772_PRX_MAXTHRESHHI] =
742*4882a593Smuzhiyun (chip->settings.prox_thres_high >> 8) & 0xFF;
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun /* and make sure we're not already on */
745*4882a593Smuzhiyun if (chip->tsl2772_chip_status == TSL2772_CHIP_WORKING) {
746*4882a593Smuzhiyun /* if forcing a register update - turn off, then on */
747*4882a593Smuzhiyun dev_info(&chip->client->dev, "device is already enabled\n");
748*4882a593Smuzhiyun return -EINVAL;
749*4882a593Smuzhiyun }
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun /* Set the gain based on tsl2772_settings struct */
752*4882a593Smuzhiyun chip->tsl2772_config[TSL2772_GAIN] =
753*4882a593Smuzhiyun (chip->settings.als_gain & 0xFF) |
754*4882a593Smuzhiyun ((chip->settings.prox_gain & 0xFF) << 2) |
755*4882a593Smuzhiyun (chip->settings.prox_diode << 4) |
756*4882a593Smuzhiyun (chip->settings.prox_power << 6);
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun /* set chip time scaling and saturation */
759*4882a593Smuzhiyun als_count = 256 - chip->settings.als_time;
760*4882a593Smuzhiyun als_time_us = als_count * tsl2772_int_time_avail[chip->id][3];
761*4882a593Smuzhiyun chip->als_saturation = als_count * 768; /* 75% of full scale */
762*4882a593Smuzhiyun chip->als_gain_time_scale = als_time_us *
763*4882a593Smuzhiyun tsl2772_als_gain[chip->settings.als_gain];
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun /*
766*4882a593Smuzhiyun * TSL2772 Specific power-on / adc enable sequence
767*4882a593Smuzhiyun * Power on the device 1st.
768*4882a593Smuzhiyun */
769*4882a593Smuzhiyun ret = tsl2772_write_control_reg(chip, TSL2772_CNTL_PWR_ON);
770*4882a593Smuzhiyun if (ret < 0)
771*4882a593Smuzhiyun return ret;
772*4882a593Smuzhiyun
773*4882a593Smuzhiyun /*
774*4882a593Smuzhiyun * Use the following shadow copy for our delay before enabling ADC.
775*4882a593Smuzhiyun * Write all the registers.
776*4882a593Smuzhiyun */
777*4882a593Smuzhiyun for (i = 0, dev_reg = chip->tsl2772_config;
778*4882a593Smuzhiyun i < TSL2772_MAX_CONFIG_REG; i++) {
779*4882a593Smuzhiyun int reg = TSL2772_CMD_REG + i;
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(chip->client, reg,
782*4882a593Smuzhiyun *dev_reg++);
783*4882a593Smuzhiyun if (ret < 0) {
784*4882a593Smuzhiyun dev_err(&chip->client->dev,
785*4882a593Smuzhiyun "%s: failed to write to register %x: %d\n",
786*4882a593Smuzhiyun __func__, reg, ret);
787*4882a593Smuzhiyun return ret;
788*4882a593Smuzhiyun }
789*4882a593Smuzhiyun }
790*4882a593Smuzhiyun
791*4882a593Smuzhiyun /* Power-on settling time */
792*4882a593Smuzhiyun usleep_range(3000, 3500);
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun reg_val = TSL2772_CNTL_PWR_ON | TSL2772_CNTL_ADC_ENBL |
795*4882a593Smuzhiyun TSL2772_CNTL_PROX_DET_ENBL;
796*4882a593Smuzhiyun if (chip->settings.als_interrupt_en)
797*4882a593Smuzhiyun reg_val |= TSL2772_CNTL_ALS_INT_ENBL;
798*4882a593Smuzhiyun if (chip->settings.prox_interrupt_en)
799*4882a593Smuzhiyun reg_val |= TSL2772_CNTL_PROX_INT_ENBL;
800*4882a593Smuzhiyun
801*4882a593Smuzhiyun ret = tsl2772_write_control_reg(chip, reg_val);
802*4882a593Smuzhiyun if (ret < 0)
803*4882a593Smuzhiyun return ret;
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun ret = i2c_smbus_write_byte(chip->client,
806*4882a593Smuzhiyun TSL2772_CMD_REG | TSL2772_CMD_SPL_FN |
807*4882a593Smuzhiyun TSL2772_CMD_PROXALS_INT_CLR);
808*4882a593Smuzhiyun if (ret < 0) {
809*4882a593Smuzhiyun dev_err(&chip->client->dev,
810*4882a593Smuzhiyun "%s: failed to clear interrupt status: %d\n",
811*4882a593Smuzhiyun __func__, ret);
812*4882a593Smuzhiyun return ret;
813*4882a593Smuzhiyun }
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun chip->tsl2772_chip_status = TSL2772_CHIP_WORKING;
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun return ret;
818*4882a593Smuzhiyun }
819*4882a593Smuzhiyun
tsl2772_chip_off(struct iio_dev * indio_dev)820*4882a593Smuzhiyun static int tsl2772_chip_off(struct iio_dev *indio_dev)
821*4882a593Smuzhiyun {
822*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun /* turn device off */
825*4882a593Smuzhiyun chip->tsl2772_chip_status = TSL2772_CHIP_SUSPENDED;
826*4882a593Smuzhiyun return tsl2772_write_control_reg(chip, 0x00);
827*4882a593Smuzhiyun }
828*4882a593Smuzhiyun
tsl2772_chip_off_action(void * data)829*4882a593Smuzhiyun static void tsl2772_chip_off_action(void *data)
830*4882a593Smuzhiyun {
831*4882a593Smuzhiyun struct iio_dev *indio_dev = data;
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun tsl2772_chip_off(indio_dev);
834*4882a593Smuzhiyun }
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun /**
837*4882a593Smuzhiyun * tsl2772_invoke_change - power cycle the device to implement the user
838*4882a593Smuzhiyun * parameters
839*4882a593Smuzhiyun * @indio_dev: pointer to IIO device
840*4882a593Smuzhiyun *
841*4882a593Smuzhiyun * Obtain and lock both ALS and PROX resources, determine and save device state
842*4882a593Smuzhiyun * (On/Off), cycle device to implement updated parameter, put device back into
843*4882a593Smuzhiyun * proper state, and unlock resource.
844*4882a593Smuzhiyun */
tsl2772_invoke_change(struct iio_dev * indio_dev)845*4882a593Smuzhiyun static int tsl2772_invoke_change(struct iio_dev *indio_dev)
846*4882a593Smuzhiyun {
847*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
848*4882a593Smuzhiyun int device_status = chip->tsl2772_chip_status;
849*4882a593Smuzhiyun int ret;
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun mutex_lock(&chip->als_mutex);
852*4882a593Smuzhiyun mutex_lock(&chip->prox_mutex);
853*4882a593Smuzhiyun
854*4882a593Smuzhiyun if (device_status == TSL2772_CHIP_WORKING) {
855*4882a593Smuzhiyun ret = tsl2772_chip_off(indio_dev);
856*4882a593Smuzhiyun if (ret < 0)
857*4882a593Smuzhiyun goto unlock;
858*4882a593Smuzhiyun }
859*4882a593Smuzhiyun
860*4882a593Smuzhiyun ret = tsl2772_chip_on(indio_dev);
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun unlock:
863*4882a593Smuzhiyun mutex_unlock(&chip->prox_mutex);
864*4882a593Smuzhiyun mutex_unlock(&chip->als_mutex);
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun return ret;
867*4882a593Smuzhiyun }
868*4882a593Smuzhiyun
tsl2772_prox_cal(struct iio_dev * indio_dev)869*4882a593Smuzhiyun static int tsl2772_prox_cal(struct iio_dev *indio_dev)
870*4882a593Smuzhiyun {
871*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
872*4882a593Smuzhiyun int prox_history[MAX_SAMPLES_CAL + 1];
873*4882a593Smuzhiyun int i, ret, mean, max, sample_sum;
874*4882a593Smuzhiyun
875*4882a593Smuzhiyun if (chip->settings.prox_max_samples_cal < 1 ||
876*4882a593Smuzhiyun chip->settings.prox_max_samples_cal > MAX_SAMPLES_CAL)
877*4882a593Smuzhiyun return -EINVAL;
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun for (i = 0; i < chip->settings.prox_max_samples_cal; i++) {
880*4882a593Smuzhiyun usleep_range(15000, 17500);
881*4882a593Smuzhiyun ret = tsl2772_get_prox(indio_dev);
882*4882a593Smuzhiyun if (ret < 0)
883*4882a593Smuzhiyun return ret;
884*4882a593Smuzhiyun
885*4882a593Smuzhiyun prox_history[i] = chip->prox_data;
886*4882a593Smuzhiyun }
887*4882a593Smuzhiyun
888*4882a593Smuzhiyun sample_sum = 0;
889*4882a593Smuzhiyun max = INT_MIN;
890*4882a593Smuzhiyun for (i = 0; i < chip->settings.prox_max_samples_cal; i++) {
891*4882a593Smuzhiyun sample_sum += prox_history[i];
892*4882a593Smuzhiyun max = max(max, prox_history[i]);
893*4882a593Smuzhiyun }
894*4882a593Smuzhiyun mean = sample_sum / chip->settings.prox_max_samples_cal;
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun chip->settings.prox_thres_high = (max << 1) - mean;
897*4882a593Smuzhiyun
898*4882a593Smuzhiyun return tsl2772_invoke_change(indio_dev);
899*4882a593Smuzhiyun }
900*4882a593Smuzhiyun
tsl2772_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)901*4882a593Smuzhiyun static int tsl2772_read_avail(struct iio_dev *indio_dev,
902*4882a593Smuzhiyun struct iio_chan_spec const *chan,
903*4882a593Smuzhiyun const int **vals, int *type, int *length,
904*4882a593Smuzhiyun long mask)
905*4882a593Smuzhiyun {
906*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
907*4882a593Smuzhiyun
908*4882a593Smuzhiyun switch (mask) {
909*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBSCALE:
910*4882a593Smuzhiyun if (chan->type == IIO_INTENSITY) {
911*4882a593Smuzhiyun *length = ARRAY_SIZE(tsl2772_int_calibscale_avail);
912*4882a593Smuzhiyun *vals = tsl2772_int_calibscale_avail;
913*4882a593Smuzhiyun } else {
914*4882a593Smuzhiyun *length = ARRAY_SIZE(tsl2772_prox_calibscale_avail);
915*4882a593Smuzhiyun *vals = tsl2772_prox_calibscale_avail;
916*4882a593Smuzhiyun }
917*4882a593Smuzhiyun *type = IIO_VAL_INT;
918*4882a593Smuzhiyun return IIO_AVAIL_LIST;
919*4882a593Smuzhiyun case IIO_CHAN_INFO_INT_TIME:
920*4882a593Smuzhiyun *length = ARRAY_SIZE(tsl2772_int_time_avail[chip->id]);
921*4882a593Smuzhiyun *vals = tsl2772_int_time_avail[chip->id];
922*4882a593Smuzhiyun *type = IIO_VAL_INT_PLUS_MICRO;
923*4882a593Smuzhiyun return IIO_AVAIL_RANGE;
924*4882a593Smuzhiyun }
925*4882a593Smuzhiyun
926*4882a593Smuzhiyun return -EINVAL;
927*4882a593Smuzhiyun }
928*4882a593Smuzhiyun
in_illuminance0_target_input_show(struct device * dev,struct device_attribute * attr,char * buf)929*4882a593Smuzhiyun static ssize_t in_illuminance0_target_input_show(struct device *dev,
930*4882a593Smuzhiyun struct device_attribute *attr,
931*4882a593Smuzhiyun char *buf)
932*4882a593Smuzhiyun {
933*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(dev_to_iio_dev(dev));
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun return scnprintf(buf, PAGE_SIZE, "%d\n", chip->settings.als_cal_target);
936*4882a593Smuzhiyun }
937*4882a593Smuzhiyun
in_illuminance0_target_input_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)938*4882a593Smuzhiyun static ssize_t in_illuminance0_target_input_store(struct device *dev,
939*4882a593Smuzhiyun struct device_attribute *attr,
940*4882a593Smuzhiyun const char *buf, size_t len)
941*4882a593Smuzhiyun {
942*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_to_iio_dev(dev);
943*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
944*4882a593Smuzhiyun u16 value;
945*4882a593Smuzhiyun int ret;
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun if (kstrtou16(buf, 0, &value))
948*4882a593Smuzhiyun return -EINVAL;
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun chip->settings.als_cal_target = value;
951*4882a593Smuzhiyun ret = tsl2772_invoke_change(indio_dev);
952*4882a593Smuzhiyun if (ret < 0)
953*4882a593Smuzhiyun return ret;
954*4882a593Smuzhiyun
955*4882a593Smuzhiyun return len;
956*4882a593Smuzhiyun }
957*4882a593Smuzhiyun
in_illuminance0_calibrate_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)958*4882a593Smuzhiyun static ssize_t in_illuminance0_calibrate_store(struct device *dev,
959*4882a593Smuzhiyun struct device_attribute *attr,
960*4882a593Smuzhiyun const char *buf, size_t len)
961*4882a593Smuzhiyun {
962*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_to_iio_dev(dev);
963*4882a593Smuzhiyun bool value;
964*4882a593Smuzhiyun int ret;
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun if (kstrtobool(buf, &value) || !value)
967*4882a593Smuzhiyun return -EINVAL;
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun ret = tsl2772_als_calibrate(indio_dev);
970*4882a593Smuzhiyun if (ret < 0)
971*4882a593Smuzhiyun return ret;
972*4882a593Smuzhiyun
973*4882a593Smuzhiyun ret = tsl2772_invoke_change(indio_dev);
974*4882a593Smuzhiyun if (ret < 0)
975*4882a593Smuzhiyun return ret;
976*4882a593Smuzhiyun
977*4882a593Smuzhiyun return len;
978*4882a593Smuzhiyun }
979*4882a593Smuzhiyun
in_illuminance0_lux_table_show(struct device * dev,struct device_attribute * attr,char * buf)980*4882a593Smuzhiyun static ssize_t in_illuminance0_lux_table_show(struct device *dev,
981*4882a593Smuzhiyun struct device_attribute *attr,
982*4882a593Smuzhiyun char *buf)
983*4882a593Smuzhiyun {
984*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(dev_to_iio_dev(dev));
985*4882a593Smuzhiyun int i = 0;
986*4882a593Smuzhiyun int offset = 0;
987*4882a593Smuzhiyun
988*4882a593Smuzhiyun while (i < TSL2772_MAX_LUX_TABLE_SIZE) {
989*4882a593Smuzhiyun offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%u,%u,",
990*4882a593Smuzhiyun chip->tsl2772_device_lux[i].ch0,
991*4882a593Smuzhiyun chip->tsl2772_device_lux[i].ch1);
992*4882a593Smuzhiyun if (chip->tsl2772_device_lux[i].ch0 == 0) {
993*4882a593Smuzhiyun /*
994*4882a593Smuzhiyun * We just printed the first "0" entry.
995*4882a593Smuzhiyun * Now get rid of the extra "," and break.
996*4882a593Smuzhiyun */
997*4882a593Smuzhiyun offset--;
998*4882a593Smuzhiyun break;
999*4882a593Smuzhiyun }
1000*4882a593Smuzhiyun i++;
1001*4882a593Smuzhiyun }
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun offset += scnprintf(buf + offset, PAGE_SIZE - offset, "\n");
1004*4882a593Smuzhiyun return offset;
1005*4882a593Smuzhiyun }
1006*4882a593Smuzhiyun
in_illuminance0_lux_table_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)1007*4882a593Smuzhiyun static ssize_t in_illuminance0_lux_table_store(struct device *dev,
1008*4882a593Smuzhiyun struct device_attribute *attr,
1009*4882a593Smuzhiyun const char *buf, size_t len)
1010*4882a593Smuzhiyun {
1011*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1012*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
1013*4882a593Smuzhiyun int value[ARRAY_SIZE(chip->tsl2772_device_lux) * 2 + 1];
1014*4882a593Smuzhiyun int n, ret;
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun get_options(buf, ARRAY_SIZE(value), value);
1017*4882a593Smuzhiyun
1018*4882a593Smuzhiyun /*
1019*4882a593Smuzhiyun * We now have an array of ints starting at value[1], and
1020*4882a593Smuzhiyun * enumerated by value[0].
1021*4882a593Smuzhiyun * We expect each group of two ints to be one table entry,
1022*4882a593Smuzhiyun * and the last table entry is all 0.
1023*4882a593Smuzhiyun */
1024*4882a593Smuzhiyun n = value[0];
1025*4882a593Smuzhiyun if ((n % 2) || n < 4 ||
1026*4882a593Smuzhiyun n > ((ARRAY_SIZE(chip->tsl2772_device_lux) - 1) * 2))
1027*4882a593Smuzhiyun return -EINVAL;
1028*4882a593Smuzhiyun
1029*4882a593Smuzhiyun if ((value[(n - 1)] | value[n]) != 0)
1030*4882a593Smuzhiyun return -EINVAL;
1031*4882a593Smuzhiyun
1032*4882a593Smuzhiyun if (chip->tsl2772_chip_status == TSL2772_CHIP_WORKING) {
1033*4882a593Smuzhiyun ret = tsl2772_chip_off(indio_dev);
1034*4882a593Smuzhiyun if (ret < 0)
1035*4882a593Smuzhiyun return ret;
1036*4882a593Smuzhiyun }
1037*4882a593Smuzhiyun
1038*4882a593Smuzhiyun /* Zero out the table */
1039*4882a593Smuzhiyun memset(chip->tsl2772_device_lux, 0, sizeof(chip->tsl2772_device_lux));
1040*4882a593Smuzhiyun memcpy(chip->tsl2772_device_lux, &value[1], (value[0] * 4));
1041*4882a593Smuzhiyun
1042*4882a593Smuzhiyun ret = tsl2772_invoke_change(indio_dev);
1043*4882a593Smuzhiyun if (ret < 0)
1044*4882a593Smuzhiyun return ret;
1045*4882a593Smuzhiyun
1046*4882a593Smuzhiyun return len;
1047*4882a593Smuzhiyun }
1048*4882a593Smuzhiyun
in_proximity0_calibrate_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)1049*4882a593Smuzhiyun static ssize_t in_proximity0_calibrate_store(struct device *dev,
1050*4882a593Smuzhiyun struct device_attribute *attr,
1051*4882a593Smuzhiyun const char *buf, size_t len)
1052*4882a593Smuzhiyun {
1053*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1054*4882a593Smuzhiyun bool value;
1055*4882a593Smuzhiyun int ret;
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun if (kstrtobool(buf, &value) || !value)
1058*4882a593Smuzhiyun return -EINVAL;
1059*4882a593Smuzhiyun
1060*4882a593Smuzhiyun ret = tsl2772_prox_cal(indio_dev);
1061*4882a593Smuzhiyun if (ret < 0)
1062*4882a593Smuzhiyun return ret;
1063*4882a593Smuzhiyun
1064*4882a593Smuzhiyun ret = tsl2772_invoke_change(indio_dev);
1065*4882a593Smuzhiyun if (ret < 0)
1066*4882a593Smuzhiyun return ret;
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun return len;
1069*4882a593Smuzhiyun }
1070*4882a593Smuzhiyun
tsl2772_read_interrupt_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1071*4882a593Smuzhiyun static int tsl2772_read_interrupt_config(struct iio_dev *indio_dev,
1072*4882a593Smuzhiyun const struct iio_chan_spec *chan,
1073*4882a593Smuzhiyun enum iio_event_type type,
1074*4882a593Smuzhiyun enum iio_event_direction dir)
1075*4882a593Smuzhiyun {
1076*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
1077*4882a593Smuzhiyun
1078*4882a593Smuzhiyun if (chan->type == IIO_INTENSITY)
1079*4882a593Smuzhiyun return chip->settings.als_interrupt_en;
1080*4882a593Smuzhiyun else
1081*4882a593Smuzhiyun return chip->settings.prox_interrupt_en;
1082*4882a593Smuzhiyun }
1083*4882a593Smuzhiyun
tsl2772_write_interrupt_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int val)1084*4882a593Smuzhiyun static int tsl2772_write_interrupt_config(struct iio_dev *indio_dev,
1085*4882a593Smuzhiyun const struct iio_chan_spec *chan,
1086*4882a593Smuzhiyun enum iio_event_type type,
1087*4882a593Smuzhiyun enum iio_event_direction dir,
1088*4882a593Smuzhiyun int val)
1089*4882a593Smuzhiyun {
1090*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun if (chan->type == IIO_INTENSITY)
1093*4882a593Smuzhiyun chip->settings.als_interrupt_en = val ? true : false;
1094*4882a593Smuzhiyun else
1095*4882a593Smuzhiyun chip->settings.prox_interrupt_en = val ? true : false;
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun return tsl2772_invoke_change(indio_dev);
1098*4882a593Smuzhiyun }
1099*4882a593Smuzhiyun
tsl2772_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)1100*4882a593Smuzhiyun static int tsl2772_write_event_value(struct iio_dev *indio_dev,
1101*4882a593Smuzhiyun const struct iio_chan_spec *chan,
1102*4882a593Smuzhiyun enum iio_event_type type,
1103*4882a593Smuzhiyun enum iio_event_direction dir,
1104*4882a593Smuzhiyun enum iio_event_info info,
1105*4882a593Smuzhiyun int val, int val2)
1106*4882a593Smuzhiyun {
1107*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
1108*4882a593Smuzhiyun int ret = -EINVAL, count, persistence;
1109*4882a593Smuzhiyun u8 time;
1110*4882a593Smuzhiyun
1111*4882a593Smuzhiyun switch (info) {
1112*4882a593Smuzhiyun case IIO_EV_INFO_VALUE:
1113*4882a593Smuzhiyun if (chan->type == IIO_INTENSITY) {
1114*4882a593Smuzhiyun switch (dir) {
1115*4882a593Smuzhiyun case IIO_EV_DIR_RISING:
1116*4882a593Smuzhiyun chip->settings.als_thresh_high = val;
1117*4882a593Smuzhiyun ret = 0;
1118*4882a593Smuzhiyun break;
1119*4882a593Smuzhiyun case IIO_EV_DIR_FALLING:
1120*4882a593Smuzhiyun chip->settings.als_thresh_low = val;
1121*4882a593Smuzhiyun ret = 0;
1122*4882a593Smuzhiyun break;
1123*4882a593Smuzhiyun default:
1124*4882a593Smuzhiyun break;
1125*4882a593Smuzhiyun }
1126*4882a593Smuzhiyun } else {
1127*4882a593Smuzhiyun switch (dir) {
1128*4882a593Smuzhiyun case IIO_EV_DIR_RISING:
1129*4882a593Smuzhiyun chip->settings.prox_thres_high = val;
1130*4882a593Smuzhiyun ret = 0;
1131*4882a593Smuzhiyun break;
1132*4882a593Smuzhiyun case IIO_EV_DIR_FALLING:
1133*4882a593Smuzhiyun chip->settings.prox_thres_low = val;
1134*4882a593Smuzhiyun ret = 0;
1135*4882a593Smuzhiyun break;
1136*4882a593Smuzhiyun default:
1137*4882a593Smuzhiyun break;
1138*4882a593Smuzhiyun }
1139*4882a593Smuzhiyun }
1140*4882a593Smuzhiyun break;
1141*4882a593Smuzhiyun case IIO_EV_INFO_PERIOD:
1142*4882a593Smuzhiyun if (chan->type == IIO_INTENSITY)
1143*4882a593Smuzhiyun time = chip->settings.als_time;
1144*4882a593Smuzhiyun else
1145*4882a593Smuzhiyun time = chip->settings.prox_time;
1146*4882a593Smuzhiyun
1147*4882a593Smuzhiyun count = 256 - time;
1148*4882a593Smuzhiyun persistence = ((val * 1000000) + val2) /
1149*4882a593Smuzhiyun (count * tsl2772_int_time_avail[chip->id][3]);
1150*4882a593Smuzhiyun
1151*4882a593Smuzhiyun if (chan->type == IIO_INTENSITY) {
1152*4882a593Smuzhiyun /* ALS filter values are 1, 2, 3, 5, 10, 15, ..., 60 */
1153*4882a593Smuzhiyun if (persistence > 3)
1154*4882a593Smuzhiyun persistence = (persistence / 5) + 3;
1155*4882a593Smuzhiyun
1156*4882a593Smuzhiyun chip->settings.als_persistence = persistence;
1157*4882a593Smuzhiyun } else {
1158*4882a593Smuzhiyun chip->settings.prox_persistence = persistence;
1159*4882a593Smuzhiyun }
1160*4882a593Smuzhiyun
1161*4882a593Smuzhiyun ret = 0;
1162*4882a593Smuzhiyun break;
1163*4882a593Smuzhiyun default:
1164*4882a593Smuzhiyun break;
1165*4882a593Smuzhiyun }
1166*4882a593Smuzhiyun
1167*4882a593Smuzhiyun if (ret < 0)
1168*4882a593Smuzhiyun return ret;
1169*4882a593Smuzhiyun
1170*4882a593Smuzhiyun return tsl2772_invoke_change(indio_dev);
1171*4882a593Smuzhiyun }
1172*4882a593Smuzhiyun
tsl2772_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)1173*4882a593Smuzhiyun static int tsl2772_read_event_value(struct iio_dev *indio_dev,
1174*4882a593Smuzhiyun const struct iio_chan_spec *chan,
1175*4882a593Smuzhiyun enum iio_event_type type,
1176*4882a593Smuzhiyun enum iio_event_direction dir,
1177*4882a593Smuzhiyun enum iio_event_info info,
1178*4882a593Smuzhiyun int *val, int *val2)
1179*4882a593Smuzhiyun {
1180*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
1181*4882a593Smuzhiyun int filter_delay, persistence;
1182*4882a593Smuzhiyun u8 time;
1183*4882a593Smuzhiyun
1184*4882a593Smuzhiyun switch (info) {
1185*4882a593Smuzhiyun case IIO_EV_INFO_VALUE:
1186*4882a593Smuzhiyun if (chan->type == IIO_INTENSITY) {
1187*4882a593Smuzhiyun switch (dir) {
1188*4882a593Smuzhiyun case IIO_EV_DIR_RISING:
1189*4882a593Smuzhiyun *val = chip->settings.als_thresh_high;
1190*4882a593Smuzhiyun return IIO_VAL_INT;
1191*4882a593Smuzhiyun case IIO_EV_DIR_FALLING:
1192*4882a593Smuzhiyun *val = chip->settings.als_thresh_low;
1193*4882a593Smuzhiyun return IIO_VAL_INT;
1194*4882a593Smuzhiyun default:
1195*4882a593Smuzhiyun return -EINVAL;
1196*4882a593Smuzhiyun }
1197*4882a593Smuzhiyun } else {
1198*4882a593Smuzhiyun switch (dir) {
1199*4882a593Smuzhiyun case IIO_EV_DIR_RISING:
1200*4882a593Smuzhiyun *val = chip->settings.prox_thres_high;
1201*4882a593Smuzhiyun return IIO_VAL_INT;
1202*4882a593Smuzhiyun case IIO_EV_DIR_FALLING:
1203*4882a593Smuzhiyun *val = chip->settings.prox_thres_low;
1204*4882a593Smuzhiyun return IIO_VAL_INT;
1205*4882a593Smuzhiyun default:
1206*4882a593Smuzhiyun return -EINVAL;
1207*4882a593Smuzhiyun }
1208*4882a593Smuzhiyun }
1209*4882a593Smuzhiyun break;
1210*4882a593Smuzhiyun case IIO_EV_INFO_PERIOD:
1211*4882a593Smuzhiyun if (chan->type == IIO_INTENSITY) {
1212*4882a593Smuzhiyun time = chip->settings.als_time;
1213*4882a593Smuzhiyun persistence = chip->settings.als_persistence;
1214*4882a593Smuzhiyun
1215*4882a593Smuzhiyun /* ALS filter values are 1, 2, 3, 5, 10, 15, ..., 60 */
1216*4882a593Smuzhiyun if (persistence > 3)
1217*4882a593Smuzhiyun persistence = (persistence - 3) * 5;
1218*4882a593Smuzhiyun } else {
1219*4882a593Smuzhiyun time = chip->settings.prox_time;
1220*4882a593Smuzhiyun persistence = chip->settings.prox_persistence;
1221*4882a593Smuzhiyun }
1222*4882a593Smuzhiyun
1223*4882a593Smuzhiyun filter_delay = persistence * (256 - time) *
1224*4882a593Smuzhiyun tsl2772_int_time_avail[chip->id][3];
1225*4882a593Smuzhiyun
1226*4882a593Smuzhiyun *val = filter_delay / 1000000;
1227*4882a593Smuzhiyun *val2 = filter_delay % 1000000;
1228*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
1229*4882a593Smuzhiyun default:
1230*4882a593Smuzhiyun return -EINVAL;
1231*4882a593Smuzhiyun }
1232*4882a593Smuzhiyun }
1233*4882a593Smuzhiyun
tsl2772_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)1234*4882a593Smuzhiyun static int tsl2772_read_raw(struct iio_dev *indio_dev,
1235*4882a593Smuzhiyun struct iio_chan_spec const *chan,
1236*4882a593Smuzhiyun int *val,
1237*4882a593Smuzhiyun int *val2,
1238*4882a593Smuzhiyun long mask)
1239*4882a593Smuzhiyun {
1240*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
1241*4882a593Smuzhiyun
1242*4882a593Smuzhiyun switch (mask) {
1243*4882a593Smuzhiyun case IIO_CHAN_INFO_PROCESSED:
1244*4882a593Smuzhiyun switch (chan->type) {
1245*4882a593Smuzhiyun case IIO_LIGHT:
1246*4882a593Smuzhiyun tsl2772_get_lux(indio_dev);
1247*4882a593Smuzhiyun *val = chip->als_cur_info.lux;
1248*4882a593Smuzhiyun return IIO_VAL_INT;
1249*4882a593Smuzhiyun default:
1250*4882a593Smuzhiyun return -EINVAL;
1251*4882a593Smuzhiyun }
1252*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
1253*4882a593Smuzhiyun switch (chan->type) {
1254*4882a593Smuzhiyun case IIO_INTENSITY:
1255*4882a593Smuzhiyun tsl2772_get_lux(indio_dev);
1256*4882a593Smuzhiyun if (chan->channel == 0)
1257*4882a593Smuzhiyun *val = chip->als_cur_info.als_ch0;
1258*4882a593Smuzhiyun else
1259*4882a593Smuzhiyun *val = chip->als_cur_info.als_ch1;
1260*4882a593Smuzhiyun return IIO_VAL_INT;
1261*4882a593Smuzhiyun case IIO_PROXIMITY:
1262*4882a593Smuzhiyun tsl2772_get_prox(indio_dev);
1263*4882a593Smuzhiyun *val = chip->prox_data;
1264*4882a593Smuzhiyun return IIO_VAL_INT;
1265*4882a593Smuzhiyun default:
1266*4882a593Smuzhiyun return -EINVAL;
1267*4882a593Smuzhiyun }
1268*4882a593Smuzhiyun break;
1269*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBSCALE:
1270*4882a593Smuzhiyun if (chan->type == IIO_LIGHT)
1271*4882a593Smuzhiyun *val = tsl2772_als_gain[chip->settings.als_gain];
1272*4882a593Smuzhiyun else
1273*4882a593Smuzhiyun *val = tsl2772_prox_gain[chip->settings.prox_gain];
1274*4882a593Smuzhiyun return IIO_VAL_INT;
1275*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBBIAS:
1276*4882a593Smuzhiyun *val = chip->settings.als_gain_trim;
1277*4882a593Smuzhiyun return IIO_VAL_INT;
1278*4882a593Smuzhiyun case IIO_CHAN_INFO_INT_TIME:
1279*4882a593Smuzhiyun *val = 0;
1280*4882a593Smuzhiyun *val2 = (256 - chip->settings.als_time) *
1281*4882a593Smuzhiyun tsl2772_int_time_avail[chip->id][3];
1282*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
1283*4882a593Smuzhiyun default:
1284*4882a593Smuzhiyun return -EINVAL;
1285*4882a593Smuzhiyun }
1286*4882a593Smuzhiyun }
1287*4882a593Smuzhiyun
tsl2772_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)1288*4882a593Smuzhiyun static int tsl2772_write_raw(struct iio_dev *indio_dev,
1289*4882a593Smuzhiyun struct iio_chan_spec const *chan,
1290*4882a593Smuzhiyun int val,
1291*4882a593Smuzhiyun int val2,
1292*4882a593Smuzhiyun long mask)
1293*4882a593Smuzhiyun {
1294*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
1295*4882a593Smuzhiyun
1296*4882a593Smuzhiyun switch (mask) {
1297*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBSCALE:
1298*4882a593Smuzhiyun if (chan->type == IIO_INTENSITY) {
1299*4882a593Smuzhiyun switch (val) {
1300*4882a593Smuzhiyun case 1:
1301*4882a593Smuzhiyun chip->settings.als_gain = 0;
1302*4882a593Smuzhiyun break;
1303*4882a593Smuzhiyun case 8:
1304*4882a593Smuzhiyun chip->settings.als_gain = 1;
1305*4882a593Smuzhiyun break;
1306*4882a593Smuzhiyun case 16:
1307*4882a593Smuzhiyun chip->settings.als_gain = 2;
1308*4882a593Smuzhiyun break;
1309*4882a593Smuzhiyun case 120:
1310*4882a593Smuzhiyun chip->settings.als_gain = 3;
1311*4882a593Smuzhiyun break;
1312*4882a593Smuzhiyun default:
1313*4882a593Smuzhiyun return -EINVAL;
1314*4882a593Smuzhiyun }
1315*4882a593Smuzhiyun } else {
1316*4882a593Smuzhiyun switch (val) {
1317*4882a593Smuzhiyun case 1:
1318*4882a593Smuzhiyun chip->settings.prox_gain = 0;
1319*4882a593Smuzhiyun break;
1320*4882a593Smuzhiyun case 2:
1321*4882a593Smuzhiyun chip->settings.prox_gain = 1;
1322*4882a593Smuzhiyun break;
1323*4882a593Smuzhiyun case 4:
1324*4882a593Smuzhiyun chip->settings.prox_gain = 2;
1325*4882a593Smuzhiyun break;
1326*4882a593Smuzhiyun case 8:
1327*4882a593Smuzhiyun chip->settings.prox_gain = 3;
1328*4882a593Smuzhiyun break;
1329*4882a593Smuzhiyun default:
1330*4882a593Smuzhiyun return -EINVAL;
1331*4882a593Smuzhiyun }
1332*4882a593Smuzhiyun }
1333*4882a593Smuzhiyun break;
1334*4882a593Smuzhiyun case IIO_CHAN_INFO_CALIBBIAS:
1335*4882a593Smuzhiyun if (val < TSL2772_ALS_GAIN_TRIM_MIN ||
1336*4882a593Smuzhiyun val > TSL2772_ALS_GAIN_TRIM_MAX)
1337*4882a593Smuzhiyun return -EINVAL;
1338*4882a593Smuzhiyun
1339*4882a593Smuzhiyun chip->settings.als_gain_trim = val;
1340*4882a593Smuzhiyun break;
1341*4882a593Smuzhiyun case IIO_CHAN_INFO_INT_TIME:
1342*4882a593Smuzhiyun if (val != 0 || val2 < tsl2772_int_time_avail[chip->id][1] ||
1343*4882a593Smuzhiyun val2 > tsl2772_int_time_avail[chip->id][5])
1344*4882a593Smuzhiyun return -EINVAL;
1345*4882a593Smuzhiyun
1346*4882a593Smuzhiyun chip->settings.als_time = 256 -
1347*4882a593Smuzhiyun (val2 / tsl2772_int_time_avail[chip->id][3]);
1348*4882a593Smuzhiyun break;
1349*4882a593Smuzhiyun default:
1350*4882a593Smuzhiyun return -EINVAL;
1351*4882a593Smuzhiyun }
1352*4882a593Smuzhiyun
1353*4882a593Smuzhiyun return tsl2772_invoke_change(indio_dev);
1354*4882a593Smuzhiyun }
1355*4882a593Smuzhiyun
1356*4882a593Smuzhiyun static DEVICE_ATTR_RW(in_illuminance0_target_input);
1357*4882a593Smuzhiyun
1358*4882a593Smuzhiyun static DEVICE_ATTR_WO(in_illuminance0_calibrate);
1359*4882a593Smuzhiyun
1360*4882a593Smuzhiyun static DEVICE_ATTR_WO(in_proximity0_calibrate);
1361*4882a593Smuzhiyun
1362*4882a593Smuzhiyun static DEVICE_ATTR_RW(in_illuminance0_lux_table);
1363*4882a593Smuzhiyun
1364*4882a593Smuzhiyun /* Use the default register values to identify the Taos device */
tsl2772_device_id_verif(int id,int target)1365*4882a593Smuzhiyun static int tsl2772_device_id_verif(int id, int target)
1366*4882a593Smuzhiyun {
1367*4882a593Smuzhiyun switch (target) {
1368*4882a593Smuzhiyun case tsl2571:
1369*4882a593Smuzhiyun case tsl2671:
1370*4882a593Smuzhiyun case tsl2771:
1371*4882a593Smuzhiyun return (id & 0xf0) == TRITON_ID;
1372*4882a593Smuzhiyun case tmd2671:
1373*4882a593Smuzhiyun case tmd2771:
1374*4882a593Smuzhiyun return (id & 0xf0) == HALIBUT_ID;
1375*4882a593Smuzhiyun case tsl2572:
1376*4882a593Smuzhiyun case tsl2672:
1377*4882a593Smuzhiyun case tmd2672:
1378*4882a593Smuzhiyun case tsl2772:
1379*4882a593Smuzhiyun case tmd2772:
1380*4882a593Smuzhiyun case apds9930:
1381*4882a593Smuzhiyun return (id & 0xf0) == SWORDFISH_ID;
1382*4882a593Smuzhiyun }
1383*4882a593Smuzhiyun
1384*4882a593Smuzhiyun return -EINVAL;
1385*4882a593Smuzhiyun }
1386*4882a593Smuzhiyun
tsl2772_event_handler(int irq,void * private)1387*4882a593Smuzhiyun static irqreturn_t tsl2772_event_handler(int irq, void *private)
1388*4882a593Smuzhiyun {
1389*4882a593Smuzhiyun struct iio_dev *indio_dev = private;
1390*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
1391*4882a593Smuzhiyun s64 timestamp = iio_get_time_ns(indio_dev);
1392*4882a593Smuzhiyun int ret;
1393*4882a593Smuzhiyun
1394*4882a593Smuzhiyun ret = tsl2772_read_status(chip);
1395*4882a593Smuzhiyun if (ret < 0)
1396*4882a593Smuzhiyun return IRQ_HANDLED;
1397*4882a593Smuzhiyun
1398*4882a593Smuzhiyun /* What type of interrupt do we need to process */
1399*4882a593Smuzhiyun if (ret & TSL2772_STA_PRX_INTR) {
1400*4882a593Smuzhiyun iio_push_event(indio_dev,
1401*4882a593Smuzhiyun IIO_UNMOD_EVENT_CODE(IIO_PROXIMITY,
1402*4882a593Smuzhiyun 0,
1403*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
1404*4882a593Smuzhiyun IIO_EV_DIR_EITHER),
1405*4882a593Smuzhiyun timestamp);
1406*4882a593Smuzhiyun }
1407*4882a593Smuzhiyun
1408*4882a593Smuzhiyun if (ret & TSL2772_STA_ALS_INTR) {
1409*4882a593Smuzhiyun iio_push_event(indio_dev,
1410*4882a593Smuzhiyun IIO_UNMOD_EVENT_CODE(IIO_LIGHT,
1411*4882a593Smuzhiyun 0,
1412*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
1413*4882a593Smuzhiyun IIO_EV_DIR_EITHER),
1414*4882a593Smuzhiyun timestamp);
1415*4882a593Smuzhiyun }
1416*4882a593Smuzhiyun
1417*4882a593Smuzhiyun ret = i2c_smbus_write_byte(chip->client,
1418*4882a593Smuzhiyun TSL2772_CMD_REG | TSL2772_CMD_SPL_FN |
1419*4882a593Smuzhiyun TSL2772_CMD_PROXALS_INT_CLR);
1420*4882a593Smuzhiyun if (ret < 0)
1421*4882a593Smuzhiyun dev_err(&chip->client->dev,
1422*4882a593Smuzhiyun "%s: failed to clear interrupt status: %d\n",
1423*4882a593Smuzhiyun __func__, ret);
1424*4882a593Smuzhiyun
1425*4882a593Smuzhiyun return IRQ_HANDLED;
1426*4882a593Smuzhiyun }
1427*4882a593Smuzhiyun
1428*4882a593Smuzhiyun static struct attribute *tsl2772_ALS_device_attrs[] = {
1429*4882a593Smuzhiyun &dev_attr_in_illuminance0_target_input.attr,
1430*4882a593Smuzhiyun &dev_attr_in_illuminance0_calibrate.attr,
1431*4882a593Smuzhiyun &dev_attr_in_illuminance0_lux_table.attr,
1432*4882a593Smuzhiyun NULL
1433*4882a593Smuzhiyun };
1434*4882a593Smuzhiyun
1435*4882a593Smuzhiyun static struct attribute *tsl2772_PRX_device_attrs[] = {
1436*4882a593Smuzhiyun &dev_attr_in_proximity0_calibrate.attr,
1437*4882a593Smuzhiyun NULL
1438*4882a593Smuzhiyun };
1439*4882a593Smuzhiyun
1440*4882a593Smuzhiyun static struct attribute *tsl2772_ALSPRX_device_attrs[] = {
1441*4882a593Smuzhiyun &dev_attr_in_illuminance0_target_input.attr,
1442*4882a593Smuzhiyun &dev_attr_in_illuminance0_calibrate.attr,
1443*4882a593Smuzhiyun &dev_attr_in_illuminance0_lux_table.attr,
1444*4882a593Smuzhiyun NULL
1445*4882a593Smuzhiyun };
1446*4882a593Smuzhiyun
1447*4882a593Smuzhiyun static struct attribute *tsl2772_PRX2_device_attrs[] = {
1448*4882a593Smuzhiyun &dev_attr_in_proximity0_calibrate.attr,
1449*4882a593Smuzhiyun NULL
1450*4882a593Smuzhiyun };
1451*4882a593Smuzhiyun
1452*4882a593Smuzhiyun static struct attribute *tsl2772_ALSPRX2_device_attrs[] = {
1453*4882a593Smuzhiyun &dev_attr_in_illuminance0_target_input.attr,
1454*4882a593Smuzhiyun &dev_attr_in_illuminance0_calibrate.attr,
1455*4882a593Smuzhiyun &dev_attr_in_illuminance0_lux_table.attr,
1456*4882a593Smuzhiyun &dev_attr_in_proximity0_calibrate.attr,
1457*4882a593Smuzhiyun NULL
1458*4882a593Smuzhiyun };
1459*4882a593Smuzhiyun
1460*4882a593Smuzhiyun static const struct attribute_group tsl2772_device_attr_group_tbl[] = {
1461*4882a593Smuzhiyun [ALS] = {
1462*4882a593Smuzhiyun .attrs = tsl2772_ALS_device_attrs,
1463*4882a593Smuzhiyun },
1464*4882a593Smuzhiyun [PRX] = {
1465*4882a593Smuzhiyun .attrs = tsl2772_PRX_device_attrs,
1466*4882a593Smuzhiyun },
1467*4882a593Smuzhiyun [ALSPRX] = {
1468*4882a593Smuzhiyun .attrs = tsl2772_ALSPRX_device_attrs,
1469*4882a593Smuzhiyun },
1470*4882a593Smuzhiyun [PRX2] = {
1471*4882a593Smuzhiyun .attrs = tsl2772_PRX2_device_attrs,
1472*4882a593Smuzhiyun },
1473*4882a593Smuzhiyun [ALSPRX2] = {
1474*4882a593Smuzhiyun .attrs = tsl2772_ALSPRX2_device_attrs,
1475*4882a593Smuzhiyun },
1476*4882a593Smuzhiyun };
1477*4882a593Smuzhiyun
1478*4882a593Smuzhiyun #define TSL2772_DEVICE_INFO(type)[type] = \
1479*4882a593Smuzhiyun { \
1480*4882a593Smuzhiyun .attrs = &tsl2772_device_attr_group_tbl[type], \
1481*4882a593Smuzhiyun .read_raw = &tsl2772_read_raw, \
1482*4882a593Smuzhiyun .read_avail = &tsl2772_read_avail, \
1483*4882a593Smuzhiyun .write_raw = &tsl2772_write_raw, \
1484*4882a593Smuzhiyun .read_event_value = &tsl2772_read_event_value, \
1485*4882a593Smuzhiyun .write_event_value = &tsl2772_write_event_value, \
1486*4882a593Smuzhiyun .read_event_config = &tsl2772_read_interrupt_config, \
1487*4882a593Smuzhiyun .write_event_config = &tsl2772_write_interrupt_config, \
1488*4882a593Smuzhiyun }
1489*4882a593Smuzhiyun
1490*4882a593Smuzhiyun static const struct iio_info tsl2772_device_info[] = {
1491*4882a593Smuzhiyun TSL2772_DEVICE_INFO(ALS),
1492*4882a593Smuzhiyun TSL2772_DEVICE_INFO(PRX),
1493*4882a593Smuzhiyun TSL2772_DEVICE_INFO(ALSPRX),
1494*4882a593Smuzhiyun TSL2772_DEVICE_INFO(PRX2),
1495*4882a593Smuzhiyun TSL2772_DEVICE_INFO(ALSPRX2),
1496*4882a593Smuzhiyun };
1497*4882a593Smuzhiyun
1498*4882a593Smuzhiyun static const struct iio_event_spec tsl2772_events[] = {
1499*4882a593Smuzhiyun {
1500*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
1501*4882a593Smuzhiyun .dir = IIO_EV_DIR_RISING,
1502*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_VALUE),
1503*4882a593Smuzhiyun }, {
1504*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
1505*4882a593Smuzhiyun .dir = IIO_EV_DIR_FALLING,
1506*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_VALUE),
1507*4882a593Smuzhiyun }, {
1508*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
1509*4882a593Smuzhiyun .dir = IIO_EV_DIR_EITHER,
1510*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_PERIOD) |
1511*4882a593Smuzhiyun BIT(IIO_EV_INFO_ENABLE),
1512*4882a593Smuzhiyun },
1513*4882a593Smuzhiyun };
1514*4882a593Smuzhiyun
1515*4882a593Smuzhiyun static const struct tsl2772_chip_info tsl2772_chip_info_tbl[] = {
1516*4882a593Smuzhiyun [ALS] = {
1517*4882a593Smuzhiyun .channel_with_events = {
1518*4882a593Smuzhiyun {
1519*4882a593Smuzhiyun .type = IIO_LIGHT,
1520*4882a593Smuzhiyun .indexed = 1,
1521*4882a593Smuzhiyun .channel = 0,
1522*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
1523*4882a593Smuzhiyun }, {
1524*4882a593Smuzhiyun .type = IIO_INTENSITY,
1525*4882a593Smuzhiyun .indexed = 1,
1526*4882a593Smuzhiyun .channel = 0,
1527*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1528*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_INT_TIME) |
1529*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE) |
1530*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBBIAS),
1531*4882a593Smuzhiyun .info_mask_separate_available =
1532*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_INT_TIME) |
1533*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE),
1534*4882a593Smuzhiyun .event_spec = tsl2772_events,
1535*4882a593Smuzhiyun .num_event_specs = ARRAY_SIZE(tsl2772_events),
1536*4882a593Smuzhiyun }, {
1537*4882a593Smuzhiyun .type = IIO_INTENSITY,
1538*4882a593Smuzhiyun .indexed = 1,
1539*4882a593Smuzhiyun .channel = 1,
1540*4882a593Smuzhiyun },
1541*4882a593Smuzhiyun },
1542*4882a593Smuzhiyun .channel_without_events = {
1543*4882a593Smuzhiyun {
1544*4882a593Smuzhiyun .type = IIO_LIGHT,
1545*4882a593Smuzhiyun .indexed = 1,
1546*4882a593Smuzhiyun .channel = 0,
1547*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
1548*4882a593Smuzhiyun }, {
1549*4882a593Smuzhiyun .type = IIO_INTENSITY,
1550*4882a593Smuzhiyun .indexed = 1,
1551*4882a593Smuzhiyun .channel = 0,
1552*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1553*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_INT_TIME) |
1554*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE) |
1555*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBBIAS),
1556*4882a593Smuzhiyun .info_mask_separate_available =
1557*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_INT_TIME) |
1558*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE),
1559*4882a593Smuzhiyun }, {
1560*4882a593Smuzhiyun .type = IIO_INTENSITY,
1561*4882a593Smuzhiyun .indexed = 1,
1562*4882a593Smuzhiyun .channel = 1,
1563*4882a593Smuzhiyun },
1564*4882a593Smuzhiyun },
1565*4882a593Smuzhiyun .chan_table_elements = 3,
1566*4882a593Smuzhiyun .info = &tsl2772_device_info[ALS],
1567*4882a593Smuzhiyun },
1568*4882a593Smuzhiyun [PRX] = {
1569*4882a593Smuzhiyun .channel_with_events = {
1570*4882a593Smuzhiyun {
1571*4882a593Smuzhiyun .type = IIO_PROXIMITY,
1572*4882a593Smuzhiyun .indexed = 1,
1573*4882a593Smuzhiyun .channel = 0,
1574*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
1575*4882a593Smuzhiyun .event_spec = tsl2772_events,
1576*4882a593Smuzhiyun .num_event_specs = ARRAY_SIZE(tsl2772_events),
1577*4882a593Smuzhiyun },
1578*4882a593Smuzhiyun },
1579*4882a593Smuzhiyun .channel_without_events = {
1580*4882a593Smuzhiyun {
1581*4882a593Smuzhiyun .type = IIO_PROXIMITY,
1582*4882a593Smuzhiyun .indexed = 1,
1583*4882a593Smuzhiyun .channel = 0,
1584*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
1585*4882a593Smuzhiyun },
1586*4882a593Smuzhiyun },
1587*4882a593Smuzhiyun .chan_table_elements = 1,
1588*4882a593Smuzhiyun .info = &tsl2772_device_info[PRX],
1589*4882a593Smuzhiyun },
1590*4882a593Smuzhiyun [ALSPRX] = {
1591*4882a593Smuzhiyun .channel_with_events = {
1592*4882a593Smuzhiyun {
1593*4882a593Smuzhiyun .type = IIO_LIGHT,
1594*4882a593Smuzhiyun .indexed = 1,
1595*4882a593Smuzhiyun .channel = 0,
1596*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
1597*4882a593Smuzhiyun }, {
1598*4882a593Smuzhiyun .type = IIO_INTENSITY,
1599*4882a593Smuzhiyun .indexed = 1,
1600*4882a593Smuzhiyun .channel = 0,
1601*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1602*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_INT_TIME) |
1603*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE) |
1604*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBBIAS),
1605*4882a593Smuzhiyun .info_mask_separate_available =
1606*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_INT_TIME) |
1607*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE),
1608*4882a593Smuzhiyun .event_spec = tsl2772_events,
1609*4882a593Smuzhiyun .num_event_specs = ARRAY_SIZE(tsl2772_events),
1610*4882a593Smuzhiyun }, {
1611*4882a593Smuzhiyun .type = IIO_INTENSITY,
1612*4882a593Smuzhiyun .indexed = 1,
1613*4882a593Smuzhiyun .channel = 1,
1614*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
1615*4882a593Smuzhiyun }, {
1616*4882a593Smuzhiyun .type = IIO_PROXIMITY,
1617*4882a593Smuzhiyun .indexed = 1,
1618*4882a593Smuzhiyun .channel = 0,
1619*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
1620*4882a593Smuzhiyun .event_spec = tsl2772_events,
1621*4882a593Smuzhiyun .num_event_specs = ARRAY_SIZE(tsl2772_events),
1622*4882a593Smuzhiyun },
1623*4882a593Smuzhiyun },
1624*4882a593Smuzhiyun .channel_without_events = {
1625*4882a593Smuzhiyun {
1626*4882a593Smuzhiyun .type = IIO_LIGHT,
1627*4882a593Smuzhiyun .indexed = 1,
1628*4882a593Smuzhiyun .channel = 0,
1629*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
1630*4882a593Smuzhiyun }, {
1631*4882a593Smuzhiyun .type = IIO_INTENSITY,
1632*4882a593Smuzhiyun .indexed = 1,
1633*4882a593Smuzhiyun .channel = 0,
1634*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1635*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_INT_TIME) |
1636*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE) |
1637*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBBIAS),
1638*4882a593Smuzhiyun .info_mask_separate_available =
1639*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_INT_TIME) |
1640*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE),
1641*4882a593Smuzhiyun }, {
1642*4882a593Smuzhiyun .type = IIO_INTENSITY,
1643*4882a593Smuzhiyun .indexed = 1,
1644*4882a593Smuzhiyun .channel = 1,
1645*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
1646*4882a593Smuzhiyun }, {
1647*4882a593Smuzhiyun .type = IIO_PROXIMITY,
1648*4882a593Smuzhiyun .indexed = 1,
1649*4882a593Smuzhiyun .channel = 0,
1650*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
1651*4882a593Smuzhiyun },
1652*4882a593Smuzhiyun },
1653*4882a593Smuzhiyun .chan_table_elements = 4,
1654*4882a593Smuzhiyun .info = &tsl2772_device_info[ALSPRX],
1655*4882a593Smuzhiyun },
1656*4882a593Smuzhiyun [PRX2] = {
1657*4882a593Smuzhiyun .channel_with_events = {
1658*4882a593Smuzhiyun {
1659*4882a593Smuzhiyun .type = IIO_PROXIMITY,
1660*4882a593Smuzhiyun .indexed = 1,
1661*4882a593Smuzhiyun .channel = 0,
1662*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1663*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE),
1664*4882a593Smuzhiyun .info_mask_separate_available =
1665*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE),
1666*4882a593Smuzhiyun .event_spec = tsl2772_events,
1667*4882a593Smuzhiyun .num_event_specs = ARRAY_SIZE(tsl2772_events),
1668*4882a593Smuzhiyun },
1669*4882a593Smuzhiyun },
1670*4882a593Smuzhiyun .channel_without_events = {
1671*4882a593Smuzhiyun {
1672*4882a593Smuzhiyun .type = IIO_PROXIMITY,
1673*4882a593Smuzhiyun .indexed = 1,
1674*4882a593Smuzhiyun .channel = 0,
1675*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1676*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE),
1677*4882a593Smuzhiyun .info_mask_separate_available =
1678*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE),
1679*4882a593Smuzhiyun },
1680*4882a593Smuzhiyun },
1681*4882a593Smuzhiyun .chan_table_elements = 1,
1682*4882a593Smuzhiyun .info = &tsl2772_device_info[PRX2],
1683*4882a593Smuzhiyun },
1684*4882a593Smuzhiyun [ALSPRX2] = {
1685*4882a593Smuzhiyun .channel_with_events = {
1686*4882a593Smuzhiyun {
1687*4882a593Smuzhiyun .type = IIO_LIGHT,
1688*4882a593Smuzhiyun .indexed = 1,
1689*4882a593Smuzhiyun .channel = 0,
1690*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
1691*4882a593Smuzhiyun }, {
1692*4882a593Smuzhiyun .type = IIO_INTENSITY,
1693*4882a593Smuzhiyun .indexed = 1,
1694*4882a593Smuzhiyun .channel = 0,
1695*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1696*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_INT_TIME) |
1697*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE) |
1698*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBBIAS),
1699*4882a593Smuzhiyun .info_mask_separate_available =
1700*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_INT_TIME) |
1701*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE),
1702*4882a593Smuzhiyun .event_spec = tsl2772_events,
1703*4882a593Smuzhiyun .num_event_specs = ARRAY_SIZE(tsl2772_events),
1704*4882a593Smuzhiyun }, {
1705*4882a593Smuzhiyun .type = IIO_INTENSITY,
1706*4882a593Smuzhiyun .indexed = 1,
1707*4882a593Smuzhiyun .channel = 1,
1708*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
1709*4882a593Smuzhiyun }, {
1710*4882a593Smuzhiyun .type = IIO_PROXIMITY,
1711*4882a593Smuzhiyun .indexed = 1,
1712*4882a593Smuzhiyun .channel = 0,
1713*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1714*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE),
1715*4882a593Smuzhiyun .info_mask_separate_available =
1716*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE),
1717*4882a593Smuzhiyun .event_spec = tsl2772_events,
1718*4882a593Smuzhiyun .num_event_specs = ARRAY_SIZE(tsl2772_events),
1719*4882a593Smuzhiyun },
1720*4882a593Smuzhiyun },
1721*4882a593Smuzhiyun .channel_without_events = {
1722*4882a593Smuzhiyun {
1723*4882a593Smuzhiyun .type = IIO_LIGHT,
1724*4882a593Smuzhiyun .indexed = 1,
1725*4882a593Smuzhiyun .channel = 0,
1726*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
1727*4882a593Smuzhiyun }, {
1728*4882a593Smuzhiyun .type = IIO_INTENSITY,
1729*4882a593Smuzhiyun .indexed = 1,
1730*4882a593Smuzhiyun .channel = 0,
1731*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1732*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_INT_TIME) |
1733*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE) |
1734*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBBIAS),
1735*4882a593Smuzhiyun .info_mask_separate_available =
1736*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_INT_TIME) |
1737*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE),
1738*4882a593Smuzhiyun }, {
1739*4882a593Smuzhiyun .type = IIO_INTENSITY,
1740*4882a593Smuzhiyun .indexed = 1,
1741*4882a593Smuzhiyun .channel = 1,
1742*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
1743*4882a593Smuzhiyun }, {
1744*4882a593Smuzhiyun .type = IIO_PROXIMITY,
1745*4882a593Smuzhiyun .indexed = 1,
1746*4882a593Smuzhiyun .channel = 0,
1747*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
1748*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE),
1749*4882a593Smuzhiyun .info_mask_separate_available =
1750*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_CALIBSCALE),
1751*4882a593Smuzhiyun },
1752*4882a593Smuzhiyun },
1753*4882a593Smuzhiyun .chan_table_elements = 4,
1754*4882a593Smuzhiyun .info = &tsl2772_device_info[ALSPRX2],
1755*4882a593Smuzhiyun },
1756*4882a593Smuzhiyun };
1757*4882a593Smuzhiyun
tsl2772_probe(struct i2c_client * clientp,const struct i2c_device_id * id)1758*4882a593Smuzhiyun static int tsl2772_probe(struct i2c_client *clientp,
1759*4882a593Smuzhiyun const struct i2c_device_id *id)
1760*4882a593Smuzhiyun {
1761*4882a593Smuzhiyun struct iio_dev *indio_dev;
1762*4882a593Smuzhiyun struct tsl2772_chip *chip;
1763*4882a593Smuzhiyun int ret;
1764*4882a593Smuzhiyun
1765*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&clientp->dev, sizeof(*chip));
1766*4882a593Smuzhiyun if (!indio_dev)
1767*4882a593Smuzhiyun return -ENOMEM;
1768*4882a593Smuzhiyun
1769*4882a593Smuzhiyun chip = iio_priv(indio_dev);
1770*4882a593Smuzhiyun chip->client = clientp;
1771*4882a593Smuzhiyun i2c_set_clientdata(clientp, indio_dev);
1772*4882a593Smuzhiyun
1773*4882a593Smuzhiyun chip->supplies[TSL2772_SUPPLY_VDD].supply = "vdd";
1774*4882a593Smuzhiyun chip->supplies[TSL2772_SUPPLY_VDDIO].supply = "vddio";
1775*4882a593Smuzhiyun
1776*4882a593Smuzhiyun ret = devm_regulator_bulk_get(&clientp->dev,
1777*4882a593Smuzhiyun ARRAY_SIZE(chip->supplies),
1778*4882a593Smuzhiyun chip->supplies);
1779*4882a593Smuzhiyun if (ret < 0)
1780*4882a593Smuzhiyun return dev_err_probe(&clientp->dev, ret, "Failed to get regulators\n");
1781*4882a593Smuzhiyun
1782*4882a593Smuzhiyun ret = regulator_bulk_enable(ARRAY_SIZE(chip->supplies), chip->supplies);
1783*4882a593Smuzhiyun if (ret < 0) {
1784*4882a593Smuzhiyun dev_err(&clientp->dev, "Failed to enable regulators: %d\n",
1785*4882a593Smuzhiyun ret);
1786*4882a593Smuzhiyun return ret;
1787*4882a593Smuzhiyun }
1788*4882a593Smuzhiyun
1789*4882a593Smuzhiyun ret = devm_add_action_or_reset(&clientp->dev,
1790*4882a593Smuzhiyun tsl2772_disable_regulators_action,
1791*4882a593Smuzhiyun chip);
1792*4882a593Smuzhiyun if (ret < 0) {
1793*4882a593Smuzhiyun dev_err(&clientp->dev, "Failed to setup regulator cleanup action %d\n",
1794*4882a593Smuzhiyun ret);
1795*4882a593Smuzhiyun return ret;
1796*4882a593Smuzhiyun }
1797*4882a593Smuzhiyun
1798*4882a593Smuzhiyun usleep_range(TSL2772_BOOT_MIN_SLEEP_TIME, TSL2772_BOOT_MAX_SLEEP_TIME);
1799*4882a593Smuzhiyun
1800*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(chip->client,
1801*4882a593Smuzhiyun TSL2772_CMD_REG | TSL2772_CHIPID);
1802*4882a593Smuzhiyun if (ret < 0)
1803*4882a593Smuzhiyun return ret;
1804*4882a593Smuzhiyun
1805*4882a593Smuzhiyun if (tsl2772_device_id_verif(ret, id->driver_data) <= 0) {
1806*4882a593Smuzhiyun dev_info(&chip->client->dev,
1807*4882a593Smuzhiyun "%s: i2c device found does not match expected id\n",
1808*4882a593Smuzhiyun __func__);
1809*4882a593Smuzhiyun return -EINVAL;
1810*4882a593Smuzhiyun }
1811*4882a593Smuzhiyun
1812*4882a593Smuzhiyun ret = i2c_smbus_write_byte(clientp, TSL2772_CMD_REG | TSL2772_CNTRL);
1813*4882a593Smuzhiyun if (ret < 0) {
1814*4882a593Smuzhiyun dev_err(&clientp->dev,
1815*4882a593Smuzhiyun "%s: Failed to write to CMD register: %d\n",
1816*4882a593Smuzhiyun __func__, ret);
1817*4882a593Smuzhiyun return ret;
1818*4882a593Smuzhiyun }
1819*4882a593Smuzhiyun
1820*4882a593Smuzhiyun mutex_init(&chip->als_mutex);
1821*4882a593Smuzhiyun mutex_init(&chip->prox_mutex);
1822*4882a593Smuzhiyun
1823*4882a593Smuzhiyun chip->tsl2772_chip_status = TSL2772_CHIP_UNKNOWN;
1824*4882a593Smuzhiyun chip->pdata = dev_get_platdata(&clientp->dev);
1825*4882a593Smuzhiyun chip->id = id->driver_data;
1826*4882a593Smuzhiyun chip->chip_info =
1827*4882a593Smuzhiyun &tsl2772_chip_info_tbl[device_channel_config[id->driver_data]];
1828*4882a593Smuzhiyun
1829*4882a593Smuzhiyun indio_dev->info = chip->chip_info->info;
1830*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
1831*4882a593Smuzhiyun indio_dev->name = chip->client->name;
1832*4882a593Smuzhiyun indio_dev->num_channels = chip->chip_info->chan_table_elements;
1833*4882a593Smuzhiyun
1834*4882a593Smuzhiyun if (clientp->irq) {
1835*4882a593Smuzhiyun indio_dev->channels = chip->chip_info->channel_with_events;
1836*4882a593Smuzhiyun
1837*4882a593Smuzhiyun ret = devm_request_threaded_irq(&clientp->dev, clientp->irq,
1838*4882a593Smuzhiyun NULL,
1839*4882a593Smuzhiyun &tsl2772_event_handler,
1840*4882a593Smuzhiyun IRQF_TRIGGER_FALLING |
1841*4882a593Smuzhiyun IRQF_ONESHOT,
1842*4882a593Smuzhiyun "TSL2772_event",
1843*4882a593Smuzhiyun indio_dev);
1844*4882a593Smuzhiyun if (ret) {
1845*4882a593Smuzhiyun dev_err(&clientp->dev,
1846*4882a593Smuzhiyun "%s: irq request failed\n", __func__);
1847*4882a593Smuzhiyun return ret;
1848*4882a593Smuzhiyun }
1849*4882a593Smuzhiyun } else {
1850*4882a593Smuzhiyun indio_dev->channels = chip->chip_info->channel_without_events;
1851*4882a593Smuzhiyun }
1852*4882a593Smuzhiyun
1853*4882a593Smuzhiyun tsl2772_defaults(chip);
1854*4882a593Smuzhiyun ret = tsl2772_chip_on(indio_dev);
1855*4882a593Smuzhiyun if (ret < 0)
1856*4882a593Smuzhiyun return ret;
1857*4882a593Smuzhiyun
1858*4882a593Smuzhiyun ret = devm_add_action_or_reset(&clientp->dev,
1859*4882a593Smuzhiyun tsl2772_chip_off_action,
1860*4882a593Smuzhiyun indio_dev);
1861*4882a593Smuzhiyun if (ret < 0)
1862*4882a593Smuzhiyun return ret;
1863*4882a593Smuzhiyun
1864*4882a593Smuzhiyun return devm_iio_device_register(&clientp->dev, indio_dev);
1865*4882a593Smuzhiyun }
1866*4882a593Smuzhiyun
tsl2772_suspend(struct device * dev)1867*4882a593Smuzhiyun static int tsl2772_suspend(struct device *dev)
1868*4882a593Smuzhiyun {
1869*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_get_drvdata(dev);
1870*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
1871*4882a593Smuzhiyun int ret;
1872*4882a593Smuzhiyun
1873*4882a593Smuzhiyun ret = tsl2772_chip_off(indio_dev);
1874*4882a593Smuzhiyun regulator_bulk_disable(ARRAY_SIZE(chip->supplies), chip->supplies);
1875*4882a593Smuzhiyun
1876*4882a593Smuzhiyun return ret;
1877*4882a593Smuzhiyun }
1878*4882a593Smuzhiyun
tsl2772_resume(struct device * dev)1879*4882a593Smuzhiyun static int tsl2772_resume(struct device *dev)
1880*4882a593Smuzhiyun {
1881*4882a593Smuzhiyun struct iio_dev *indio_dev = dev_get_drvdata(dev);
1882*4882a593Smuzhiyun struct tsl2772_chip *chip = iio_priv(indio_dev);
1883*4882a593Smuzhiyun int ret;
1884*4882a593Smuzhiyun
1885*4882a593Smuzhiyun ret = regulator_bulk_enable(ARRAY_SIZE(chip->supplies), chip->supplies);
1886*4882a593Smuzhiyun if (ret < 0)
1887*4882a593Smuzhiyun return ret;
1888*4882a593Smuzhiyun
1889*4882a593Smuzhiyun usleep_range(TSL2772_BOOT_MIN_SLEEP_TIME, TSL2772_BOOT_MAX_SLEEP_TIME);
1890*4882a593Smuzhiyun
1891*4882a593Smuzhiyun return tsl2772_chip_on(indio_dev);
1892*4882a593Smuzhiyun }
1893*4882a593Smuzhiyun
1894*4882a593Smuzhiyun static const struct i2c_device_id tsl2772_idtable[] = {
1895*4882a593Smuzhiyun { "tsl2571", tsl2571 },
1896*4882a593Smuzhiyun { "tsl2671", tsl2671 },
1897*4882a593Smuzhiyun { "tmd2671", tmd2671 },
1898*4882a593Smuzhiyun { "tsl2771", tsl2771 },
1899*4882a593Smuzhiyun { "tmd2771", tmd2771 },
1900*4882a593Smuzhiyun { "tsl2572", tsl2572 },
1901*4882a593Smuzhiyun { "tsl2672", tsl2672 },
1902*4882a593Smuzhiyun { "tmd2672", tmd2672 },
1903*4882a593Smuzhiyun { "tsl2772", tsl2772 },
1904*4882a593Smuzhiyun { "tmd2772", tmd2772 },
1905*4882a593Smuzhiyun { "apds9930", apds9930},
1906*4882a593Smuzhiyun {}
1907*4882a593Smuzhiyun };
1908*4882a593Smuzhiyun
1909*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, tsl2772_idtable);
1910*4882a593Smuzhiyun
1911*4882a593Smuzhiyun static const struct of_device_id tsl2772_of_match[] = {
1912*4882a593Smuzhiyun { .compatible = "amstaos,tsl2571" },
1913*4882a593Smuzhiyun { .compatible = "amstaos,tsl2671" },
1914*4882a593Smuzhiyun { .compatible = "amstaos,tmd2671" },
1915*4882a593Smuzhiyun { .compatible = "amstaos,tsl2771" },
1916*4882a593Smuzhiyun { .compatible = "amstaos,tmd2771" },
1917*4882a593Smuzhiyun { .compatible = "amstaos,tsl2572" },
1918*4882a593Smuzhiyun { .compatible = "amstaos,tsl2672" },
1919*4882a593Smuzhiyun { .compatible = "amstaos,tmd2672" },
1920*4882a593Smuzhiyun { .compatible = "amstaos,tsl2772" },
1921*4882a593Smuzhiyun { .compatible = "amstaos,tmd2772" },
1922*4882a593Smuzhiyun { .compatible = "avago,apds9930" },
1923*4882a593Smuzhiyun {}
1924*4882a593Smuzhiyun };
1925*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, tsl2772_of_match);
1926*4882a593Smuzhiyun
1927*4882a593Smuzhiyun static const struct dev_pm_ops tsl2772_pm_ops = {
1928*4882a593Smuzhiyun .suspend = tsl2772_suspend,
1929*4882a593Smuzhiyun .resume = tsl2772_resume,
1930*4882a593Smuzhiyun };
1931*4882a593Smuzhiyun
1932*4882a593Smuzhiyun static struct i2c_driver tsl2772_driver = {
1933*4882a593Smuzhiyun .driver = {
1934*4882a593Smuzhiyun .name = "tsl2772",
1935*4882a593Smuzhiyun .of_match_table = tsl2772_of_match,
1936*4882a593Smuzhiyun .pm = &tsl2772_pm_ops,
1937*4882a593Smuzhiyun },
1938*4882a593Smuzhiyun .id_table = tsl2772_idtable,
1939*4882a593Smuzhiyun .probe = tsl2772_probe,
1940*4882a593Smuzhiyun };
1941*4882a593Smuzhiyun
1942*4882a593Smuzhiyun module_i2c_driver(tsl2772_driver);
1943*4882a593Smuzhiyun
1944*4882a593Smuzhiyun MODULE_AUTHOR("J. August Brenner <Jon.Brenner@ams.com>");
1945*4882a593Smuzhiyun MODULE_AUTHOR("Brian Masney <masneyb@onstation.org>");
1946*4882a593Smuzhiyun MODULE_DESCRIPTION("TAOS tsl2772 ambient and proximity light sensor driver");
1947*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1948