xref: /OK3568_Linux_fs/kernel/drivers/iio/light/tcs3472.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * tcs3472.c - Support for TAOS TCS3472 color light-to-digital converter
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (c) 2013 Peter Meerwald <pmeerw@pmeerw.net>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Color light sensor with 16-bit channels for red, green, blue, clear);
8*4882a593Smuzhiyun  * 7-bit I2C slave address 0x39 (TCS34721, TCS34723) or 0x29 (TCS34725,
9*4882a593Smuzhiyun  * TCS34727)
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * Datasheet: http://ams.com/eng/content/download/319364/1117183/file/TCS3472_Datasheet_EN_v2.pdf
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  * TODO: wait time
14*4882a593Smuzhiyun  */
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/i2c.h>
18*4882a593Smuzhiyun #include <linux/delay.h>
19*4882a593Smuzhiyun #include <linux/pm.h>
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #include <linux/iio/iio.h>
22*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
23*4882a593Smuzhiyun #include <linux/iio/events.h>
24*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
25*4882a593Smuzhiyun #include <linux/iio/buffer.h>
26*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define TCS3472_DRV_NAME "tcs3472"
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define TCS3472_COMMAND BIT(7)
31*4882a593Smuzhiyun #define TCS3472_AUTO_INCR BIT(5)
32*4882a593Smuzhiyun #define TCS3472_SPECIAL_FUNC (BIT(5) | BIT(6))
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define TCS3472_INTR_CLEAR (TCS3472_COMMAND | TCS3472_SPECIAL_FUNC | 0x06)
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define TCS3472_ENABLE (TCS3472_COMMAND | 0x00)
37*4882a593Smuzhiyun #define TCS3472_ATIME (TCS3472_COMMAND | 0x01)
38*4882a593Smuzhiyun #define TCS3472_WTIME (TCS3472_COMMAND | 0x03)
39*4882a593Smuzhiyun #define TCS3472_AILT (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x04)
40*4882a593Smuzhiyun #define TCS3472_AIHT (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x06)
41*4882a593Smuzhiyun #define TCS3472_PERS (TCS3472_COMMAND | 0x0c)
42*4882a593Smuzhiyun #define TCS3472_CONFIG (TCS3472_COMMAND | 0x0d)
43*4882a593Smuzhiyun #define TCS3472_CONTROL (TCS3472_COMMAND | 0x0f)
44*4882a593Smuzhiyun #define TCS3472_ID (TCS3472_COMMAND | 0x12)
45*4882a593Smuzhiyun #define TCS3472_STATUS (TCS3472_COMMAND | 0x13)
46*4882a593Smuzhiyun #define TCS3472_CDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x14)
47*4882a593Smuzhiyun #define TCS3472_RDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x16)
48*4882a593Smuzhiyun #define TCS3472_GDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x18)
49*4882a593Smuzhiyun #define TCS3472_BDATA (TCS3472_COMMAND | TCS3472_AUTO_INCR | 0x1a)
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun #define TCS3472_STATUS_AINT BIT(4)
52*4882a593Smuzhiyun #define TCS3472_STATUS_AVALID BIT(0)
53*4882a593Smuzhiyun #define TCS3472_ENABLE_AIEN BIT(4)
54*4882a593Smuzhiyun #define TCS3472_ENABLE_AEN BIT(1)
55*4882a593Smuzhiyun #define TCS3472_ENABLE_PON BIT(0)
56*4882a593Smuzhiyun #define TCS3472_CONTROL_AGAIN_MASK (BIT(0) | BIT(1))
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun struct tcs3472_data {
59*4882a593Smuzhiyun 	struct i2c_client *client;
60*4882a593Smuzhiyun 	struct mutex lock;
61*4882a593Smuzhiyun 	u16 low_thresh;
62*4882a593Smuzhiyun 	u16 high_thresh;
63*4882a593Smuzhiyun 	u8 enable;
64*4882a593Smuzhiyun 	u8 control;
65*4882a593Smuzhiyun 	u8 atime;
66*4882a593Smuzhiyun 	u8 apers;
67*4882a593Smuzhiyun 	/* Ensure timestamp is naturally aligned */
68*4882a593Smuzhiyun 	struct {
69*4882a593Smuzhiyun 		u16 chans[4];
70*4882a593Smuzhiyun 		s64 timestamp __aligned(8);
71*4882a593Smuzhiyun 	} scan;
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun static const struct iio_event_spec tcs3472_events[] = {
75*4882a593Smuzhiyun 	{
76*4882a593Smuzhiyun 		.type = IIO_EV_TYPE_THRESH,
77*4882a593Smuzhiyun 		.dir = IIO_EV_DIR_RISING,
78*4882a593Smuzhiyun 		.mask_separate = BIT(IIO_EV_INFO_VALUE),
79*4882a593Smuzhiyun 	}, {
80*4882a593Smuzhiyun 		.type = IIO_EV_TYPE_THRESH,
81*4882a593Smuzhiyun 		.dir = IIO_EV_DIR_FALLING,
82*4882a593Smuzhiyun 		.mask_separate = BIT(IIO_EV_INFO_VALUE),
83*4882a593Smuzhiyun 	}, {
84*4882a593Smuzhiyun 		.type = IIO_EV_TYPE_THRESH,
85*4882a593Smuzhiyun 		.dir = IIO_EV_DIR_EITHER,
86*4882a593Smuzhiyun 		.mask_separate = BIT(IIO_EV_INFO_ENABLE) |
87*4882a593Smuzhiyun 				 BIT(IIO_EV_INFO_PERIOD),
88*4882a593Smuzhiyun 	},
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun #define TCS3472_CHANNEL(_color, _si, _addr) { \
92*4882a593Smuzhiyun 	.type = IIO_INTENSITY, \
93*4882a593Smuzhiyun 	.modified = 1, \
94*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
95*4882a593Smuzhiyun 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_CALIBSCALE) | \
96*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_INT_TIME), \
97*4882a593Smuzhiyun 	.channel2 = IIO_MOD_LIGHT_##_color, \
98*4882a593Smuzhiyun 	.address = _addr, \
99*4882a593Smuzhiyun 	.scan_index = _si, \
100*4882a593Smuzhiyun 	.scan_type = { \
101*4882a593Smuzhiyun 		.sign = 'u', \
102*4882a593Smuzhiyun 		.realbits = 16, \
103*4882a593Smuzhiyun 		.storagebits = 16, \
104*4882a593Smuzhiyun 		.endianness = IIO_CPU, \
105*4882a593Smuzhiyun 	}, \
106*4882a593Smuzhiyun 	.event_spec = _si ? NULL : tcs3472_events, \
107*4882a593Smuzhiyun 	.num_event_specs = _si ? 0 : ARRAY_SIZE(tcs3472_events), \
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun static const int tcs3472_agains[] = { 1, 4, 16, 60 };
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun static const struct iio_chan_spec tcs3472_channels[] = {
113*4882a593Smuzhiyun 	TCS3472_CHANNEL(CLEAR, 0, TCS3472_CDATA),
114*4882a593Smuzhiyun 	TCS3472_CHANNEL(RED, 1, TCS3472_RDATA),
115*4882a593Smuzhiyun 	TCS3472_CHANNEL(GREEN, 2, TCS3472_GDATA),
116*4882a593Smuzhiyun 	TCS3472_CHANNEL(BLUE, 3, TCS3472_BDATA),
117*4882a593Smuzhiyun 	IIO_CHAN_SOFT_TIMESTAMP(4),
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun 
tcs3472_req_data(struct tcs3472_data * data)120*4882a593Smuzhiyun static int tcs3472_req_data(struct tcs3472_data *data)
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun 	int tries = 50;
123*4882a593Smuzhiyun 	int ret;
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun 	while (tries--) {
126*4882a593Smuzhiyun 		ret = i2c_smbus_read_byte_data(data->client, TCS3472_STATUS);
127*4882a593Smuzhiyun 		if (ret < 0)
128*4882a593Smuzhiyun 			return ret;
129*4882a593Smuzhiyun 		if (ret & TCS3472_STATUS_AVALID)
130*4882a593Smuzhiyun 			break;
131*4882a593Smuzhiyun 		msleep(20);
132*4882a593Smuzhiyun 	}
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun 	if (tries < 0) {
135*4882a593Smuzhiyun 		dev_err(&data->client->dev, "data not ready\n");
136*4882a593Smuzhiyun 		return -EIO;
137*4882a593Smuzhiyun 	}
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun 	return 0;
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun 
tcs3472_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)142*4882a593Smuzhiyun static int tcs3472_read_raw(struct iio_dev *indio_dev,
143*4882a593Smuzhiyun 			   struct iio_chan_spec const *chan,
144*4882a593Smuzhiyun 			   int *val, int *val2, long mask)
145*4882a593Smuzhiyun {
146*4882a593Smuzhiyun 	struct tcs3472_data *data = iio_priv(indio_dev);
147*4882a593Smuzhiyun 	int ret;
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun 	switch (mask) {
150*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW:
151*4882a593Smuzhiyun 		ret = iio_device_claim_direct_mode(indio_dev);
152*4882a593Smuzhiyun 		if (ret)
153*4882a593Smuzhiyun 			return ret;
154*4882a593Smuzhiyun 		ret = tcs3472_req_data(data);
155*4882a593Smuzhiyun 		if (ret < 0) {
156*4882a593Smuzhiyun 			iio_device_release_direct_mode(indio_dev);
157*4882a593Smuzhiyun 			return ret;
158*4882a593Smuzhiyun 		}
159*4882a593Smuzhiyun 		ret = i2c_smbus_read_word_data(data->client, chan->address);
160*4882a593Smuzhiyun 		iio_device_release_direct_mode(indio_dev);
161*4882a593Smuzhiyun 		if (ret < 0)
162*4882a593Smuzhiyun 			return ret;
163*4882a593Smuzhiyun 		*val = ret;
164*4882a593Smuzhiyun 		return IIO_VAL_INT;
165*4882a593Smuzhiyun 	case IIO_CHAN_INFO_CALIBSCALE:
166*4882a593Smuzhiyun 		*val = tcs3472_agains[data->control &
167*4882a593Smuzhiyun 			TCS3472_CONTROL_AGAIN_MASK];
168*4882a593Smuzhiyun 		return IIO_VAL_INT;
169*4882a593Smuzhiyun 	case IIO_CHAN_INFO_INT_TIME:
170*4882a593Smuzhiyun 		*val = 0;
171*4882a593Smuzhiyun 		*val2 = (256 - data->atime) * 2400;
172*4882a593Smuzhiyun 		return IIO_VAL_INT_PLUS_MICRO;
173*4882a593Smuzhiyun 	}
174*4882a593Smuzhiyun 	return -EINVAL;
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun 
tcs3472_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)177*4882a593Smuzhiyun static int tcs3472_write_raw(struct iio_dev *indio_dev,
178*4882a593Smuzhiyun 			       struct iio_chan_spec const *chan,
179*4882a593Smuzhiyun 			       int val, int val2, long mask)
180*4882a593Smuzhiyun {
181*4882a593Smuzhiyun 	struct tcs3472_data *data = iio_priv(indio_dev);
182*4882a593Smuzhiyun 	int i;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	switch (mask) {
185*4882a593Smuzhiyun 	case IIO_CHAN_INFO_CALIBSCALE:
186*4882a593Smuzhiyun 		if (val2 != 0)
187*4882a593Smuzhiyun 			return -EINVAL;
188*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(tcs3472_agains); i++) {
189*4882a593Smuzhiyun 			if (val == tcs3472_agains[i]) {
190*4882a593Smuzhiyun 				data->control &= ~TCS3472_CONTROL_AGAIN_MASK;
191*4882a593Smuzhiyun 				data->control |= i;
192*4882a593Smuzhiyun 				return i2c_smbus_write_byte_data(
193*4882a593Smuzhiyun 					data->client, TCS3472_CONTROL,
194*4882a593Smuzhiyun 					data->control);
195*4882a593Smuzhiyun 			}
196*4882a593Smuzhiyun 		}
197*4882a593Smuzhiyun 		return -EINVAL;
198*4882a593Smuzhiyun 	case IIO_CHAN_INFO_INT_TIME:
199*4882a593Smuzhiyun 		if (val != 0)
200*4882a593Smuzhiyun 			return -EINVAL;
201*4882a593Smuzhiyun 		for (i = 0; i < 256; i++) {
202*4882a593Smuzhiyun 			if (val2 == (256 - i) * 2400) {
203*4882a593Smuzhiyun 				data->atime = i;
204*4882a593Smuzhiyun 				return i2c_smbus_write_byte_data(
205*4882a593Smuzhiyun 					data->client, TCS3472_ATIME,
206*4882a593Smuzhiyun 					data->atime);
207*4882a593Smuzhiyun 			}
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 		}
210*4882a593Smuzhiyun 		return -EINVAL;
211*4882a593Smuzhiyun 	}
212*4882a593Smuzhiyun 	return -EINVAL;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun /*
216*4882a593Smuzhiyun  * Translation from APERS field value to the number of consecutive out-of-range
217*4882a593Smuzhiyun  * clear channel values before an interrupt is generated
218*4882a593Smuzhiyun  */
219*4882a593Smuzhiyun static const int tcs3472_intr_pers[] = {
220*4882a593Smuzhiyun 	0, 1, 2, 3, 5, 10, 15, 20, 25, 30, 35, 40, 45, 50, 55, 60
221*4882a593Smuzhiyun };
222*4882a593Smuzhiyun 
tcs3472_read_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)223*4882a593Smuzhiyun static int tcs3472_read_event(struct iio_dev *indio_dev,
224*4882a593Smuzhiyun 	const struct iio_chan_spec *chan, enum iio_event_type type,
225*4882a593Smuzhiyun 	enum iio_event_direction dir, enum iio_event_info info, int *val,
226*4882a593Smuzhiyun 	int *val2)
227*4882a593Smuzhiyun {
228*4882a593Smuzhiyun 	struct tcs3472_data *data = iio_priv(indio_dev);
229*4882a593Smuzhiyun 	int ret;
230*4882a593Smuzhiyun 	unsigned int period;
231*4882a593Smuzhiyun 
232*4882a593Smuzhiyun 	mutex_lock(&data->lock);
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	switch (info) {
235*4882a593Smuzhiyun 	case IIO_EV_INFO_VALUE:
236*4882a593Smuzhiyun 		*val = (dir == IIO_EV_DIR_RISING) ?
237*4882a593Smuzhiyun 			data->high_thresh : data->low_thresh;
238*4882a593Smuzhiyun 		ret = IIO_VAL_INT;
239*4882a593Smuzhiyun 		break;
240*4882a593Smuzhiyun 	case IIO_EV_INFO_PERIOD:
241*4882a593Smuzhiyun 		period = (256 - data->atime) * 2400 *
242*4882a593Smuzhiyun 			tcs3472_intr_pers[data->apers];
243*4882a593Smuzhiyun 		*val = period / USEC_PER_SEC;
244*4882a593Smuzhiyun 		*val2 = period % USEC_PER_SEC;
245*4882a593Smuzhiyun 		ret = IIO_VAL_INT_PLUS_MICRO;
246*4882a593Smuzhiyun 		break;
247*4882a593Smuzhiyun 	default:
248*4882a593Smuzhiyun 		ret = -EINVAL;
249*4882a593Smuzhiyun 		break;
250*4882a593Smuzhiyun 	}
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	return ret;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun 
tcs3472_write_event(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)257*4882a593Smuzhiyun static int tcs3472_write_event(struct iio_dev *indio_dev,
258*4882a593Smuzhiyun 	const struct iio_chan_spec *chan, enum iio_event_type type,
259*4882a593Smuzhiyun 	enum iio_event_direction dir, enum iio_event_info info, int val,
260*4882a593Smuzhiyun 	int val2)
261*4882a593Smuzhiyun {
262*4882a593Smuzhiyun 	struct tcs3472_data *data = iio_priv(indio_dev);
263*4882a593Smuzhiyun 	int ret;
264*4882a593Smuzhiyun 	u8 command;
265*4882a593Smuzhiyun 	int period;
266*4882a593Smuzhiyun 	int i;
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun 	mutex_lock(&data->lock);
269*4882a593Smuzhiyun 	switch (info) {
270*4882a593Smuzhiyun 	case IIO_EV_INFO_VALUE:
271*4882a593Smuzhiyun 		switch (dir) {
272*4882a593Smuzhiyun 		case IIO_EV_DIR_RISING:
273*4882a593Smuzhiyun 			command = TCS3472_AIHT;
274*4882a593Smuzhiyun 			break;
275*4882a593Smuzhiyun 		case IIO_EV_DIR_FALLING:
276*4882a593Smuzhiyun 			command = TCS3472_AILT;
277*4882a593Smuzhiyun 			break;
278*4882a593Smuzhiyun 		default:
279*4882a593Smuzhiyun 			ret = -EINVAL;
280*4882a593Smuzhiyun 			goto error;
281*4882a593Smuzhiyun 		}
282*4882a593Smuzhiyun 		ret = i2c_smbus_write_word_data(data->client, command, val);
283*4882a593Smuzhiyun 		if (ret)
284*4882a593Smuzhiyun 			goto error;
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 		if (dir == IIO_EV_DIR_RISING)
287*4882a593Smuzhiyun 			data->high_thresh = val;
288*4882a593Smuzhiyun 		else
289*4882a593Smuzhiyun 			data->low_thresh = val;
290*4882a593Smuzhiyun 		break;
291*4882a593Smuzhiyun 	case IIO_EV_INFO_PERIOD:
292*4882a593Smuzhiyun 		period = val * USEC_PER_SEC + val2;
293*4882a593Smuzhiyun 		for (i = 1; i < ARRAY_SIZE(tcs3472_intr_pers) - 1; i++) {
294*4882a593Smuzhiyun 			if (period <= (256 - data->atime) * 2400 *
295*4882a593Smuzhiyun 					tcs3472_intr_pers[i])
296*4882a593Smuzhiyun 				break;
297*4882a593Smuzhiyun 		}
298*4882a593Smuzhiyun 		ret = i2c_smbus_write_byte_data(data->client, TCS3472_PERS, i);
299*4882a593Smuzhiyun 		if (ret)
300*4882a593Smuzhiyun 			goto error;
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 		data->apers = i;
303*4882a593Smuzhiyun 		break;
304*4882a593Smuzhiyun 	default:
305*4882a593Smuzhiyun 		ret = -EINVAL;
306*4882a593Smuzhiyun 		break;
307*4882a593Smuzhiyun 	}
308*4882a593Smuzhiyun error:
309*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	return ret;
312*4882a593Smuzhiyun }
313*4882a593Smuzhiyun 
tcs3472_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)314*4882a593Smuzhiyun static int tcs3472_read_event_config(struct iio_dev *indio_dev,
315*4882a593Smuzhiyun 	const struct iio_chan_spec *chan, enum iio_event_type type,
316*4882a593Smuzhiyun 	enum iio_event_direction dir)
317*4882a593Smuzhiyun {
318*4882a593Smuzhiyun 	struct tcs3472_data *data = iio_priv(indio_dev);
319*4882a593Smuzhiyun 	int ret;
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	mutex_lock(&data->lock);
322*4882a593Smuzhiyun 	ret = !!(data->enable & TCS3472_ENABLE_AIEN);
323*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	return ret;
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun 
tcs3472_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)328*4882a593Smuzhiyun static int tcs3472_write_event_config(struct iio_dev *indio_dev,
329*4882a593Smuzhiyun 	const struct iio_chan_spec *chan, enum iio_event_type type,
330*4882a593Smuzhiyun 	enum iio_event_direction dir, int state)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun 	struct tcs3472_data *data = iio_priv(indio_dev);
333*4882a593Smuzhiyun 	int ret = 0;
334*4882a593Smuzhiyun 	u8 enable_old;
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	mutex_lock(&data->lock);
337*4882a593Smuzhiyun 
338*4882a593Smuzhiyun 	enable_old = data->enable;
339*4882a593Smuzhiyun 
340*4882a593Smuzhiyun 	if (state)
341*4882a593Smuzhiyun 		data->enable |= TCS3472_ENABLE_AIEN;
342*4882a593Smuzhiyun 	else
343*4882a593Smuzhiyun 		data->enable &= ~TCS3472_ENABLE_AIEN;
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun 	if (enable_old != data->enable) {
346*4882a593Smuzhiyun 		ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
347*4882a593Smuzhiyun 						data->enable);
348*4882a593Smuzhiyun 		if (ret)
349*4882a593Smuzhiyun 			data->enable = enable_old;
350*4882a593Smuzhiyun 	}
351*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	return ret;
354*4882a593Smuzhiyun }
355*4882a593Smuzhiyun 
tcs3472_event_handler(int irq,void * priv)356*4882a593Smuzhiyun static irqreturn_t tcs3472_event_handler(int irq, void *priv)
357*4882a593Smuzhiyun {
358*4882a593Smuzhiyun 	struct iio_dev *indio_dev = priv;
359*4882a593Smuzhiyun 	struct tcs3472_data *data = iio_priv(indio_dev);
360*4882a593Smuzhiyun 	int ret;
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(data->client, TCS3472_STATUS);
363*4882a593Smuzhiyun 	if (ret >= 0 && (ret & TCS3472_STATUS_AINT)) {
364*4882a593Smuzhiyun 		iio_push_event(indio_dev, IIO_UNMOD_EVENT_CODE(IIO_INTENSITY, 0,
365*4882a593Smuzhiyun 						IIO_EV_TYPE_THRESH,
366*4882a593Smuzhiyun 						IIO_EV_DIR_EITHER),
367*4882a593Smuzhiyun 				iio_get_time_ns(indio_dev));
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun 		i2c_smbus_read_byte_data(data->client, TCS3472_INTR_CLEAR);
370*4882a593Smuzhiyun 	}
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	return IRQ_HANDLED;
373*4882a593Smuzhiyun }
374*4882a593Smuzhiyun 
tcs3472_trigger_handler(int irq,void * p)375*4882a593Smuzhiyun static irqreturn_t tcs3472_trigger_handler(int irq, void *p)
376*4882a593Smuzhiyun {
377*4882a593Smuzhiyun 	struct iio_poll_func *pf = p;
378*4882a593Smuzhiyun 	struct iio_dev *indio_dev = pf->indio_dev;
379*4882a593Smuzhiyun 	struct tcs3472_data *data = iio_priv(indio_dev);
380*4882a593Smuzhiyun 	int i, j = 0;
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun 	int ret = tcs3472_req_data(data);
383*4882a593Smuzhiyun 	if (ret < 0)
384*4882a593Smuzhiyun 		goto done;
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 	for_each_set_bit(i, indio_dev->active_scan_mask,
387*4882a593Smuzhiyun 		indio_dev->masklength) {
388*4882a593Smuzhiyun 		ret = i2c_smbus_read_word_data(data->client,
389*4882a593Smuzhiyun 			TCS3472_CDATA + 2*i);
390*4882a593Smuzhiyun 		if (ret < 0)
391*4882a593Smuzhiyun 			goto done;
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 		data->scan.chans[j++] = ret;
394*4882a593Smuzhiyun 	}
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun 	iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
397*4882a593Smuzhiyun 		iio_get_time_ns(indio_dev));
398*4882a593Smuzhiyun 
399*4882a593Smuzhiyun done:
400*4882a593Smuzhiyun 	iio_trigger_notify_done(indio_dev->trig);
401*4882a593Smuzhiyun 
402*4882a593Smuzhiyun 	return IRQ_HANDLED;
403*4882a593Smuzhiyun }
404*4882a593Smuzhiyun 
tcs3472_show_int_time_available(struct device * dev,struct device_attribute * attr,char * buf)405*4882a593Smuzhiyun static ssize_t tcs3472_show_int_time_available(struct device *dev,
406*4882a593Smuzhiyun 					struct device_attribute *attr,
407*4882a593Smuzhiyun 					char *buf)
408*4882a593Smuzhiyun {
409*4882a593Smuzhiyun 	size_t len = 0;
410*4882a593Smuzhiyun 	int i;
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	for (i = 1; i <= 256; i++)
413*4882a593Smuzhiyun 		len += scnprintf(buf + len, PAGE_SIZE - len, "0.%06d ",
414*4882a593Smuzhiyun 			2400 * i);
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun 	/* replace trailing space by newline */
417*4882a593Smuzhiyun 	buf[len - 1] = '\n';
418*4882a593Smuzhiyun 
419*4882a593Smuzhiyun 	return len;
420*4882a593Smuzhiyun }
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun static IIO_CONST_ATTR(calibscale_available, "1 4 16 60");
423*4882a593Smuzhiyun static IIO_DEV_ATTR_INT_TIME_AVAIL(tcs3472_show_int_time_available);
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun static struct attribute *tcs3472_attributes[] = {
426*4882a593Smuzhiyun 	&iio_const_attr_calibscale_available.dev_attr.attr,
427*4882a593Smuzhiyun 	&iio_dev_attr_integration_time_available.dev_attr.attr,
428*4882a593Smuzhiyun 	NULL
429*4882a593Smuzhiyun };
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun static const struct attribute_group tcs3472_attribute_group = {
432*4882a593Smuzhiyun 	.attrs = tcs3472_attributes,
433*4882a593Smuzhiyun };
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun static const struct iio_info tcs3472_info = {
436*4882a593Smuzhiyun 	.read_raw = tcs3472_read_raw,
437*4882a593Smuzhiyun 	.write_raw = tcs3472_write_raw,
438*4882a593Smuzhiyun 	.read_event_value = tcs3472_read_event,
439*4882a593Smuzhiyun 	.write_event_value = tcs3472_write_event,
440*4882a593Smuzhiyun 	.read_event_config = tcs3472_read_event_config,
441*4882a593Smuzhiyun 	.write_event_config = tcs3472_write_event_config,
442*4882a593Smuzhiyun 	.attrs = &tcs3472_attribute_group,
443*4882a593Smuzhiyun };
444*4882a593Smuzhiyun 
tcs3472_probe(struct i2c_client * client,const struct i2c_device_id * id)445*4882a593Smuzhiyun static int tcs3472_probe(struct i2c_client *client,
446*4882a593Smuzhiyun 			   const struct i2c_device_id *id)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun 	struct tcs3472_data *data;
449*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
450*4882a593Smuzhiyun 	int ret;
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
453*4882a593Smuzhiyun 	if (indio_dev == NULL)
454*4882a593Smuzhiyun 		return -ENOMEM;
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	data = iio_priv(indio_dev);
457*4882a593Smuzhiyun 	i2c_set_clientdata(client, indio_dev);
458*4882a593Smuzhiyun 	data->client = client;
459*4882a593Smuzhiyun 	mutex_init(&data->lock);
460*4882a593Smuzhiyun 
461*4882a593Smuzhiyun 	indio_dev->info = &tcs3472_info;
462*4882a593Smuzhiyun 	indio_dev->name = TCS3472_DRV_NAME;
463*4882a593Smuzhiyun 	indio_dev->channels = tcs3472_channels;
464*4882a593Smuzhiyun 	indio_dev->num_channels = ARRAY_SIZE(tcs3472_channels);
465*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(data->client, TCS3472_ID);
468*4882a593Smuzhiyun 	if (ret < 0)
469*4882a593Smuzhiyun 		return ret;
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	if (ret == 0x44)
472*4882a593Smuzhiyun 		dev_info(&client->dev, "TCS34721/34725 found\n");
473*4882a593Smuzhiyun 	else if (ret == 0x4d)
474*4882a593Smuzhiyun 		dev_info(&client->dev, "TCS34723/34727 found\n");
475*4882a593Smuzhiyun 	else
476*4882a593Smuzhiyun 		return -ENODEV;
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(data->client, TCS3472_CONTROL);
479*4882a593Smuzhiyun 	if (ret < 0)
480*4882a593Smuzhiyun 		return ret;
481*4882a593Smuzhiyun 	data->control = ret;
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(data->client, TCS3472_ATIME);
484*4882a593Smuzhiyun 	if (ret < 0)
485*4882a593Smuzhiyun 		return ret;
486*4882a593Smuzhiyun 	data->atime = ret;
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun 	ret = i2c_smbus_read_word_data(data->client, TCS3472_AILT);
489*4882a593Smuzhiyun 	if (ret < 0)
490*4882a593Smuzhiyun 		return ret;
491*4882a593Smuzhiyun 	data->low_thresh = ret;
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun 	ret = i2c_smbus_read_word_data(data->client, TCS3472_AIHT);
494*4882a593Smuzhiyun 	if (ret < 0)
495*4882a593Smuzhiyun 		return ret;
496*4882a593Smuzhiyun 	data->high_thresh = ret;
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun 	data->apers = 1;
499*4882a593Smuzhiyun 	ret = i2c_smbus_write_byte_data(data->client, TCS3472_PERS,
500*4882a593Smuzhiyun 					data->apers);
501*4882a593Smuzhiyun 	if (ret < 0)
502*4882a593Smuzhiyun 		return ret;
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(data->client, TCS3472_ENABLE);
505*4882a593Smuzhiyun 	if (ret < 0)
506*4882a593Smuzhiyun 		return ret;
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun 	/* enable device */
509*4882a593Smuzhiyun 	data->enable = ret | TCS3472_ENABLE_PON | TCS3472_ENABLE_AEN;
510*4882a593Smuzhiyun 	data->enable &= ~TCS3472_ENABLE_AIEN;
511*4882a593Smuzhiyun 	ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
512*4882a593Smuzhiyun 		data->enable);
513*4882a593Smuzhiyun 	if (ret < 0)
514*4882a593Smuzhiyun 		return ret;
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 	ret = iio_triggered_buffer_setup(indio_dev, NULL,
517*4882a593Smuzhiyun 		tcs3472_trigger_handler, NULL);
518*4882a593Smuzhiyun 	if (ret < 0)
519*4882a593Smuzhiyun 		return ret;
520*4882a593Smuzhiyun 
521*4882a593Smuzhiyun 	if (client->irq) {
522*4882a593Smuzhiyun 		ret = request_threaded_irq(client->irq, NULL,
523*4882a593Smuzhiyun 					   tcs3472_event_handler,
524*4882a593Smuzhiyun 					   IRQF_TRIGGER_FALLING | IRQF_SHARED |
525*4882a593Smuzhiyun 					   IRQF_ONESHOT,
526*4882a593Smuzhiyun 					   client->name, indio_dev);
527*4882a593Smuzhiyun 		if (ret)
528*4882a593Smuzhiyun 			goto buffer_cleanup;
529*4882a593Smuzhiyun 	}
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun 	ret = iio_device_register(indio_dev);
532*4882a593Smuzhiyun 	if (ret < 0)
533*4882a593Smuzhiyun 		goto free_irq;
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	return 0;
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun free_irq:
538*4882a593Smuzhiyun 	if (client->irq)
539*4882a593Smuzhiyun 		free_irq(client->irq, indio_dev);
540*4882a593Smuzhiyun buffer_cleanup:
541*4882a593Smuzhiyun 	iio_triggered_buffer_cleanup(indio_dev);
542*4882a593Smuzhiyun 	return ret;
543*4882a593Smuzhiyun }
544*4882a593Smuzhiyun 
tcs3472_powerdown(struct tcs3472_data * data)545*4882a593Smuzhiyun static int tcs3472_powerdown(struct tcs3472_data *data)
546*4882a593Smuzhiyun {
547*4882a593Smuzhiyun 	int ret;
548*4882a593Smuzhiyun 	u8 enable_mask = TCS3472_ENABLE_AEN | TCS3472_ENABLE_PON;
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 	mutex_lock(&data->lock);
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun 	ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
553*4882a593Smuzhiyun 		data->enable & ~enable_mask);
554*4882a593Smuzhiyun 	if (!ret)
555*4882a593Smuzhiyun 		data->enable &= ~enable_mask;
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 	return ret;
560*4882a593Smuzhiyun }
561*4882a593Smuzhiyun 
tcs3472_remove(struct i2c_client * client)562*4882a593Smuzhiyun static int tcs3472_remove(struct i2c_client *client)
563*4882a593Smuzhiyun {
564*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(client);
565*4882a593Smuzhiyun 
566*4882a593Smuzhiyun 	iio_device_unregister(indio_dev);
567*4882a593Smuzhiyun 	if (client->irq)
568*4882a593Smuzhiyun 		free_irq(client->irq, indio_dev);
569*4882a593Smuzhiyun 	iio_triggered_buffer_cleanup(indio_dev);
570*4882a593Smuzhiyun 	tcs3472_powerdown(iio_priv(indio_dev));
571*4882a593Smuzhiyun 
572*4882a593Smuzhiyun 	return 0;
573*4882a593Smuzhiyun }
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
tcs3472_suspend(struct device * dev)576*4882a593Smuzhiyun static int tcs3472_suspend(struct device *dev)
577*4882a593Smuzhiyun {
578*4882a593Smuzhiyun 	struct tcs3472_data *data = iio_priv(i2c_get_clientdata(
579*4882a593Smuzhiyun 		to_i2c_client(dev)));
580*4882a593Smuzhiyun 	return tcs3472_powerdown(data);
581*4882a593Smuzhiyun }
582*4882a593Smuzhiyun 
tcs3472_resume(struct device * dev)583*4882a593Smuzhiyun static int tcs3472_resume(struct device *dev)
584*4882a593Smuzhiyun {
585*4882a593Smuzhiyun 	struct tcs3472_data *data = iio_priv(i2c_get_clientdata(
586*4882a593Smuzhiyun 		to_i2c_client(dev)));
587*4882a593Smuzhiyun 	int ret;
588*4882a593Smuzhiyun 	u8 enable_mask = TCS3472_ENABLE_AEN | TCS3472_ENABLE_PON;
589*4882a593Smuzhiyun 
590*4882a593Smuzhiyun 	mutex_lock(&data->lock);
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun 	ret = i2c_smbus_write_byte_data(data->client, TCS3472_ENABLE,
593*4882a593Smuzhiyun 		data->enable | enable_mask);
594*4882a593Smuzhiyun 	if (!ret)
595*4882a593Smuzhiyun 		data->enable |= enable_mask;
596*4882a593Smuzhiyun 
597*4882a593Smuzhiyun 	mutex_unlock(&data->lock);
598*4882a593Smuzhiyun 
599*4882a593Smuzhiyun 	return ret;
600*4882a593Smuzhiyun }
601*4882a593Smuzhiyun #endif
602*4882a593Smuzhiyun 
603*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(tcs3472_pm_ops, tcs3472_suspend, tcs3472_resume);
604*4882a593Smuzhiyun 
605*4882a593Smuzhiyun static const struct i2c_device_id tcs3472_id[] = {
606*4882a593Smuzhiyun 	{ "tcs3472", 0 },
607*4882a593Smuzhiyun 	{ }
608*4882a593Smuzhiyun };
609*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, tcs3472_id);
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun static struct i2c_driver tcs3472_driver = {
612*4882a593Smuzhiyun 	.driver = {
613*4882a593Smuzhiyun 		.name	= TCS3472_DRV_NAME,
614*4882a593Smuzhiyun 		.pm	= &tcs3472_pm_ops,
615*4882a593Smuzhiyun 	},
616*4882a593Smuzhiyun 	.probe		= tcs3472_probe,
617*4882a593Smuzhiyun 	.remove		= tcs3472_remove,
618*4882a593Smuzhiyun 	.id_table	= tcs3472_id,
619*4882a593Smuzhiyun };
620*4882a593Smuzhiyun module_i2c_driver(tcs3472_driver);
621*4882a593Smuzhiyun 
622*4882a593Smuzhiyun MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
623*4882a593Smuzhiyun MODULE_DESCRIPTION("TCS3472 color light sensors driver");
624*4882a593Smuzhiyun MODULE_LICENSE("GPL");
625