1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2015 Intel Corporation
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Driver for TXC PA12203001 Proximity and Ambient Light Sensor.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * To do: Interrupt support.
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/kernel.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/acpi.h>
13*4882a593Smuzhiyun #include <linux/delay.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/iio/iio.h>
16*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
17*4882a593Smuzhiyun #include <linux/mutex.h>
18*4882a593Smuzhiyun #include <linux/pm.h>
19*4882a593Smuzhiyun #include <linux/pm_runtime.h>
20*4882a593Smuzhiyun #include <linux/regmap.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define PA12203001_DRIVER_NAME "pa12203001"
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #define PA12203001_REG_CFG0 0x00
25*4882a593Smuzhiyun #define PA12203001_REG_CFG1 0x01
26*4882a593Smuzhiyun #define PA12203001_REG_CFG2 0x02
27*4882a593Smuzhiyun #define PA12203001_REG_CFG3 0x03
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun #define PA12203001_REG_ADL 0x0b
30*4882a593Smuzhiyun #define PA12203001_REG_PDH 0x0e
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #define PA12203001_REG_POFS 0x10
33*4882a593Smuzhiyun #define PA12203001_REG_PSET 0x11
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define PA12203001_ALS_EN_MASK BIT(0)
36*4882a593Smuzhiyun #define PA12203001_PX_EN_MASK BIT(1)
37*4882a593Smuzhiyun #define PA12203001_PX_NORMAL_MODE_MASK GENMASK(7, 6)
38*4882a593Smuzhiyun #define PA12203001_AFSR_MASK GENMASK(5, 4)
39*4882a593Smuzhiyun #define PA12203001_AFSR_SHIFT 4
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define PA12203001_PSCAN 0x03
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* als range 31000, ps, als disabled */
44*4882a593Smuzhiyun #define PA12203001_REG_CFG0_DEFAULT 0x30
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* led current: 100 mA */
47*4882a593Smuzhiyun #define PA12203001_REG_CFG1_DEFAULT 0x20
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* ps mode: normal, interrupts not active */
50*4882a593Smuzhiyun #define PA12203001_REG_CFG2_DEFAULT 0xcc
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun #define PA12203001_REG_CFG3_DEFAULT 0x00
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun #define PA12203001_SLEEP_DELAY_MS 3000
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun #define PA12203001_CHIP_ENABLE 0xff
57*4882a593Smuzhiyun #define PA12203001_CHIP_DISABLE 0x00
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* available scales: corresponding to [500, 4000, 7000, 31000] lux */
60*4882a593Smuzhiyun static const int pa12203001_scales[] = { 7629, 61036, 106813, 473029};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun struct pa12203001_data {
63*4882a593Smuzhiyun struct i2c_client *client;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* protect device states */
66*4882a593Smuzhiyun struct mutex lock;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun bool als_enabled;
69*4882a593Smuzhiyun bool px_enabled;
70*4882a593Smuzhiyun bool als_needs_enable;
71*4882a593Smuzhiyun bool px_needs_enable;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun struct regmap *map;
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun static const struct {
77*4882a593Smuzhiyun u8 reg;
78*4882a593Smuzhiyun u8 val;
79*4882a593Smuzhiyun } regvals[] = {
80*4882a593Smuzhiyun {PA12203001_REG_CFG0, PA12203001_REG_CFG0_DEFAULT},
81*4882a593Smuzhiyun {PA12203001_REG_CFG1, PA12203001_REG_CFG1_DEFAULT},
82*4882a593Smuzhiyun {PA12203001_REG_CFG2, PA12203001_REG_CFG2_DEFAULT},
83*4882a593Smuzhiyun {PA12203001_REG_CFG3, PA12203001_REG_CFG3_DEFAULT},
84*4882a593Smuzhiyun {PA12203001_REG_PSET, PA12203001_PSCAN},
85*4882a593Smuzhiyun };
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun static IIO_CONST_ATTR(in_illuminance_scale_available,
88*4882a593Smuzhiyun "0.007629 0.061036 0.106813 0.473029");
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun static struct attribute *pa12203001_attrs[] = {
91*4882a593Smuzhiyun &iio_const_attr_in_illuminance_scale_available.dev_attr.attr,
92*4882a593Smuzhiyun NULL
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun static const struct attribute_group pa12203001_attr_group = {
96*4882a593Smuzhiyun .attrs = pa12203001_attrs,
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun static const struct iio_chan_spec pa12203001_channels[] = {
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun .type = IIO_LIGHT,
102*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
103*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE),
104*4882a593Smuzhiyun },
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun .type = IIO_PROXIMITY,
107*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun };
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun static const struct regmap_range pa12203001_volatile_regs_ranges[] = {
112*4882a593Smuzhiyun regmap_reg_range(PA12203001_REG_ADL, PA12203001_REG_ADL + 1),
113*4882a593Smuzhiyun regmap_reg_range(PA12203001_REG_PDH, PA12203001_REG_PDH),
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun static const struct regmap_access_table pa12203001_volatile_regs = {
117*4882a593Smuzhiyun .yes_ranges = pa12203001_volatile_regs_ranges,
118*4882a593Smuzhiyun .n_yes_ranges = ARRAY_SIZE(pa12203001_volatile_regs_ranges),
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun static const struct regmap_config pa12203001_regmap_config = {
122*4882a593Smuzhiyun .reg_bits = 8,
123*4882a593Smuzhiyun .val_bits = 8,
124*4882a593Smuzhiyun .max_register = PA12203001_REG_PSET,
125*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
126*4882a593Smuzhiyun .volatile_table = &pa12203001_volatile_regs,
127*4882a593Smuzhiyun };
128*4882a593Smuzhiyun
pa12203001_als_enable(struct pa12203001_data * data,u8 enable)129*4882a593Smuzhiyun static inline int pa12203001_als_enable(struct pa12203001_data *data, u8 enable)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun int ret;
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun ret = regmap_update_bits(data->map, PA12203001_REG_CFG0,
134*4882a593Smuzhiyun PA12203001_ALS_EN_MASK, enable);
135*4882a593Smuzhiyun if (ret < 0)
136*4882a593Smuzhiyun return ret;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun data->als_enabled = !!enable;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun return 0;
141*4882a593Smuzhiyun }
142*4882a593Smuzhiyun
pa12203001_px_enable(struct pa12203001_data * data,u8 enable)143*4882a593Smuzhiyun static inline int pa12203001_px_enable(struct pa12203001_data *data, u8 enable)
144*4882a593Smuzhiyun {
145*4882a593Smuzhiyun int ret;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun ret = regmap_update_bits(data->map, PA12203001_REG_CFG0,
148*4882a593Smuzhiyun PA12203001_PX_EN_MASK, enable);
149*4882a593Smuzhiyun if (ret < 0)
150*4882a593Smuzhiyun return ret;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun data->px_enabled = !!enable;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun return 0;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
pa12203001_set_power_state(struct pa12203001_data * data,bool on,u8 mask)157*4882a593Smuzhiyun static int pa12203001_set_power_state(struct pa12203001_data *data, bool on,
158*4882a593Smuzhiyun u8 mask)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun #ifdef CONFIG_PM
161*4882a593Smuzhiyun int ret;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun if (on && (mask & PA12203001_ALS_EN_MASK)) {
164*4882a593Smuzhiyun mutex_lock(&data->lock);
165*4882a593Smuzhiyun if (data->px_enabled) {
166*4882a593Smuzhiyun ret = pa12203001_als_enable(data,
167*4882a593Smuzhiyun PA12203001_ALS_EN_MASK);
168*4882a593Smuzhiyun if (ret < 0)
169*4882a593Smuzhiyun goto err;
170*4882a593Smuzhiyun } else {
171*4882a593Smuzhiyun data->als_needs_enable = true;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun mutex_unlock(&data->lock);
174*4882a593Smuzhiyun }
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun if (on && (mask & PA12203001_PX_EN_MASK)) {
177*4882a593Smuzhiyun mutex_lock(&data->lock);
178*4882a593Smuzhiyun if (data->als_enabled) {
179*4882a593Smuzhiyun ret = pa12203001_px_enable(data, PA12203001_PX_EN_MASK);
180*4882a593Smuzhiyun if (ret < 0)
181*4882a593Smuzhiyun goto err;
182*4882a593Smuzhiyun } else {
183*4882a593Smuzhiyun data->px_needs_enable = true;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun mutex_unlock(&data->lock);
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun if (on) {
189*4882a593Smuzhiyun ret = pm_runtime_get_sync(&data->client->dev);
190*4882a593Smuzhiyun if (ret < 0)
191*4882a593Smuzhiyun pm_runtime_put_noidle(&data->client->dev);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun } else {
194*4882a593Smuzhiyun pm_runtime_mark_last_busy(&data->client->dev);
195*4882a593Smuzhiyun ret = pm_runtime_put_autosuspend(&data->client->dev);
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun return ret;
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun err:
201*4882a593Smuzhiyun mutex_unlock(&data->lock);
202*4882a593Smuzhiyun return ret;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun #endif
205*4882a593Smuzhiyun return 0;
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun
pa12203001_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)208*4882a593Smuzhiyun static int pa12203001_read_raw(struct iio_dev *indio_dev,
209*4882a593Smuzhiyun struct iio_chan_spec const *chan, int *val,
210*4882a593Smuzhiyun int *val2, long mask)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun struct pa12203001_data *data = iio_priv(indio_dev);
213*4882a593Smuzhiyun int ret;
214*4882a593Smuzhiyun u8 dev_mask;
215*4882a593Smuzhiyun unsigned int reg_byte;
216*4882a593Smuzhiyun __le16 reg_word;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun switch (mask) {
219*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
220*4882a593Smuzhiyun switch (chan->type) {
221*4882a593Smuzhiyun case IIO_LIGHT:
222*4882a593Smuzhiyun dev_mask = PA12203001_ALS_EN_MASK;
223*4882a593Smuzhiyun ret = pa12203001_set_power_state(data, true, dev_mask);
224*4882a593Smuzhiyun if (ret < 0)
225*4882a593Smuzhiyun return ret;
226*4882a593Smuzhiyun /*
227*4882a593Smuzhiyun * ALS ADC value is stored in registers
228*4882a593Smuzhiyun * PA12203001_REG_ADL and in PA12203001_REG_ADL + 1.
229*4882a593Smuzhiyun */
230*4882a593Smuzhiyun ret = regmap_bulk_read(data->map, PA12203001_REG_ADL,
231*4882a593Smuzhiyun ®_word, 2);
232*4882a593Smuzhiyun if (ret < 0)
233*4882a593Smuzhiyun goto reg_err;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun *val = le16_to_cpu(reg_word);
236*4882a593Smuzhiyun ret = pa12203001_set_power_state(data, false, dev_mask);
237*4882a593Smuzhiyun if (ret < 0)
238*4882a593Smuzhiyun return ret;
239*4882a593Smuzhiyun break;
240*4882a593Smuzhiyun case IIO_PROXIMITY:
241*4882a593Smuzhiyun dev_mask = PA12203001_PX_EN_MASK;
242*4882a593Smuzhiyun ret = pa12203001_set_power_state(data, true, dev_mask);
243*4882a593Smuzhiyun if (ret < 0)
244*4882a593Smuzhiyun return ret;
245*4882a593Smuzhiyun ret = regmap_read(data->map, PA12203001_REG_PDH,
246*4882a593Smuzhiyun ®_byte);
247*4882a593Smuzhiyun if (ret < 0)
248*4882a593Smuzhiyun goto reg_err;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun *val = reg_byte;
251*4882a593Smuzhiyun ret = pa12203001_set_power_state(data, false, dev_mask);
252*4882a593Smuzhiyun if (ret < 0)
253*4882a593Smuzhiyun return ret;
254*4882a593Smuzhiyun break;
255*4882a593Smuzhiyun default:
256*4882a593Smuzhiyun return -EINVAL;
257*4882a593Smuzhiyun }
258*4882a593Smuzhiyun return IIO_VAL_INT;
259*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
260*4882a593Smuzhiyun ret = regmap_read(data->map, PA12203001_REG_CFG0, ®_byte);
261*4882a593Smuzhiyun if (ret < 0)
262*4882a593Smuzhiyun return ret;
263*4882a593Smuzhiyun *val = 0;
264*4882a593Smuzhiyun reg_byte = (reg_byte & PA12203001_AFSR_MASK);
265*4882a593Smuzhiyun *val2 = pa12203001_scales[reg_byte >> 4];
266*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
267*4882a593Smuzhiyun default:
268*4882a593Smuzhiyun return -EINVAL;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun reg_err:
272*4882a593Smuzhiyun pa12203001_set_power_state(data, false, dev_mask);
273*4882a593Smuzhiyun return ret;
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun
pa12203001_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)276*4882a593Smuzhiyun static int pa12203001_write_raw(struct iio_dev *indio_dev,
277*4882a593Smuzhiyun struct iio_chan_spec const *chan, int val,
278*4882a593Smuzhiyun int val2, long mask)
279*4882a593Smuzhiyun {
280*4882a593Smuzhiyun struct pa12203001_data *data = iio_priv(indio_dev);
281*4882a593Smuzhiyun int i, ret, new_val;
282*4882a593Smuzhiyun unsigned int reg_byte;
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun switch (mask) {
285*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
286*4882a593Smuzhiyun ret = regmap_read(data->map, PA12203001_REG_CFG0, ®_byte);
287*4882a593Smuzhiyun if (val != 0 || ret < 0)
288*4882a593Smuzhiyun return -EINVAL;
289*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(pa12203001_scales); i++) {
290*4882a593Smuzhiyun if (val2 == pa12203001_scales[i]) {
291*4882a593Smuzhiyun new_val = i << PA12203001_AFSR_SHIFT;
292*4882a593Smuzhiyun return regmap_update_bits(data->map,
293*4882a593Smuzhiyun PA12203001_REG_CFG0,
294*4882a593Smuzhiyun PA12203001_AFSR_MASK,
295*4882a593Smuzhiyun new_val);
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun }
298*4882a593Smuzhiyun break;
299*4882a593Smuzhiyun default:
300*4882a593Smuzhiyun break;
301*4882a593Smuzhiyun }
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun return -EINVAL;
304*4882a593Smuzhiyun }
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun static const struct iio_info pa12203001_info = {
307*4882a593Smuzhiyun .read_raw = pa12203001_read_raw,
308*4882a593Smuzhiyun .write_raw = pa12203001_write_raw,
309*4882a593Smuzhiyun .attrs = &pa12203001_attr_group,
310*4882a593Smuzhiyun };
311*4882a593Smuzhiyun
pa12203001_init(struct iio_dev * indio_dev)312*4882a593Smuzhiyun static int pa12203001_init(struct iio_dev *indio_dev)
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun struct pa12203001_data *data = iio_priv(indio_dev);
315*4882a593Smuzhiyun int i, ret;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(regvals); i++) {
318*4882a593Smuzhiyun ret = regmap_write(data->map, regvals[i].reg, regvals[i].val);
319*4882a593Smuzhiyun if (ret < 0)
320*4882a593Smuzhiyun return ret;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun return 0;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
pa12203001_power_chip(struct iio_dev * indio_dev,u8 state)326*4882a593Smuzhiyun static int pa12203001_power_chip(struct iio_dev *indio_dev, u8 state)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun struct pa12203001_data *data = iio_priv(indio_dev);
329*4882a593Smuzhiyun int ret;
330*4882a593Smuzhiyun
331*4882a593Smuzhiyun mutex_lock(&data->lock);
332*4882a593Smuzhiyun ret = pa12203001_als_enable(data, state);
333*4882a593Smuzhiyun if (ret < 0)
334*4882a593Smuzhiyun goto out;
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun ret = pa12203001_px_enable(data, state);
337*4882a593Smuzhiyun
338*4882a593Smuzhiyun out:
339*4882a593Smuzhiyun mutex_unlock(&data->lock);
340*4882a593Smuzhiyun return ret;
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun
pa12203001_probe(struct i2c_client * client,const struct i2c_device_id * id)343*4882a593Smuzhiyun static int pa12203001_probe(struct i2c_client *client,
344*4882a593Smuzhiyun const struct i2c_device_id *id)
345*4882a593Smuzhiyun {
346*4882a593Smuzhiyun struct pa12203001_data *data;
347*4882a593Smuzhiyun struct iio_dev *indio_dev;
348*4882a593Smuzhiyun int ret;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&client->dev,
351*4882a593Smuzhiyun sizeof(struct pa12203001_data));
352*4882a593Smuzhiyun if (!indio_dev)
353*4882a593Smuzhiyun return -ENOMEM;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun data = iio_priv(indio_dev);
356*4882a593Smuzhiyun i2c_set_clientdata(client, indio_dev);
357*4882a593Smuzhiyun data->client = client;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun data->map = devm_regmap_init_i2c(client, &pa12203001_regmap_config);
360*4882a593Smuzhiyun if (IS_ERR(data->map))
361*4882a593Smuzhiyun return PTR_ERR(data->map);
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun mutex_init(&data->lock);
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun indio_dev->info = &pa12203001_info;
366*4882a593Smuzhiyun indio_dev->name = PA12203001_DRIVER_NAME;
367*4882a593Smuzhiyun indio_dev->channels = pa12203001_channels;
368*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(pa12203001_channels);
369*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun ret = pa12203001_init(indio_dev);
372*4882a593Smuzhiyun if (ret < 0)
373*4882a593Smuzhiyun return ret;
374*4882a593Smuzhiyun
375*4882a593Smuzhiyun ret = pa12203001_power_chip(indio_dev, PA12203001_CHIP_ENABLE);
376*4882a593Smuzhiyun if (ret < 0)
377*4882a593Smuzhiyun return ret;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun ret = pm_runtime_set_active(&client->dev);
380*4882a593Smuzhiyun if (ret < 0)
381*4882a593Smuzhiyun goto out_err;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun pm_runtime_enable(&client->dev);
384*4882a593Smuzhiyun pm_runtime_set_autosuspend_delay(&client->dev,
385*4882a593Smuzhiyun PA12203001_SLEEP_DELAY_MS);
386*4882a593Smuzhiyun pm_runtime_use_autosuspend(&client->dev);
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
389*4882a593Smuzhiyun if (ret < 0)
390*4882a593Smuzhiyun goto out_err;
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun return 0;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun out_err:
395*4882a593Smuzhiyun pa12203001_power_chip(indio_dev, PA12203001_CHIP_DISABLE);
396*4882a593Smuzhiyun return ret;
397*4882a593Smuzhiyun }
398*4882a593Smuzhiyun
pa12203001_remove(struct i2c_client * client)399*4882a593Smuzhiyun static int pa12203001_remove(struct i2c_client *client)
400*4882a593Smuzhiyun {
401*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(client);
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun iio_device_unregister(indio_dev);
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun pm_runtime_disable(&client->dev);
406*4882a593Smuzhiyun pm_runtime_set_suspended(&client->dev);
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun return pa12203001_power_chip(indio_dev, PA12203001_CHIP_DISABLE);
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun #if defined(CONFIG_PM_SLEEP) || defined(CONFIG_PM)
pa12203001_suspend(struct device * dev)412*4882a593Smuzhiyun static int pa12203001_suspend(struct device *dev)
413*4882a593Smuzhiyun {
414*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun return pa12203001_power_chip(indio_dev, PA12203001_CHIP_DISABLE);
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun #endif
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
pa12203001_resume(struct device * dev)421*4882a593Smuzhiyun static int pa12203001_resume(struct device *dev)
422*4882a593Smuzhiyun {
423*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun return pa12203001_power_chip(indio_dev, PA12203001_CHIP_ENABLE);
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun #endif
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun #ifdef CONFIG_PM
pa12203001_runtime_resume(struct device * dev)430*4882a593Smuzhiyun static int pa12203001_runtime_resume(struct device *dev)
431*4882a593Smuzhiyun {
432*4882a593Smuzhiyun struct pa12203001_data *data;
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun data = iio_priv(i2c_get_clientdata(to_i2c_client(dev)));
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun mutex_lock(&data->lock);
437*4882a593Smuzhiyun if (data->als_needs_enable) {
438*4882a593Smuzhiyun pa12203001_als_enable(data, PA12203001_ALS_EN_MASK);
439*4882a593Smuzhiyun data->als_needs_enable = false;
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun if (data->px_needs_enable) {
442*4882a593Smuzhiyun pa12203001_px_enable(data, PA12203001_PX_EN_MASK);
443*4882a593Smuzhiyun data->px_needs_enable = false;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun mutex_unlock(&data->lock);
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun return 0;
448*4882a593Smuzhiyun }
449*4882a593Smuzhiyun #endif
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun static const struct dev_pm_ops pa12203001_pm_ops = {
452*4882a593Smuzhiyun SET_SYSTEM_SLEEP_PM_OPS(pa12203001_suspend, pa12203001_resume)
453*4882a593Smuzhiyun SET_RUNTIME_PM_OPS(pa12203001_suspend, pa12203001_runtime_resume, NULL)
454*4882a593Smuzhiyun };
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun static const struct acpi_device_id pa12203001_acpi_match[] = {
457*4882a593Smuzhiyun { "TXCPA122", 0},
458*4882a593Smuzhiyun {}
459*4882a593Smuzhiyun };
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, pa12203001_acpi_match);
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun static const struct i2c_device_id pa12203001_id[] = {
464*4882a593Smuzhiyun {"txcpa122", 0},
465*4882a593Smuzhiyun {}
466*4882a593Smuzhiyun };
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, pa12203001_id);
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun static struct i2c_driver pa12203001_driver = {
471*4882a593Smuzhiyun .driver = {
472*4882a593Smuzhiyun .name = PA12203001_DRIVER_NAME,
473*4882a593Smuzhiyun .pm = &pa12203001_pm_ops,
474*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(pa12203001_acpi_match),
475*4882a593Smuzhiyun },
476*4882a593Smuzhiyun .probe = pa12203001_probe,
477*4882a593Smuzhiyun .remove = pa12203001_remove,
478*4882a593Smuzhiyun .id_table = pa12203001_id,
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun };
481*4882a593Smuzhiyun module_i2c_driver(pa12203001_driver);
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun MODULE_AUTHOR("Adriana Reus <adriana.reus@intel.com>");
484*4882a593Smuzhiyun MODULE_DESCRIPTION("Driver for TXC PA12203001 Proximity and Light Sensor");
485*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
486