1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /**
3*4882a593Smuzhiyun * opt3001.c - Texas Instruments OPT3001 Light Sensor
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Andreas Dannenberg <dannenberg@ti.com>
8*4882a593Smuzhiyun * Based on previous work from: Felipe Balbi <balbi@ti.com>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/bitops.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun #include <linux/i2c.h>
15*4882a593Smuzhiyun #include <linux/interrupt.h>
16*4882a593Smuzhiyun #include <linux/irq.h>
17*4882a593Smuzhiyun #include <linux/kernel.h>
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/mod_devicetable.h>
20*4882a593Smuzhiyun #include <linux/mutex.h>
21*4882a593Smuzhiyun #include <linux/slab.h>
22*4882a593Smuzhiyun #include <linux/types.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include <linux/iio/events.h>
25*4882a593Smuzhiyun #include <linux/iio/iio.h>
26*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #define OPT3001_RESULT 0x00
29*4882a593Smuzhiyun #define OPT3001_CONFIGURATION 0x01
30*4882a593Smuzhiyun #define OPT3001_LOW_LIMIT 0x02
31*4882a593Smuzhiyun #define OPT3001_HIGH_LIMIT 0x03
32*4882a593Smuzhiyun #define OPT3001_MANUFACTURER_ID 0x7e
33*4882a593Smuzhiyun #define OPT3001_DEVICE_ID 0x7f
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define OPT3001_CONFIGURATION_RN_MASK (0xf << 12)
36*4882a593Smuzhiyun #define OPT3001_CONFIGURATION_RN_AUTO (0xc << 12)
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define OPT3001_CONFIGURATION_CT BIT(11)
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define OPT3001_CONFIGURATION_M_MASK (3 << 9)
41*4882a593Smuzhiyun #define OPT3001_CONFIGURATION_M_SHUTDOWN (0 << 9)
42*4882a593Smuzhiyun #define OPT3001_CONFIGURATION_M_SINGLE (1 << 9)
43*4882a593Smuzhiyun #define OPT3001_CONFIGURATION_M_CONTINUOUS (2 << 9) /* also 3 << 9 */
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #define OPT3001_CONFIGURATION_OVF BIT(8)
46*4882a593Smuzhiyun #define OPT3001_CONFIGURATION_CRF BIT(7)
47*4882a593Smuzhiyun #define OPT3001_CONFIGURATION_FH BIT(6)
48*4882a593Smuzhiyun #define OPT3001_CONFIGURATION_FL BIT(5)
49*4882a593Smuzhiyun #define OPT3001_CONFIGURATION_L BIT(4)
50*4882a593Smuzhiyun #define OPT3001_CONFIGURATION_POL BIT(3)
51*4882a593Smuzhiyun #define OPT3001_CONFIGURATION_ME BIT(2)
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #define OPT3001_CONFIGURATION_FC_MASK (3 << 0)
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* The end-of-conversion enable is located in the low-limit register */
56*4882a593Smuzhiyun #define OPT3001_LOW_LIMIT_EOC_ENABLE 0xc000
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define OPT3001_REG_EXPONENT(n) ((n) >> 12)
59*4882a593Smuzhiyun #define OPT3001_REG_MANTISSA(n) ((n) & 0xfff)
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #define OPT3001_INT_TIME_LONG 800000
62*4882a593Smuzhiyun #define OPT3001_INT_TIME_SHORT 100000
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /*
65*4882a593Smuzhiyun * Time to wait for conversion result to be ready. The device datasheet
66*4882a593Smuzhiyun * sect. 6.5 states results are ready after total integration time plus 3ms.
67*4882a593Smuzhiyun * This results in worst-case max values of 113ms or 883ms, respectively.
68*4882a593Smuzhiyun * Add some slack to be on the safe side.
69*4882a593Smuzhiyun */
70*4882a593Smuzhiyun #define OPT3001_RESULT_READY_SHORT 150
71*4882a593Smuzhiyun #define OPT3001_RESULT_READY_LONG 1000
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun struct opt3001 {
74*4882a593Smuzhiyun struct i2c_client *client;
75*4882a593Smuzhiyun struct device *dev;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun struct mutex lock;
78*4882a593Smuzhiyun bool ok_to_ignore_lock;
79*4882a593Smuzhiyun bool result_ready;
80*4882a593Smuzhiyun wait_queue_head_t result_ready_queue;
81*4882a593Smuzhiyun u16 result;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun u32 int_time;
84*4882a593Smuzhiyun u32 mode;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun u16 high_thresh_mantissa;
87*4882a593Smuzhiyun u16 low_thresh_mantissa;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun u8 high_thresh_exp;
90*4882a593Smuzhiyun u8 low_thresh_exp;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun bool use_irq;
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun struct opt3001_scale {
96*4882a593Smuzhiyun int val;
97*4882a593Smuzhiyun int val2;
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun static const struct opt3001_scale opt3001_scales[] = {
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun .val = 40,
103*4882a593Smuzhiyun .val2 = 950000,
104*4882a593Smuzhiyun },
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun .val = 81,
107*4882a593Smuzhiyun .val2 = 900000,
108*4882a593Smuzhiyun },
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun .val = 163,
111*4882a593Smuzhiyun .val2 = 800000,
112*4882a593Smuzhiyun },
113*4882a593Smuzhiyun {
114*4882a593Smuzhiyun .val = 327,
115*4882a593Smuzhiyun .val2 = 600000,
116*4882a593Smuzhiyun },
117*4882a593Smuzhiyun {
118*4882a593Smuzhiyun .val = 655,
119*4882a593Smuzhiyun .val2 = 200000,
120*4882a593Smuzhiyun },
121*4882a593Smuzhiyun {
122*4882a593Smuzhiyun .val = 1310,
123*4882a593Smuzhiyun .val2 = 400000,
124*4882a593Smuzhiyun },
125*4882a593Smuzhiyun {
126*4882a593Smuzhiyun .val = 2620,
127*4882a593Smuzhiyun .val2 = 800000,
128*4882a593Smuzhiyun },
129*4882a593Smuzhiyun {
130*4882a593Smuzhiyun .val = 5241,
131*4882a593Smuzhiyun .val2 = 600000,
132*4882a593Smuzhiyun },
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun .val = 10483,
135*4882a593Smuzhiyun .val2 = 200000,
136*4882a593Smuzhiyun },
137*4882a593Smuzhiyun {
138*4882a593Smuzhiyun .val = 20966,
139*4882a593Smuzhiyun .val2 = 400000,
140*4882a593Smuzhiyun },
141*4882a593Smuzhiyun {
142*4882a593Smuzhiyun .val = 83865,
143*4882a593Smuzhiyun .val2 = 600000,
144*4882a593Smuzhiyun },
145*4882a593Smuzhiyun };
146*4882a593Smuzhiyun
opt3001_find_scale(const struct opt3001 * opt,int val,int val2,u8 * exponent)147*4882a593Smuzhiyun static int opt3001_find_scale(const struct opt3001 *opt, int val,
148*4882a593Smuzhiyun int val2, u8 *exponent)
149*4882a593Smuzhiyun {
150*4882a593Smuzhiyun int i;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun for (i = 0; i < ARRAY_SIZE(opt3001_scales); i++) {
153*4882a593Smuzhiyun const struct opt3001_scale *scale = &opt3001_scales[i];
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun /*
156*4882a593Smuzhiyun * Combine the integer and micro parts for comparison
157*4882a593Smuzhiyun * purposes. Use milli lux precision to avoid 32-bit integer
158*4882a593Smuzhiyun * overflows.
159*4882a593Smuzhiyun */
160*4882a593Smuzhiyun if ((val * 1000 + val2 / 1000) <=
161*4882a593Smuzhiyun (scale->val * 1000 + scale->val2 / 1000)) {
162*4882a593Smuzhiyun *exponent = i;
163*4882a593Smuzhiyun return 0;
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun }
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun return -EINVAL;
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun
opt3001_to_iio_ret(struct opt3001 * opt,u8 exponent,u16 mantissa,int * val,int * val2)170*4882a593Smuzhiyun static void opt3001_to_iio_ret(struct opt3001 *opt, u8 exponent,
171*4882a593Smuzhiyun u16 mantissa, int *val, int *val2)
172*4882a593Smuzhiyun {
173*4882a593Smuzhiyun int lux;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun lux = 10 * (mantissa << exponent);
176*4882a593Smuzhiyun *val = lux / 1000;
177*4882a593Smuzhiyun *val2 = (lux - (*val * 1000)) * 1000;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun
opt3001_set_mode(struct opt3001 * opt,u16 * reg,u16 mode)180*4882a593Smuzhiyun static void opt3001_set_mode(struct opt3001 *opt, u16 *reg, u16 mode)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun *reg &= ~OPT3001_CONFIGURATION_M_MASK;
183*4882a593Smuzhiyun *reg |= mode;
184*4882a593Smuzhiyun opt->mode = mode;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun static IIO_CONST_ATTR_INT_TIME_AVAIL("0.1 0.8");
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun static struct attribute *opt3001_attributes[] = {
190*4882a593Smuzhiyun &iio_const_attr_integration_time_available.dev_attr.attr,
191*4882a593Smuzhiyun NULL
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun static const struct attribute_group opt3001_attribute_group = {
195*4882a593Smuzhiyun .attrs = opt3001_attributes,
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun static const struct iio_event_spec opt3001_event_spec[] = {
199*4882a593Smuzhiyun {
200*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
201*4882a593Smuzhiyun .dir = IIO_EV_DIR_RISING,
202*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_VALUE) |
203*4882a593Smuzhiyun BIT(IIO_EV_INFO_ENABLE),
204*4882a593Smuzhiyun },
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
207*4882a593Smuzhiyun .dir = IIO_EV_DIR_FALLING,
208*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_VALUE) |
209*4882a593Smuzhiyun BIT(IIO_EV_INFO_ENABLE),
210*4882a593Smuzhiyun },
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun static const struct iio_chan_spec opt3001_channels[] = {
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun .type = IIO_LIGHT,
216*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
217*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_INT_TIME),
218*4882a593Smuzhiyun .event_spec = opt3001_event_spec,
219*4882a593Smuzhiyun .num_event_specs = ARRAY_SIZE(opt3001_event_spec),
220*4882a593Smuzhiyun },
221*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(1),
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun
opt3001_get_lux(struct opt3001 * opt,int * val,int * val2)224*4882a593Smuzhiyun static int opt3001_get_lux(struct opt3001 *opt, int *val, int *val2)
225*4882a593Smuzhiyun {
226*4882a593Smuzhiyun int ret;
227*4882a593Smuzhiyun u16 mantissa;
228*4882a593Smuzhiyun u16 reg;
229*4882a593Smuzhiyun u8 exponent;
230*4882a593Smuzhiyun u16 value;
231*4882a593Smuzhiyun long timeout;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun if (opt->use_irq) {
234*4882a593Smuzhiyun /*
235*4882a593Smuzhiyun * Enable the end-of-conversion interrupt mechanism. Note that
236*4882a593Smuzhiyun * doing so will overwrite the low-level limit value however we
237*4882a593Smuzhiyun * will restore this value later on.
238*4882a593Smuzhiyun */
239*4882a593Smuzhiyun ret = i2c_smbus_write_word_swapped(opt->client,
240*4882a593Smuzhiyun OPT3001_LOW_LIMIT,
241*4882a593Smuzhiyun OPT3001_LOW_LIMIT_EOC_ENABLE);
242*4882a593Smuzhiyun if (ret < 0) {
243*4882a593Smuzhiyun dev_err(opt->dev, "failed to write register %02x\n",
244*4882a593Smuzhiyun OPT3001_LOW_LIMIT);
245*4882a593Smuzhiyun return ret;
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun /* Allow IRQ to access the device despite lock being set */
249*4882a593Smuzhiyun opt->ok_to_ignore_lock = true;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun /* Reset data-ready indicator flag */
253*4882a593Smuzhiyun opt->result_ready = false;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun /* Configure for single-conversion mode and start a new conversion */
256*4882a593Smuzhiyun ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
257*4882a593Smuzhiyun if (ret < 0) {
258*4882a593Smuzhiyun dev_err(opt->dev, "failed to read register %02x\n",
259*4882a593Smuzhiyun OPT3001_CONFIGURATION);
260*4882a593Smuzhiyun goto err;
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun reg = ret;
264*4882a593Smuzhiyun opt3001_set_mode(opt, ®, OPT3001_CONFIGURATION_M_SINGLE);
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
267*4882a593Smuzhiyun reg);
268*4882a593Smuzhiyun if (ret < 0) {
269*4882a593Smuzhiyun dev_err(opt->dev, "failed to write register %02x\n",
270*4882a593Smuzhiyun OPT3001_CONFIGURATION);
271*4882a593Smuzhiyun goto err;
272*4882a593Smuzhiyun }
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun if (opt->use_irq) {
275*4882a593Smuzhiyun /* Wait for the IRQ to indicate the conversion is complete */
276*4882a593Smuzhiyun ret = wait_event_timeout(opt->result_ready_queue,
277*4882a593Smuzhiyun opt->result_ready,
278*4882a593Smuzhiyun msecs_to_jiffies(OPT3001_RESULT_READY_LONG));
279*4882a593Smuzhiyun if (ret == 0)
280*4882a593Smuzhiyun return -ETIMEDOUT;
281*4882a593Smuzhiyun } else {
282*4882a593Smuzhiyun /* Sleep for result ready time */
283*4882a593Smuzhiyun timeout = (opt->int_time == OPT3001_INT_TIME_SHORT) ?
284*4882a593Smuzhiyun OPT3001_RESULT_READY_SHORT : OPT3001_RESULT_READY_LONG;
285*4882a593Smuzhiyun msleep(timeout);
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun /* Check result ready flag */
288*4882a593Smuzhiyun ret = i2c_smbus_read_word_swapped(opt->client,
289*4882a593Smuzhiyun OPT3001_CONFIGURATION);
290*4882a593Smuzhiyun if (ret < 0) {
291*4882a593Smuzhiyun dev_err(opt->dev, "failed to read register %02x\n",
292*4882a593Smuzhiyun OPT3001_CONFIGURATION);
293*4882a593Smuzhiyun goto err;
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun if (!(ret & OPT3001_CONFIGURATION_CRF)) {
297*4882a593Smuzhiyun ret = -ETIMEDOUT;
298*4882a593Smuzhiyun goto err;
299*4882a593Smuzhiyun }
300*4882a593Smuzhiyun
301*4882a593Smuzhiyun /* Obtain value */
302*4882a593Smuzhiyun ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_RESULT);
303*4882a593Smuzhiyun if (ret < 0) {
304*4882a593Smuzhiyun dev_err(opt->dev, "failed to read register %02x\n",
305*4882a593Smuzhiyun OPT3001_RESULT);
306*4882a593Smuzhiyun goto err;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun opt->result = ret;
309*4882a593Smuzhiyun opt->result_ready = true;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun err:
313*4882a593Smuzhiyun if (opt->use_irq)
314*4882a593Smuzhiyun /* Disallow IRQ to access the device while lock is active */
315*4882a593Smuzhiyun opt->ok_to_ignore_lock = false;
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun if (ret < 0)
318*4882a593Smuzhiyun return ret;
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun if (opt->use_irq) {
321*4882a593Smuzhiyun /*
322*4882a593Smuzhiyun * Disable the end-of-conversion interrupt mechanism by
323*4882a593Smuzhiyun * restoring the low-level limit value (clearing
324*4882a593Smuzhiyun * OPT3001_LOW_LIMIT_EOC_ENABLE). Note that selectively clearing
325*4882a593Smuzhiyun * those enable bits would affect the actual limit value due to
326*4882a593Smuzhiyun * bit-overlap and therefore can't be done.
327*4882a593Smuzhiyun */
328*4882a593Smuzhiyun value = (opt->low_thresh_exp << 12) | opt->low_thresh_mantissa;
329*4882a593Smuzhiyun ret = i2c_smbus_write_word_swapped(opt->client,
330*4882a593Smuzhiyun OPT3001_LOW_LIMIT,
331*4882a593Smuzhiyun value);
332*4882a593Smuzhiyun if (ret < 0) {
333*4882a593Smuzhiyun dev_err(opt->dev, "failed to write register %02x\n",
334*4882a593Smuzhiyun OPT3001_LOW_LIMIT);
335*4882a593Smuzhiyun return ret;
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun exponent = OPT3001_REG_EXPONENT(opt->result);
340*4882a593Smuzhiyun mantissa = OPT3001_REG_MANTISSA(opt->result);
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun opt3001_to_iio_ret(opt, exponent, mantissa, val, val2);
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun
opt3001_get_int_time(struct opt3001 * opt,int * val,int * val2)347*4882a593Smuzhiyun static int opt3001_get_int_time(struct opt3001 *opt, int *val, int *val2)
348*4882a593Smuzhiyun {
349*4882a593Smuzhiyun *val = 0;
350*4882a593Smuzhiyun *val2 = opt->int_time;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun
opt3001_set_int_time(struct opt3001 * opt,int time)355*4882a593Smuzhiyun static int opt3001_set_int_time(struct opt3001 *opt, int time)
356*4882a593Smuzhiyun {
357*4882a593Smuzhiyun int ret;
358*4882a593Smuzhiyun u16 reg;
359*4882a593Smuzhiyun
360*4882a593Smuzhiyun ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
361*4882a593Smuzhiyun if (ret < 0) {
362*4882a593Smuzhiyun dev_err(opt->dev, "failed to read register %02x\n",
363*4882a593Smuzhiyun OPT3001_CONFIGURATION);
364*4882a593Smuzhiyun return ret;
365*4882a593Smuzhiyun }
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun reg = ret;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun switch (time) {
370*4882a593Smuzhiyun case OPT3001_INT_TIME_SHORT:
371*4882a593Smuzhiyun reg &= ~OPT3001_CONFIGURATION_CT;
372*4882a593Smuzhiyun opt->int_time = OPT3001_INT_TIME_SHORT;
373*4882a593Smuzhiyun break;
374*4882a593Smuzhiyun case OPT3001_INT_TIME_LONG:
375*4882a593Smuzhiyun reg |= OPT3001_CONFIGURATION_CT;
376*4882a593Smuzhiyun opt->int_time = OPT3001_INT_TIME_LONG;
377*4882a593Smuzhiyun break;
378*4882a593Smuzhiyun default:
379*4882a593Smuzhiyun return -EINVAL;
380*4882a593Smuzhiyun }
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun return i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
383*4882a593Smuzhiyun reg);
384*4882a593Smuzhiyun }
385*4882a593Smuzhiyun
opt3001_read_raw(struct iio_dev * iio,struct iio_chan_spec const * chan,int * val,int * val2,long mask)386*4882a593Smuzhiyun static int opt3001_read_raw(struct iio_dev *iio,
387*4882a593Smuzhiyun struct iio_chan_spec const *chan, int *val, int *val2,
388*4882a593Smuzhiyun long mask)
389*4882a593Smuzhiyun {
390*4882a593Smuzhiyun struct opt3001 *opt = iio_priv(iio);
391*4882a593Smuzhiyun int ret;
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun if (opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS)
394*4882a593Smuzhiyun return -EBUSY;
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun if (chan->type != IIO_LIGHT)
397*4882a593Smuzhiyun return -EINVAL;
398*4882a593Smuzhiyun
399*4882a593Smuzhiyun mutex_lock(&opt->lock);
400*4882a593Smuzhiyun
401*4882a593Smuzhiyun switch (mask) {
402*4882a593Smuzhiyun case IIO_CHAN_INFO_PROCESSED:
403*4882a593Smuzhiyun ret = opt3001_get_lux(opt, val, val2);
404*4882a593Smuzhiyun break;
405*4882a593Smuzhiyun case IIO_CHAN_INFO_INT_TIME:
406*4882a593Smuzhiyun ret = opt3001_get_int_time(opt, val, val2);
407*4882a593Smuzhiyun break;
408*4882a593Smuzhiyun default:
409*4882a593Smuzhiyun ret = -EINVAL;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun mutex_unlock(&opt->lock);
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun return ret;
415*4882a593Smuzhiyun }
416*4882a593Smuzhiyun
opt3001_write_raw(struct iio_dev * iio,struct iio_chan_spec const * chan,int val,int val2,long mask)417*4882a593Smuzhiyun static int opt3001_write_raw(struct iio_dev *iio,
418*4882a593Smuzhiyun struct iio_chan_spec const *chan, int val, int val2,
419*4882a593Smuzhiyun long mask)
420*4882a593Smuzhiyun {
421*4882a593Smuzhiyun struct opt3001 *opt = iio_priv(iio);
422*4882a593Smuzhiyun int ret;
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun if (opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS)
425*4882a593Smuzhiyun return -EBUSY;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun if (chan->type != IIO_LIGHT)
428*4882a593Smuzhiyun return -EINVAL;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun if (mask != IIO_CHAN_INFO_INT_TIME)
431*4882a593Smuzhiyun return -EINVAL;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun if (val != 0)
434*4882a593Smuzhiyun return -EINVAL;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun mutex_lock(&opt->lock);
437*4882a593Smuzhiyun ret = opt3001_set_int_time(opt, val2);
438*4882a593Smuzhiyun mutex_unlock(&opt->lock);
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun return ret;
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun
opt3001_read_event_value(struct iio_dev * iio,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)443*4882a593Smuzhiyun static int opt3001_read_event_value(struct iio_dev *iio,
444*4882a593Smuzhiyun const struct iio_chan_spec *chan, enum iio_event_type type,
445*4882a593Smuzhiyun enum iio_event_direction dir, enum iio_event_info info,
446*4882a593Smuzhiyun int *val, int *val2)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun struct opt3001 *opt = iio_priv(iio);
449*4882a593Smuzhiyun int ret = IIO_VAL_INT_PLUS_MICRO;
450*4882a593Smuzhiyun
451*4882a593Smuzhiyun mutex_lock(&opt->lock);
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun switch (dir) {
454*4882a593Smuzhiyun case IIO_EV_DIR_RISING:
455*4882a593Smuzhiyun opt3001_to_iio_ret(opt, opt->high_thresh_exp,
456*4882a593Smuzhiyun opt->high_thresh_mantissa, val, val2);
457*4882a593Smuzhiyun break;
458*4882a593Smuzhiyun case IIO_EV_DIR_FALLING:
459*4882a593Smuzhiyun opt3001_to_iio_ret(opt, opt->low_thresh_exp,
460*4882a593Smuzhiyun opt->low_thresh_mantissa, val, val2);
461*4882a593Smuzhiyun break;
462*4882a593Smuzhiyun default:
463*4882a593Smuzhiyun ret = -EINVAL;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun mutex_unlock(&opt->lock);
467*4882a593Smuzhiyun
468*4882a593Smuzhiyun return ret;
469*4882a593Smuzhiyun }
470*4882a593Smuzhiyun
opt3001_write_event_value(struct iio_dev * iio,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)471*4882a593Smuzhiyun static int opt3001_write_event_value(struct iio_dev *iio,
472*4882a593Smuzhiyun const struct iio_chan_spec *chan, enum iio_event_type type,
473*4882a593Smuzhiyun enum iio_event_direction dir, enum iio_event_info info,
474*4882a593Smuzhiyun int val, int val2)
475*4882a593Smuzhiyun {
476*4882a593Smuzhiyun struct opt3001 *opt = iio_priv(iio);
477*4882a593Smuzhiyun int ret;
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun u16 mantissa;
480*4882a593Smuzhiyun u16 value;
481*4882a593Smuzhiyun u16 reg;
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun u8 exponent;
484*4882a593Smuzhiyun
485*4882a593Smuzhiyun if (val < 0)
486*4882a593Smuzhiyun return -EINVAL;
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun mutex_lock(&opt->lock);
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun ret = opt3001_find_scale(opt, val, val2, &exponent);
491*4882a593Smuzhiyun if (ret < 0) {
492*4882a593Smuzhiyun dev_err(opt->dev, "can't find scale for %d.%06u\n", val, val2);
493*4882a593Smuzhiyun goto err;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun mantissa = (((val * 1000) + (val2 / 1000)) / 10) >> exponent;
497*4882a593Smuzhiyun value = (exponent << 12) | mantissa;
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun switch (dir) {
500*4882a593Smuzhiyun case IIO_EV_DIR_RISING:
501*4882a593Smuzhiyun reg = OPT3001_HIGH_LIMIT;
502*4882a593Smuzhiyun opt->high_thresh_mantissa = mantissa;
503*4882a593Smuzhiyun opt->high_thresh_exp = exponent;
504*4882a593Smuzhiyun break;
505*4882a593Smuzhiyun case IIO_EV_DIR_FALLING:
506*4882a593Smuzhiyun reg = OPT3001_LOW_LIMIT;
507*4882a593Smuzhiyun opt->low_thresh_mantissa = mantissa;
508*4882a593Smuzhiyun opt->low_thresh_exp = exponent;
509*4882a593Smuzhiyun break;
510*4882a593Smuzhiyun default:
511*4882a593Smuzhiyun ret = -EINVAL;
512*4882a593Smuzhiyun goto err;
513*4882a593Smuzhiyun }
514*4882a593Smuzhiyun
515*4882a593Smuzhiyun ret = i2c_smbus_write_word_swapped(opt->client, reg, value);
516*4882a593Smuzhiyun if (ret < 0) {
517*4882a593Smuzhiyun dev_err(opt->dev, "failed to write register %02x\n", reg);
518*4882a593Smuzhiyun goto err;
519*4882a593Smuzhiyun }
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun err:
522*4882a593Smuzhiyun mutex_unlock(&opt->lock);
523*4882a593Smuzhiyun
524*4882a593Smuzhiyun return ret;
525*4882a593Smuzhiyun }
526*4882a593Smuzhiyun
opt3001_read_event_config(struct iio_dev * iio,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)527*4882a593Smuzhiyun static int opt3001_read_event_config(struct iio_dev *iio,
528*4882a593Smuzhiyun const struct iio_chan_spec *chan, enum iio_event_type type,
529*4882a593Smuzhiyun enum iio_event_direction dir)
530*4882a593Smuzhiyun {
531*4882a593Smuzhiyun struct opt3001 *opt = iio_priv(iio);
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun return opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS;
534*4882a593Smuzhiyun }
535*4882a593Smuzhiyun
opt3001_write_event_config(struct iio_dev * iio,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)536*4882a593Smuzhiyun static int opt3001_write_event_config(struct iio_dev *iio,
537*4882a593Smuzhiyun const struct iio_chan_spec *chan, enum iio_event_type type,
538*4882a593Smuzhiyun enum iio_event_direction dir, int state)
539*4882a593Smuzhiyun {
540*4882a593Smuzhiyun struct opt3001 *opt = iio_priv(iio);
541*4882a593Smuzhiyun int ret;
542*4882a593Smuzhiyun u16 mode;
543*4882a593Smuzhiyun u16 reg;
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun if (state && opt->mode == OPT3001_CONFIGURATION_M_CONTINUOUS)
546*4882a593Smuzhiyun return 0;
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun if (!state && opt->mode == OPT3001_CONFIGURATION_M_SHUTDOWN)
549*4882a593Smuzhiyun return 0;
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun mutex_lock(&opt->lock);
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun mode = state ? OPT3001_CONFIGURATION_M_CONTINUOUS
554*4882a593Smuzhiyun : OPT3001_CONFIGURATION_M_SHUTDOWN;
555*4882a593Smuzhiyun
556*4882a593Smuzhiyun ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
557*4882a593Smuzhiyun if (ret < 0) {
558*4882a593Smuzhiyun dev_err(opt->dev, "failed to read register %02x\n",
559*4882a593Smuzhiyun OPT3001_CONFIGURATION);
560*4882a593Smuzhiyun goto err;
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun
563*4882a593Smuzhiyun reg = ret;
564*4882a593Smuzhiyun opt3001_set_mode(opt, ®, mode);
565*4882a593Smuzhiyun
566*4882a593Smuzhiyun ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
567*4882a593Smuzhiyun reg);
568*4882a593Smuzhiyun if (ret < 0) {
569*4882a593Smuzhiyun dev_err(opt->dev, "failed to write register %02x\n",
570*4882a593Smuzhiyun OPT3001_CONFIGURATION);
571*4882a593Smuzhiyun goto err;
572*4882a593Smuzhiyun }
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun err:
575*4882a593Smuzhiyun mutex_unlock(&opt->lock);
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun return ret;
578*4882a593Smuzhiyun }
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun static const struct iio_info opt3001_info = {
581*4882a593Smuzhiyun .attrs = &opt3001_attribute_group,
582*4882a593Smuzhiyun .read_raw = opt3001_read_raw,
583*4882a593Smuzhiyun .write_raw = opt3001_write_raw,
584*4882a593Smuzhiyun .read_event_value = opt3001_read_event_value,
585*4882a593Smuzhiyun .write_event_value = opt3001_write_event_value,
586*4882a593Smuzhiyun .read_event_config = opt3001_read_event_config,
587*4882a593Smuzhiyun .write_event_config = opt3001_write_event_config,
588*4882a593Smuzhiyun };
589*4882a593Smuzhiyun
opt3001_read_id(struct opt3001 * opt)590*4882a593Smuzhiyun static int opt3001_read_id(struct opt3001 *opt)
591*4882a593Smuzhiyun {
592*4882a593Smuzhiyun char manufacturer[2];
593*4882a593Smuzhiyun u16 device_id;
594*4882a593Smuzhiyun int ret;
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_MANUFACTURER_ID);
597*4882a593Smuzhiyun if (ret < 0) {
598*4882a593Smuzhiyun dev_err(opt->dev, "failed to read register %02x\n",
599*4882a593Smuzhiyun OPT3001_MANUFACTURER_ID);
600*4882a593Smuzhiyun return ret;
601*4882a593Smuzhiyun }
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun manufacturer[0] = ret >> 8;
604*4882a593Smuzhiyun manufacturer[1] = ret & 0xff;
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_DEVICE_ID);
607*4882a593Smuzhiyun if (ret < 0) {
608*4882a593Smuzhiyun dev_err(opt->dev, "failed to read register %02x\n",
609*4882a593Smuzhiyun OPT3001_DEVICE_ID);
610*4882a593Smuzhiyun return ret;
611*4882a593Smuzhiyun }
612*4882a593Smuzhiyun
613*4882a593Smuzhiyun device_id = ret;
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun dev_info(opt->dev, "Found %c%c OPT%04x\n", manufacturer[0],
616*4882a593Smuzhiyun manufacturer[1], device_id);
617*4882a593Smuzhiyun
618*4882a593Smuzhiyun return 0;
619*4882a593Smuzhiyun }
620*4882a593Smuzhiyun
opt3001_configure(struct opt3001 * opt)621*4882a593Smuzhiyun static int opt3001_configure(struct opt3001 *opt)
622*4882a593Smuzhiyun {
623*4882a593Smuzhiyun int ret;
624*4882a593Smuzhiyun u16 reg;
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
627*4882a593Smuzhiyun if (ret < 0) {
628*4882a593Smuzhiyun dev_err(opt->dev, "failed to read register %02x\n",
629*4882a593Smuzhiyun OPT3001_CONFIGURATION);
630*4882a593Smuzhiyun return ret;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun
633*4882a593Smuzhiyun reg = ret;
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun /* Enable automatic full-scale setting mode */
636*4882a593Smuzhiyun reg &= ~OPT3001_CONFIGURATION_RN_MASK;
637*4882a593Smuzhiyun reg |= OPT3001_CONFIGURATION_RN_AUTO;
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun /* Reflect status of the device's integration time setting */
640*4882a593Smuzhiyun if (reg & OPT3001_CONFIGURATION_CT)
641*4882a593Smuzhiyun opt->int_time = OPT3001_INT_TIME_LONG;
642*4882a593Smuzhiyun else
643*4882a593Smuzhiyun opt->int_time = OPT3001_INT_TIME_SHORT;
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun /* Ensure device is in shutdown initially */
646*4882a593Smuzhiyun opt3001_set_mode(opt, ®, OPT3001_CONFIGURATION_M_SHUTDOWN);
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun /* Configure for latched window-style comparison operation */
649*4882a593Smuzhiyun reg |= OPT3001_CONFIGURATION_L;
650*4882a593Smuzhiyun reg &= ~OPT3001_CONFIGURATION_POL;
651*4882a593Smuzhiyun reg &= ~OPT3001_CONFIGURATION_ME;
652*4882a593Smuzhiyun reg &= ~OPT3001_CONFIGURATION_FC_MASK;
653*4882a593Smuzhiyun
654*4882a593Smuzhiyun ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
655*4882a593Smuzhiyun reg);
656*4882a593Smuzhiyun if (ret < 0) {
657*4882a593Smuzhiyun dev_err(opt->dev, "failed to write register %02x\n",
658*4882a593Smuzhiyun OPT3001_CONFIGURATION);
659*4882a593Smuzhiyun return ret;
660*4882a593Smuzhiyun }
661*4882a593Smuzhiyun
662*4882a593Smuzhiyun ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_LOW_LIMIT);
663*4882a593Smuzhiyun if (ret < 0) {
664*4882a593Smuzhiyun dev_err(opt->dev, "failed to read register %02x\n",
665*4882a593Smuzhiyun OPT3001_LOW_LIMIT);
666*4882a593Smuzhiyun return ret;
667*4882a593Smuzhiyun }
668*4882a593Smuzhiyun
669*4882a593Smuzhiyun opt->low_thresh_mantissa = OPT3001_REG_MANTISSA(ret);
670*4882a593Smuzhiyun opt->low_thresh_exp = OPT3001_REG_EXPONENT(ret);
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_HIGH_LIMIT);
673*4882a593Smuzhiyun if (ret < 0) {
674*4882a593Smuzhiyun dev_err(opt->dev, "failed to read register %02x\n",
675*4882a593Smuzhiyun OPT3001_HIGH_LIMIT);
676*4882a593Smuzhiyun return ret;
677*4882a593Smuzhiyun }
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun opt->high_thresh_mantissa = OPT3001_REG_MANTISSA(ret);
680*4882a593Smuzhiyun opt->high_thresh_exp = OPT3001_REG_EXPONENT(ret);
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun return 0;
683*4882a593Smuzhiyun }
684*4882a593Smuzhiyun
opt3001_irq(int irq,void * _iio)685*4882a593Smuzhiyun static irqreturn_t opt3001_irq(int irq, void *_iio)
686*4882a593Smuzhiyun {
687*4882a593Smuzhiyun struct iio_dev *iio = _iio;
688*4882a593Smuzhiyun struct opt3001 *opt = iio_priv(iio);
689*4882a593Smuzhiyun int ret;
690*4882a593Smuzhiyun bool wake_result_ready_queue = false;
691*4882a593Smuzhiyun
692*4882a593Smuzhiyun if (!opt->ok_to_ignore_lock)
693*4882a593Smuzhiyun mutex_lock(&opt->lock);
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
696*4882a593Smuzhiyun if (ret < 0) {
697*4882a593Smuzhiyun dev_err(opt->dev, "failed to read register %02x\n",
698*4882a593Smuzhiyun OPT3001_CONFIGURATION);
699*4882a593Smuzhiyun goto out;
700*4882a593Smuzhiyun }
701*4882a593Smuzhiyun
702*4882a593Smuzhiyun if ((ret & OPT3001_CONFIGURATION_M_MASK) ==
703*4882a593Smuzhiyun OPT3001_CONFIGURATION_M_CONTINUOUS) {
704*4882a593Smuzhiyun if (ret & OPT3001_CONFIGURATION_FH)
705*4882a593Smuzhiyun iio_push_event(iio,
706*4882a593Smuzhiyun IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
707*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
708*4882a593Smuzhiyun IIO_EV_DIR_RISING),
709*4882a593Smuzhiyun iio_get_time_ns(iio));
710*4882a593Smuzhiyun if (ret & OPT3001_CONFIGURATION_FL)
711*4882a593Smuzhiyun iio_push_event(iio,
712*4882a593Smuzhiyun IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
713*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
714*4882a593Smuzhiyun IIO_EV_DIR_FALLING),
715*4882a593Smuzhiyun iio_get_time_ns(iio));
716*4882a593Smuzhiyun } else if (ret & OPT3001_CONFIGURATION_CRF) {
717*4882a593Smuzhiyun ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_RESULT);
718*4882a593Smuzhiyun if (ret < 0) {
719*4882a593Smuzhiyun dev_err(opt->dev, "failed to read register %02x\n",
720*4882a593Smuzhiyun OPT3001_RESULT);
721*4882a593Smuzhiyun goto out;
722*4882a593Smuzhiyun }
723*4882a593Smuzhiyun opt->result = ret;
724*4882a593Smuzhiyun opt->result_ready = true;
725*4882a593Smuzhiyun wake_result_ready_queue = true;
726*4882a593Smuzhiyun }
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun out:
729*4882a593Smuzhiyun if (!opt->ok_to_ignore_lock)
730*4882a593Smuzhiyun mutex_unlock(&opt->lock);
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun if (wake_result_ready_queue)
733*4882a593Smuzhiyun wake_up(&opt->result_ready_queue);
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun return IRQ_HANDLED;
736*4882a593Smuzhiyun }
737*4882a593Smuzhiyun
opt3001_probe(struct i2c_client * client,const struct i2c_device_id * id)738*4882a593Smuzhiyun static int opt3001_probe(struct i2c_client *client,
739*4882a593Smuzhiyun const struct i2c_device_id *id)
740*4882a593Smuzhiyun {
741*4882a593Smuzhiyun struct device *dev = &client->dev;
742*4882a593Smuzhiyun
743*4882a593Smuzhiyun struct iio_dev *iio;
744*4882a593Smuzhiyun struct opt3001 *opt;
745*4882a593Smuzhiyun int irq = client->irq;
746*4882a593Smuzhiyun int ret;
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun iio = devm_iio_device_alloc(dev, sizeof(*opt));
749*4882a593Smuzhiyun if (!iio)
750*4882a593Smuzhiyun return -ENOMEM;
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun opt = iio_priv(iio);
753*4882a593Smuzhiyun opt->client = client;
754*4882a593Smuzhiyun opt->dev = dev;
755*4882a593Smuzhiyun
756*4882a593Smuzhiyun mutex_init(&opt->lock);
757*4882a593Smuzhiyun init_waitqueue_head(&opt->result_ready_queue);
758*4882a593Smuzhiyun i2c_set_clientdata(client, iio);
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun ret = opt3001_read_id(opt);
761*4882a593Smuzhiyun if (ret)
762*4882a593Smuzhiyun return ret;
763*4882a593Smuzhiyun
764*4882a593Smuzhiyun ret = opt3001_configure(opt);
765*4882a593Smuzhiyun if (ret)
766*4882a593Smuzhiyun return ret;
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun iio->name = client->name;
769*4882a593Smuzhiyun iio->channels = opt3001_channels;
770*4882a593Smuzhiyun iio->num_channels = ARRAY_SIZE(opt3001_channels);
771*4882a593Smuzhiyun iio->modes = INDIO_DIRECT_MODE;
772*4882a593Smuzhiyun iio->info = &opt3001_info;
773*4882a593Smuzhiyun
774*4882a593Smuzhiyun ret = devm_iio_device_register(dev, iio);
775*4882a593Smuzhiyun if (ret) {
776*4882a593Smuzhiyun dev_err(dev, "failed to register IIO device\n");
777*4882a593Smuzhiyun return ret;
778*4882a593Smuzhiyun }
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun /* Make use of INT pin only if valid IRQ no. is given */
781*4882a593Smuzhiyun if (irq > 0) {
782*4882a593Smuzhiyun ret = request_threaded_irq(irq, NULL, opt3001_irq,
783*4882a593Smuzhiyun IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
784*4882a593Smuzhiyun "opt3001", iio);
785*4882a593Smuzhiyun if (ret) {
786*4882a593Smuzhiyun dev_err(dev, "failed to request IRQ #%d\n", irq);
787*4882a593Smuzhiyun return ret;
788*4882a593Smuzhiyun }
789*4882a593Smuzhiyun opt->use_irq = true;
790*4882a593Smuzhiyun } else {
791*4882a593Smuzhiyun dev_dbg(opt->dev, "enabling interrupt-less operation\n");
792*4882a593Smuzhiyun }
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun return 0;
795*4882a593Smuzhiyun }
796*4882a593Smuzhiyun
opt3001_remove(struct i2c_client * client)797*4882a593Smuzhiyun static int opt3001_remove(struct i2c_client *client)
798*4882a593Smuzhiyun {
799*4882a593Smuzhiyun struct iio_dev *iio = i2c_get_clientdata(client);
800*4882a593Smuzhiyun struct opt3001 *opt = iio_priv(iio);
801*4882a593Smuzhiyun int ret;
802*4882a593Smuzhiyun u16 reg;
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun if (opt->use_irq)
805*4882a593Smuzhiyun free_irq(client->irq, iio);
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun ret = i2c_smbus_read_word_swapped(opt->client, OPT3001_CONFIGURATION);
808*4882a593Smuzhiyun if (ret < 0) {
809*4882a593Smuzhiyun dev_err(opt->dev, "failed to read register %02x\n",
810*4882a593Smuzhiyun OPT3001_CONFIGURATION);
811*4882a593Smuzhiyun return ret;
812*4882a593Smuzhiyun }
813*4882a593Smuzhiyun
814*4882a593Smuzhiyun reg = ret;
815*4882a593Smuzhiyun opt3001_set_mode(opt, ®, OPT3001_CONFIGURATION_M_SHUTDOWN);
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun ret = i2c_smbus_write_word_swapped(opt->client, OPT3001_CONFIGURATION,
818*4882a593Smuzhiyun reg);
819*4882a593Smuzhiyun if (ret < 0) {
820*4882a593Smuzhiyun dev_err(opt->dev, "failed to write register %02x\n",
821*4882a593Smuzhiyun OPT3001_CONFIGURATION);
822*4882a593Smuzhiyun return ret;
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun return 0;
826*4882a593Smuzhiyun }
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun static const struct i2c_device_id opt3001_id[] = {
829*4882a593Smuzhiyun { "opt3001", 0 },
830*4882a593Smuzhiyun { } /* Terminating Entry */
831*4882a593Smuzhiyun };
832*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, opt3001_id);
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun static const struct of_device_id opt3001_of_match[] = {
835*4882a593Smuzhiyun { .compatible = "ti,opt3001" },
836*4882a593Smuzhiyun { }
837*4882a593Smuzhiyun };
838*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, opt3001_of_match);
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun static struct i2c_driver opt3001_driver = {
841*4882a593Smuzhiyun .probe = opt3001_probe,
842*4882a593Smuzhiyun .remove = opt3001_remove,
843*4882a593Smuzhiyun .id_table = opt3001_id,
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun .driver = {
846*4882a593Smuzhiyun .name = "opt3001",
847*4882a593Smuzhiyun .of_match_table = opt3001_of_match,
848*4882a593Smuzhiyun },
849*4882a593Smuzhiyun };
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun module_i2c_driver(opt3001_driver);
852*4882a593Smuzhiyun
853*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
854*4882a593Smuzhiyun MODULE_AUTHOR("Andreas Dannenberg <dannenberg@ti.com>");
855*4882a593Smuzhiyun MODULE_DESCRIPTION("Texas Instruments OPT3001 Light Sensor Driver");
856