1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * max44009.c - Support for MAX44009 Ambient Light Sensor
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (c) 2019 Robert Eshleman <bobbyeshleman@gmail.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX44009.pdf
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * TODO: Support continuous mode and configuring from manual mode to
10*4882a593Smuzhiyun * automatic mode.
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * Default I2C address: 0x4a
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/kernel.h>
17*4882a593Smuzhiyun #include <linux/bits.h>
18*4882a593Smuzhiyun #include <linux/i2c.h>
19*4882a593Smuzhiyun #include <linux/iio/events.h>
20*4882a593Smuzhiyun #include <linux/iio/iio.h>
21*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
22*4882a593Smuzhiyun #include <linux/interrupt.h>
23*4882a593Smuzhiyun #include <linux/module.h>
24*4882a593Smuzhiyun #include <linux/util_macros.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define MAX44009_DRV_NAME "max44009"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* Registers in datasheet order */
29*4882a593Smuzhiyun #define MAX44009_REG_INT_STATUS 0x0
30*4882a593Smuzhiyun #define MAX44009_REG_INT_EN 0x1
31*4882a593Smuzhiyun #define MAX44009_REG_CFG 0x2
32*4882a593Smuzhiyun #define MAX44009_REG_LUX_HI 0x3
33*4882a593Smuzhiyun #define MAX44009_REG_LUX_LO 0x4
34*4882a593Smuzhiyun #define MAX44009_REG_UPPER_THR 0x5
35*4882a593Smuzhiyun #define MAX44009_REG_LOWER_THR 0x6
36*4882a593Smuzhiyun #define MAX44009_REG_THR_TIMER 0x7
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define MAX44009_CFG_TIM_MASK GENMASK(2, 0)
39*4882a593Smuzhiyun #define MAX44009_CFG_MAN_MODE_MASK BIT(6)
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* The maximum rising threshold for the max44009 */
42*4882a593Smuzhiyun #define MAX44009_MAXIMUM_THRESHOLD 7520256
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define MAX44009_THRESH_EXP_MASK (0xf << 4)
45*4882a593Smuzhiyun #define MAX44009_THRESH_EXP_RSHIFT 4
46*4882a593Smuzhiyun #define MAX44009_THRESH_MANT_LSHIFT 4
47*4882a593Smuzhiyun #define MAX44009_THRESH_MANT_MASK 0xf
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #define MAX44009_UPPER_THR_MINIMUM 15
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* The max44009 always scales raw readings by 0.045 and is non-configurable */
52*4882a593Smuzhiyun #define MAX44009_SCALE_NUMERATOR 45
53*4882a593Smuzhiyun #define MAX44009_SCALE_DENOMINATOR 1000
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* The fixed-point fractional multiplier for de-scaling threshold values */
56*4882a593Smuzhiyun #define MAX44009_FRACT_MULT 1000000
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun static const u32 max44009_int_time_ns_array[] = {
59*4882a593Smuzhiyun 800000000,
60*4882a593Smuzhiyun 400000000,
61*4882a593Smuzhiyun 200000000,
62*4882a593Smuzhiyun 100000000,
63*4882a593Smuzhiyun 50000000, /* Manual mode only */
64*4882a593Smuzhiyun 25000000, /* Manual mode only */
65*4882a593Smuzhiyun 12500000, /* Manual mode only */
66*4882a593Smuzhiyun 6250000, /* Manual mode only */
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun static const char max44009_int_time_str[] =
70*4882a593Smuzhiyun "0.8 "
71*4882a593Smuzhiyun "0.4 "
72*4882a593Smuzhiyun "0.2 "
73*4882a593Smuzhiyun "0.1 "
74*4882a593Smuzhiyun "0.05 "
75*4882a593Smuzhiyun "0.025 "
76*4882a593Smuzhiyun "0.0125 "
77*4882a593Smuzhiyun "0.00625";
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun struct max44009_data {
80*4882a593Smuzhiyun struct i2c_client *client;
81*4882a593Smuzhiyun struct mutex lock;
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun static const struct iio_event_spec max44009_event_spec[] = {
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
87*4882a593Smuzhiyun .dir = IIO_EV_DIR_RISING,
88*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_VALUE) |
89*4882a593Smuzhiyun BIT(IIO_EV_INFO_ENABLE),
90*4882a593Smuzhiyun },
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
93*4882a593Smuzhiyun .dir = IIO_EV_DIR_FALLING,
94*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_VALUE) |
95*4882a593Smuzhiyun BIT(IIO_EV_INFO_ENABLE),
96*4882a593Smuzhiyun },
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun static const struct iio_chan_spec max44009_channels[] = {
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun .type = IIO_LIGHT,
102*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED) |
103*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_INT_TIME),
104*4882a593Smuzhiyun .event_spec = max44009_event_spec,
105*4882a593Smuzhiyun .num_event_specs = ARRAY_SIZE(max44009_event_spec),
106*4882a593Smuzhiyun },
107*4882a593Smuzhiyun };
108*4882a593Smuzhiyun
max44009_read_int_time(struct max44009_data * data)109*4882a593Smuzhiyun static int max44009_read_int_time(struct max44009_data *data)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun int ret = i2c_smbus_read_byte_data(data->client, MAX44009_REG_CFG);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun if (ret < 0)
115*4882a593Smuzhiyun return ret;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun return max44009_int_time_ns_array[ret & MAX44009_CFG_TIM_MASK];
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
max44009_write_int_time(struct max44009_data * data,int val,int val2)120*4882a593Smuzhiyun static int max44009_write_int_time(struct max44009_data *data,
121*4882a593Smuzhiyun int val, int val2)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun struct i2c_client *client = data->client;
124*4882a593Smuzhiyun int ret, int_time, config;
125*4882a593Smuzhiyun s64 ns;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun ns = val * NSEC_PER_SEC + val2;
128*4882a593Smuzhiyun int_time = find_closest_descending(
129*4882a593Smuzhiyun ns,
130*4882a593Smuzhiyun max44009_int_time_ns_array,
131*4882a593Smuzhiyun ARRAY_SIZE(max44009_int_time_ns_array));
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(client, MAX44009_REG_CFG);
134*4882a593Smuzhiyun if (ret < 0)
135*4882a593Smuzhiyun return ret;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun config = ret;
138*4882a593Smuzhiyun config &= int_time;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun /*
141*4882a593Smuzhiyun * To set the integration time, the device must also be in manual
142*4882a593Smuzhiyun * mode.
143*4882a593Smuzhiyun */
144*4882a593Smuzhiyun config |= MAX44009_CFG_MAN_MODE_MASK;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun return i2c_smbus_write_byte_data(client, MAX44009_REG_CFG, config);
147*4882a593Smuzhiyun }
148*4882a593Smuzhiyun
max44009_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)149*4882a593Smuzhiyun static int max44009_write_raw(struct iio_dev *indio_dev,
150*4882a593Smuzhiyun struct iio_chan_spec const *chan, int val,
151*4882a593Smuzhiyun int val2, long mask)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun struct max44009_data *data = iio_priv(indio_dev);
154*4882a593Smuzhiyun int ret;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun if (mask == IIO_CHAN_INFO_INT_TIME && chan->type == IIO_LIGHT) {
157*4882a593Smuzhiyun mutex_lock(&data->lock);
158*4882a593Smuzhiyun ret = max44009_write_int_time(data, val, val2);
159*4882a593Smuzhiyun mutex_unlock(&data->lock);
160*4882a593Smuzhiyun return ret;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun return -EINVAL;
163*4882a593Smuzhiyun }
164*4882a593Smuzhiyun
max44009_write_raw_get_fmt(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,long mask)165*4882a593Smuzhiyun static int max44009_write_raw_get_fmt(struct iio_dev *indio_dev,
166*4882a593Smuzhiyun struct iio_chan_spec const *chan,
167*4882a593Smuzhiyun long mask)
168*4882a593Smuzhiyun {
169*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_NANO;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
max44009_lux_raw(u8 hi,u8 lo)172*4882a593Smuzhiyun static int max44009_lux_raw(u8 hi, u8 lo)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun int mantissa;
175*4882a593Smuzhiyun int exponent;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun /*
178*4882a593Smuzhiyun * The mantissa consists of the low nibble of the Lux High Byte
179*4882a593Smuzhiyun * and the low nibble of the Lux Low Byte.
180*4882a593Smuzhiyun */
181*4882a593Smuzhiyun mantissa = ((hi & 0xf) << 4) | (lo & 0xf);
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun /* The exponent byte is just the upper nibble of the Lux High Byte */
184*4882a593Smuzhiyun exponent = (hi >> 4) & 0xf;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun /*
187*4882a593Smuzhiyun * The exponent value is base 2 to the power of the raw exponent byte.
188*4882a593Smuzhiyun */
189*4882a593Smuzhiyun exponent = 1 << exponent;
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun return exponent * mantissa;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun #define MAX44009_READ_LUX_XFER_LEN (4)
195*4882a593Smuzhiyun
max44009_read_lux_raw(struct max44009_data * data)196*4882a593Smuzhiyun static int max44009_read_lux_raw(struct max44009_data *data)
197*4882a593Smuzhiyun {
198*4882a593Smuzhiyun int ret;
199*4882a593Smuzhiyun u8 hireg = MAX44009_REG_LUX_HI;
200*4882a593Smuzhiyun u8 loreg = MAX44009_REG_LUX_LO;
201*4882a593Smuzhiyun u8 lo = 0;
202*4882a593Smuzhiyun u8 hi = 0;
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun struct i2c_msg msgs[] = {
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun .addr = data->client->addr,
207*4882a593Smuzhiyun .flags = 0,
208*4882a593Smuzhiyun .len = sizeof(hireg),
209*4882a593Smuzhiyun .buf = &hireg,
210*4882a593Smuzhiyun },
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun .addr = data->client->addr,
213*4882a593Smuzhiyun .flags = I2C_M_RD,
214*4882a593Smuzhiyun .len = sizeof(hi),
215*4882a593Smuzhiyun .buf = &hi,
216*4882a593Smuzhiyun },
217*4882a593Smuzhiyun {
218*4882a593Smuzhiyun .addr = data->client->addr,
219*4882a593Smuzhiyun .flags = 0,
220*4882a593Smuzhiyun .len = sizeof(loreg),
221*4882a593Smuzhiyun .buf = &loreg,
222*4882a593Smuzhiyun },
223*4882a593Smuzhiyun {
224*4882a593Smuzhiyun .addr = data->client->addr,
225*4882a593Smuzhiyun .flags = I2C_M_RD,
226*4882a593Smuzhiyun .len = sizeof(lo),
227*4882a593Smuzhiyun .buf = &lo,
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun /*
232*4882a593Smuzhiyun * Use i2c_transfer instead of smbus read because i2c_transfer
233*4882a593Smuzhiyun * does NOT use a stop bit between address write and data read.
234*4882a593Smuzhiyun * Using a stop bit causes disjoint upper/lower byte reads and
235*4882a593Smuzhiyun * reduces accuracy.
236*4882a593Smuzhiyun */
237*4882a593Smuzhiyun ret = i2c_transfer(data->client->adapter,
238*4882a593Smuzhiyun msgs, MAX44009_READ_LUX_XFER_LEN);
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun if (ret != MAX44009_READ_LUX_XFER_LEN)
241*4882a593Smuzhiyun return -EIO;
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun return max44009_lux_raw(hi, lo);
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
max44009_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)246*4882a593Smuzhiyun static int max44009_read_raw(struct iio_dev *indio_dev,
247*4882a593Smuzhiyun struct iio_chan_spec const *chan, int *val,
248*4882a593Smuzhiyun int *val2, long mask)
249*4882a593Smuzhiyun {
250*4882a593Smuzhiyun struct max44009_data *data = iio_priv(indio_dev);
251*4882a593Smuzhiyun int lux_raw;
252*4882a593Smuzhiyun int ret;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun switch (mask) {
255*4882a593Smuzhiyun case IIO_CHAN_INFO_PROCESSED:
256*4882a593Smuzhiyun switch (chan->type) {
257*4882a593Smuzhiyun case IIO_LIGHT:
258*4882a593Smuzhiyun ret = max44009_read_lux_raw(data);
259*4882a593Smuzhiyun if (ret < 0)
260*4882a593Smuzhiyun return ret;
261*4882a593Smuzhiyun lux_raw = ret;
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun *val = lux_raw * MAX44009_SCALE_NUMERATOR;
264*4882a593Smuzhiyun *val2 = MAX44009_SCALE_DENOMINATOR;
265*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL;
266*4882a593Smuzhiyun default:
267*4882a593Smuzhiyun return -EINVAL;
268*4882a593Smuzhiyun }
269*4882a593Smuzhiyun case IIO_CHAN_INFO_INT_TIME:
270*4882a593Smuzhiyun switch (chan->type) {
271*4882a593Smuzhiyun case IIO_LIGHT:
272*4882a593Smuzhiyun ret = max44009_read_int_time(data);
273*4882a593Smuzhiyun if (ret < 0)
274*4882a593Smuzhiyun return ret;
275*4882a593Smuzhiyun
276*4882a593Smuzhiyun *val2 = ret;
277*4882a593Smuzhiyun *val = 0;
278*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_NANO;
279*4882a593Smuzhiyun default:
280*4882a593Smuzhiyun return -EINVAL;
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun default:
283*4882a593Smuzhiyun return -EINVAL;
284*4882a593Smuzhiyun }
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun static IIO_CONST_ATTR(illuminance_integration_time_available,
288*4882a593Smuzhiyun max44009_int_time_str);
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun static struct attribute *max44009_attributes[] = {
291*4882a593Smuzhiyun &iio_const_attr_illuminance_integration_time_available.dev_attr.attr,
292*4882a593Smuzhiyun NULL,
293*4882a593Smuzhiyun };
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun static const struct attribute_group max44009_attribute_group = {
296*4882a593Smuzhiyun .attrs = max44009_attributes,
297*4882a593Smuzhiyun };
298*4882a593Smuzhiyun
max44009_threshold_byte_from_fraction(int integral,int fractional)299*4882a593Smuzhiyun static int max44009_threshold_byte_from_fraction(int integral, int fractional)
300*4882a593Smuzhiyun {
301*4882a593Smuzhiyun int mantissa, exp;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun if ((integral <= 0 && fractional <= 0) ||
304*4882a593Smuzhiyun integral > MAX44009_MAXIMUM_THRESHOLD ||
305*4882a593Smuzhiyun (integral == MAX44009_MAXIMUM_THRESHOLD && fractional != 0))
306*4882a593Smuzhiyun return -EINVAL;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun /* Reverse scaling of fixed-point integral */
309*4882a593Smuzhiyun mantissa = integral * MAX44009_SCALE_DENOMINATOR;
310*4882a593Smuzhiyun mantissa /= MAX44009_SCALE_NUMERATOR;
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun /* Reverse scaling of fixed-point fractional */
313*4882a593Smuzhiyun mantissa += fractional / MAX44009_FRACT_MULT *
314*4882a593Smuzhiyun (MAX44009_SCALE_DENOMINATOR / MAX44009_SCALE_NUMERATOR);
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun for (exp = 0; mantissa > 0xff; exp++)
317*4882a593Smuzhiyun mantissa >>= 1;
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun mantissa >>= 4;
320*4882a593Smuzhiyun mantissa &= 0xf;
321*4882a593Smuzhiyun exp <<= 4;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun return exp | mantissa;
324*4882a593Smuzhiyun }
325*4882a593Smuzhiyun
max44009_get_thr_reg(enum iio_event_direction dir)326*4882a593Smuzhiyun static int max44009_get_thr_reg(enum iio_event_direction dir)
327*4882a593Smuzhiyun {
328*4882a593Smuzhiyun switch (dir) {
329*4882a593Smuzhiyun case IIO_EV_DIR_RISING:
330*4882a593Smuzhiyun return MAX44009_REG_UPPER_THR;
331*4882a593Smuzhiyun case IIO_EV_DIR_FALLING:
332*4882a593Smuzhiyun return MAX44009_REG_LOWER_THR;
333*4882a593Smuzhiyun default:
334*4882a593Smuzhiyun return -EINVAL;
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun
max44009_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)338*4882a593Smuzhiyun static int max44009_write_event_value(struct iio_dev *indio_dev,
339*4882a593Smuzhiyun const struct iio_chan_spec *chan,
340*4882a593Smuzhiyun enum iio_event_type type,
341*4882a593Smuzhiyun enum iio_event_direction dir,
342*4882a593Smuzhiyun enum iio_event_info info,
343*4882a593Smuzhiyun int val, int val2)
344*4882a593Smuzhiyun {
345*4882a593Smuzhiyun struct max44009_data *data = iio_priv(indio_dev);
346*4882a593Smuzhiyun int reg, threshold;
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun if (info != IIO_EV_INFO_VALUE || chan->type != IIO_LIGHT)
349*4882a593Smuzhiyun return -EINVAL;
350*4882a593Smuzhiyun
351*4882a593Smuzhiyun threshold = max44009_threshold_byte_from_fraction(val, val2);
352*4882a593Smuzhiyun if (threshold < 0)
353*4882a593Smuzhiyun return threshold;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun reg = max44009_get_thr_reg(dir);
356*4882a593Smuzhiyun if (reg < 0)
357*4882a593Smuzhiyun return reg;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun return i2c_smbus_write_byte_data(data->client, reg, threshold);
360*4882a593Smuzhiyun }
361*4882a593Smuzhiyun
max44009_read_threshold(struct iio_dev * indio_dev,enum iio_event_direction dir)362*4882a593Smuzhiyun static int max44009_read_threshold(struct iio_dev *indio_dev,
363*4882a593Smuzhiyun enum iio_event_direction dir)
364*4882a593Smuzhiyun {
365*4882a593Smuzhiyun struct max44009_data *data = iio_priv(indio_dev);
366*4882a593Smuzhiyun int byte, reg;
367*4882a593Smuzhiyun int mantissa, exponent;
368*4882a593Smuzhiyun
369*4882a593Smuzhiyun reg = max44009_get_thr_reg(dir);
370*4882a593Smuzhiyun if (reg < 0)
371*4882a593Smuzhiyun return reg;
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun byte = i2c_smbus_read_byte_data(data->client, reg);
374*4882a593Smuzhiyun if (byte < 0)
375*4882a593Smuzhiyun return byte;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun mantissa = byte & MAX44009_THRESH_MANT_MASK;
378*4882a593Smuzhiyun mantissa <<= MAX44009_THRESH_MANT_LSHIFT;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun /*
381*4882a593Smuzhiyun * To get the upper threshold, always adds the minimum upper threshold
382*4882a593Smuzhiyun * value to the shifted byte value (see datasheet).
383*4882a593Smuzhiyun */
384*4882a593Smuzhiyun if (dir == IIO_EV_DIR_RISING)
385*4882a593Smuzhiyun mantissa += MAX44009_UPPER_THR_MINIMUM;
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun /*
388*4882a593Smuzhiyun * Exponent is base 2 to the power of the threshold exponent byte
389*4882a593Smuzhiyun * value
390*4882a593Smuzhiyun */
391*4882a593Smuzhiyun exponent = byte & MAX44009_THRESH_EXP_MASK;
392*4882a593Smuzhiyun exponent >>= MAX44009_THRESH_EXP_RSHIFT;
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun return (1 << exponent) * mantissa;
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun
max44009_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)397*4882a593Smuzhiyun static int max44009_read_event_value(struct iio_dev *indio_dev,
398*4882a593Smuzhiyun const struct iio_chan_spec *chan,
399*4882a593Smuzhiyun enum iio_event_type type,
400*4882a593Smuzhiyun enum iio_event_direction dir,
401*4882a593Smuzhiyun enum iio_event_info info,
402*4882a593Smuzhiyun int *val, int *val2)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun int ret;
405*4882a593Smuzhiyun int threshold;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun if (chan->type != IIO_LIGHT || type != IIO_EV_TYPE_THRESH)
408*4882a593Smuzhiyun return -EINVAL;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun ret = max44009_read_threshold(indio_dev, dir);
411*4882a593Smuzhiyun if (ret < 0)
412*4882a593Smuzhiyun return ret;
413*4882a593Smuzhiyun threshold = ret;
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun *val = threshold * MAX44009_SCALE_NUMERATOR;
416*4882a593Smuzhiyun *val2 = MAX44009_SCALE_DENOMINATOR;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL;
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun
max44009_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)421*4882a593Smuzhiyun static int max44009_write_event_config(struct iio_dev *indio_dev,
422*4882a593Smuzhiyun const struct iio_chan_spec *chan,
423*4882a593Smuzhiyun enum iio_event_type type,
424*4882a593Smuzhiyun enum iio_event_direction dir,
425*4882a593Smuzhiyun int state)
426*4882a593Smuzhiyun {
427*4882a593Smuzhiyun struct max44009_data *data = iio_priv(indio_dev);
428*4882a593Smuzhiyun int ret;
429*4882a593Smuzhiyun
430*4882a593Smuzhiyun if (chan->type != IIO_LIGHT || type != IIO_EV_TYPE_THRESH)
431*4882a593Smuzhiyun return -EINVAL;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client,
434*4882a593Smuzhiyun MAX44009_REG_INT_EN, state);
435*4882a593Smuzhiyun if (ret < 0)
436*4882a593Smuzhiyun return ret;
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun /*
439*4882a593Smuzhiyun * Set device to trigger interrupt immediately upon exceeding
440*4882a593Smuzhiyun * the threshold limit.
441*4882a593Smuzhiyun */
442*4882a593Smuzhiyun return i2c_smbus_write_byte_data(data->client,
443*4882a593Smuzhiyun MAX44009_REG_THR_TIMER, 0);
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun
max44009_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)446*4882a593Smuzhiyun static int max44009_read_event_config(struct iio_dev *indio_dev,
447*4882a593Smuzhiyun const struct iio_chan_spec *chan,
448*4882a593Smuzhiyun enum iio_event_type type,
449*4882a593Smuzhiyun enum iio_event_direction dir)
450*4882a593Smuzhiyun {
451*4882a593Smuzhiyun struct max44009_data *data = iio_priv(indio_dev);
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun if (chan->type != IIO_LIGHT || type != IIO_EV_TYPE_THRESH)
454*4882a593Smuzhiyun return -EINVAL;
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun return i2c_smbus_read_byte_data(data->client, MAX44009_REG_INT_EN);
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun
459*4882a593Smuzhiyun static const struct iio_info max44009_info = {
460*4882a593Smuzhiyun .read_raw = max44009_read_raw,
461*4882a593Smuzhiyun .write_raw = max44009_write_raw,
462*4882a593Smuzhiyun .write_raw_get_fmt = max44009_write_raw_get_fmt,
463*4882a593Smuzhiyun .read_event_value = max44009_read_event_value,
464*4882a593Smuzhiyun .read_event_config = max44009_read_event_config,
465*4882a593Smuzhiyun .write_event_value = max44009_write_event_value,
466*4882a593Smuzhiyun .write_event_config = max44009_write_event_config,
467*4882a593Smuzhiyun .attrs = &max44009_attribute_group,
468*4882a593Smuzhiyun };
469*4882a593Smuzhiyun
max44009_threaded_irq_handler(int irq,void * p)470*4882a593Smuzhiyun static irqreturn_t max44009_threaded_irq_handler(int irq, void *p)
471*4882a593Smuzhiyun {
472*4882a593Smuzhiyun struct iio_dev *indio_dev = p;
473*4882a593Smuzhiyun struct max44009_data *data = iio_priv(indio_dev);
474*4882a593Smuzhiyun int ret;
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client, MAX44009_REG_INT_STATUS);
477*4882a593Smuzhiyun if (ret) {
478*4882a593Smuzhiyun iio_push_event(indio_dev,
479*4882a593Smuzhiyun IIO_UNMOD_EVENT_CODE(IIO_LIGHT, 0,
480*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
481*4882a593Smuzhiyun IIO_EV_DIR_EITHER),
482*4882a593Smuzhiyun iio_get_time_ns(indio_dev));
483*4882a593Smuzhiyun
484*4882a593Smuzhiyun return IRQ_HANDLED;
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun return IRQ_NONE;
488*4882a593Smuzhiyun }
489*4882a593Smuzhiyun
max44009_probe(struct i2c_client * client,const struct i2c_device_id * id)490*4882a593Smuzhiyun static int max44009_probe(struct i2c_client *client,
491*4882a593Smuzhiyun const struct i2c_device_id *id)
492*4882a593Smuzhiyun {
493*4882a593Smuzhiyun struct max44009_data *data;
494*4882a593Smuzhiyun struct iio_dev *indio_dev;
495*4882a593Smuzhiyun int ret;
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
498*4882a593Smuzhiyun if (!indio_dev)
499*4882a593Smuzhiyun return -ENOMEM;
500*4882a593Smuzhiyun
501*4882a593Smuzhiyun data = iio_priv(indio_dev);
502*4882a593Smuzhiyun i2c_set_clientdata(client, indio_dev);
503*4882a593Smuzhiyun data->client = client;
504*4882a593Smuzhiyun indio_dev->info = &max44009_info;
505*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
506*4882a593Smuzhiyun indio_dev->name = MAX44009_DRV_NAME;
507*4882a593Smuzhiyun indio_dev->channels = max44009_channels;
508*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(max44009_channels);
509*4882a593Smuzhiyun mutex_init(&data->lock);
510*4882a593Smuzhiyun
511*4882a593Smuzhiyun /* Clear any stale interrupt bit */
512*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(client, MAX44009_REG_CFG);
513*4882a593Smuzhiyun if (ret < 0)
514*4882a593Smuzhiyun return ret;
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun if (client->irq > 0) {
517*4882a593Smuzhiyun ret = devm_request_threaded_irq(&client->dev, client->irq,
518*4882a593Smuzhiyun NULL,
519*4882a593Smuzhiyun max44009_threaded_irq_handler,
520*4882a593Smuzhiyun IRQF_TRIGGER_FALLING |
521*4882a593Smuzhiyun IRQF_ONESHOT | IRQF_SHARED,
522*4882a593Smuzhiyun "max44009_event",
523*4882a593Smuzhiyun indio_dev);
524*4882a593Smuzhiyun if (ret < 0)
525*4882a593Smuzhiyun return ret;
526*4882a593Smuzhiyun }
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun return devm_iio_device_register(&client->dev, indio_dev);
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun
531*4882a593Smuzhiyun static const struct i2c_device_id max44009_id[] = {
532*4882a593Smuzhiyun { "max44009", 0 },
533*4882a593Smuzhiyun { }
534*4882a593Smuzhiyun };
535*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, max44009_id);
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun static struct i2c_driver max44009_driver = {
538*4882a593Smuzhiyun .driver = {
539*4882a593Smuzhiyun .name = MAX44009_DRV_NAME,
540*4882a593Smuzhiyun },
541*4882a593Smuzhiyun .probe = max44009_probe,
542*4882a593Smuzhiyun .id_table = max44009_id,
543*4882a593Smuzhiyun };
544*4882a593Smuzhiyun module_i2c_driver(max44009_driver);
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun static const struct of_device_id max44009_of_match[] = {
547*4882a593Smuzhiyun { .compatible = "maxim,max44009" },
548*4882a593Smuzhiyun { }
549*4882a593Smuzhiyun };
550*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, max44009_of_match);
551*4882a593Smuzhiyun
552*4882a593Smuzhiyun MODULE_AUTHOR("Robert Eshleman <bobbyeshleman@gmail.com>");
553*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
554*4882a593Smuzhiyun MODULE_DESCRIPTION("MAX44009 ambient light sensor driver");
555