xref: /OK3568_Linux_fs/kernel/drivers/iio/light/as73211.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Support for AMS AS73211 JENCOLOR(R) Digital XYZ Sensor
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Author: Christian Eggers <ceggers@arri.de>
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (c) 2020 ARRI Lighting
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Color light sensor with 16-bit channels for x, y, z and temperature);
10*4882a593Smuzhiyun  * 7-bit I2C slave address 0x74 .. 0x77.
11*4882a593Smuzhiyun  *
12*4882a593Smuzhiyun  * Datasheet: https://ams.com/documents/20143/36005/AS73211_DS000556_3-01.pdf
13*4882a593Smuzhiyun  */
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <linux/bitfield.h>
16*4882a593Smuzhiyun #include <linux/completion.h>
17*4882a593Smuzhiyun #include <linux/delay.h>
18*4882a593Smuzhiyun #include <linux/i2c.h>
19*4882a593Smuzhiyun #include <linux/iio/buffer.h>
20*4882a593Smuzhiyun #include <linux/iio/iio.h>
21*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
22*4882a593Smuzhiyun #include <linux/iio/trigger_consumer.h>
23*4882a593Smuzhiyun #include <linux/iio/triggered_buffer.h>
24*4882a593Smuzhiyun #include <linux/module.h>
25*4882a593Smuzhiyun #include <linux/mutex.h>
26*4882a593Smuzhiyun #include <linux/pm.h>
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #define HZ_PER_KHZ 1000
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define AS73211_DRV_NAME "as73211"
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /* AS73211 configuration registers */
33*4882a593Smuzhiyun #define AS73211_REG_OSR    0x0
34*4882a593Smuzhiyun #define AS73211_REG_AGEN   0x2
35*4882a593Smuzhiyun #define AS73211_REG_CREG1  0x6
36*4882a593Smuzhiyun #define AS73211_REG_CREG2  0x7
37*4882a593Smuzhiyun #define AS73211_REG_CREG3  0x8
38*4882a593Smuzhiyun 
39*4882a593Smuzhiyun /* AS73211 output register bank */
40*4882a593Smuzhiyun #define AS73211_OUT_OSR_STATUS    0
41*4882a593Smuzhiyun #define AS73211_OUT_TEMP          1
42*4882a593Smuzhiyun #define AS73211_OUT_MRES1         2
43*4882a593Smuzhiyun #define AS73211_OUT_MRES2         3
44*4882a593Smuzhiyun #define AS73211_OUT_MRES3         4
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define AS73211_OSR_SS            BIT(7)
47*4882a593Smuzhiyun #define AS73211_OSR_PD            BIT(6)
48*4882a593Smuzhiyun #define AS73211_OSR_SW_RES        BIT(3)
49*4882a593Smuzhiyun #define AS73211_OSR_DOS_MASK      GENMASK(2, 0)
50*4882a593Smuzhiyun #define AS73211_OSR_DOS_CONFIG    FIELD_PREP(AS73211_OSR_DOS_MASK, 0x2)
51*4882a593Smuzhiyun #define AS73211_OSR_DOS_MEASURE   FIELD_PREP(AS73211_OSR_DOS_MASK, 0x3)
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #define AS73211_AGEN_DEVID_MASK   GENMASK(7, 4)
54*4882a593Smuzhiyun #define AS73211_AGEN_DEVID(x)     FIELD_PREP(AS73211_AGEN_DEVID_MASK, (x))
55*4882a593Smuzhiyun #define AS73211_AGEN_MUT_MASK     GENMASK(3, 0)
56*4882a593Smuzhiyun #define AS73211_AGEN_MUT(x)       FIELD_PREP(AS73211_AGEN_MUT_MASK, (x))
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define AS73211_CREG1_GAIN_MASK   GENMASK(7, 4)
59*4882a593Smuzhiyun #define AS73211_CREG1_GAIN_1      11
60*4882a593Smuzhiyun #define AS73211_CREG1_TIME_MASK   GENMASK(3, 0)
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #define AS73211_CREG3_CCLK_MASK   GENMASK(1, 0)
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define AS73211_OSR_STATUS_OUTCONVOF  BIT(15)
65*4882a593Smuzhiyun #define AS73211_OSR_STATUS_MRESOF     BIT(14)
66*4882a593Smuzhiyun #define AS73211_OSR_STATUS_ADCOF      BIT(13)
67*4882a593Smuzhiyun #define AS73211_OSR_STATUS_LDATA      BIT(12)
68*4882a593Smuzhiyun #define AS73211_OSR_STATUS_NDATA      BIT(11)
69*4882a593Smuzhiyun #define AS73211_OSR_STATUS_NOTREADY   BIT(10)
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun #define AS73211_SAMPLE_FREQ_BASE      1024000
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun #define AS73211_SAMPLE_TIME_NUM       15
74*4882a593Smuzhiyun #define AS73211_SAMPLE_TIME_MAX_MS    BIT(AS73211_SAMPLE_TIME_NUM - 1)
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /* Available sample frequencies are 1.024MHz multiplied by powers of two. */
77*4882a593Smuzhiyun static const int as73211_samp_freq_avail[] = {
78*4882a593Smuzhiyun 	AS73211_SAMPLE_FREQ_BASE * 1,
79*4882a593Smuzhiyun 	AS73211_SAMPLE_FREQ_BASE * 2,
80*4882a593Smuzhiyun 	AS73211_SAMPLE_FREQ_BASE * 4,
81*4882a593Smuzhiyun 	AS73211_SAMPLE_FREQ_BASE * 8,
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun static const int as73211_hardwaregain_avail[] = {
85*4882a593Smuzhiyun 	1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048,
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun /**
89*4882a593Smuzhiyun  * struct as73211_data - Instance data for one AS73211
90*4882a593Smuzhiyun  * @client: I2C client.
91*4882a593Smuzhiyun  * @osr:    Cached Operational State Register.
92*4882a593Smuzhiyun  * @creg1:  Cached Configuration Register 1.
93*4882a593Smuzhiyun  * @creg2:  Cached Configuration Register 2.
94*4882a593Smuzhiyun  * @creg3:  Cached Configuration Register 3.
95*4882a593Smuzhiyun  * @mutex:  Keeps cached registers in sync with the device.
96*4882a593Smuzhiyun  * @completion: Completion to wait for interrupt.
97*4882a593Smuzhiyun  * @int_time_avail: Available integration times (depend on sampling frequency).
98*4882a593Smuzhiyun  */
99*4882a593Smuzhiyun struct as73211_data {
100*4882a593Smuzhiyun 	struct i2c_client *client;
101*4882a593Smuzhiyun 	u8 osr;
102*4882a593Smuzhiyun 	u8 creg1;
103*4882a593Smuzhiyun 	u8 creg2;
104*4882a593Smuzhiyun 	u8 creg3;
105*4882a593Smuzhiyun 	struct mutex mutex;
106*4882a593Smuzhiyun 	struct completion completion;
107*4882a593Smuzhiyun 	int int_time_avail[AS73211_SAMPLE_TIME_NUM * 2];
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun #define AS73211_COLOR_CHANNEL(_color, _si, _addr) { \
111*4882a593Smuzhiyun 	.type = IIO_INTENSITY, \
112*4882a593Smuzhiyun 	.modified = 1, \
113*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), \
114*4882a593Smuzhiyun 	.info_mask_shared_by_type = \
115*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
116*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_HARDWAREGAIN) | \
117*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_INT_TIME), \
118*4882a593Smuzhiyun 	.info_mask_shared_by_type_available = \
119*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
120*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_HARDWAREGAIN) | \
121*4882a593Smuzhiyun 		BIT(IIO_CHAN_INFO_INT_TIME), \
122*4882a593Smuzhiyun 	.channel2 = IIO_MOD_##_color, \
123*4882a593Smuzhiyun 	.address = _addr, \
124*4882a593Smuzhiyun 	.scan_index = _si, \
125*4882a593Smuzhiyun 	.scan_type = { \
126*4882a593Smuzhiyun 		.sign = 'u', \
127*4882a593Smuzhiyun 		.realbits = 16, \
128*4882a593Smuzhiyun 		.storagebits = 16, \
129*4882a593Smuzhiyun 		.endianness = IIO_LE, \
130*4882a593Smuzhiyun 	}, \
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun #define AS73211_OFFSET_TEMP_INT    (-66)
134*4882a593Smuzhiyun #define AS73211_OFFSET_TEMP_MICRO  900000
135*4882a593Smuzhiyun #define AS73211_SCALE_TEMP_INT     0
136*4882a593Smuzhiyun #define AS73211_SCALE_TEMP_MICRO   50000
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun #define AS73211_SCALE_X 277071108  /* nW/m^2 */
139*4882a593Smuzhiyun #define AS73211_SCALE_Y 298384270  /* nW/m^2 */
140*4882a593Smuzhiyun #define AS73211_SCALE_Z 160241927  /* nW/m^2 */
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun /* Channel order MUST match devices result register order */
143*4882a593Smuzhiyun #define AS73211_SCAN_INDEX_TEMP 0
144*4882a593Smuzhiyun #define AS73211_SCAN_INDEX_X    1
145*4882a593Smuzhiyun #define AS73211_SCAN_INDEX_Y    2
146*4882a593Smuzhiyun #define AS73211_SCAN_INDEX_Z    3
147*4882a593Smuzhiyun #define AS73211_SCAN_INDEX_TS   4
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun #define AS73211_SCAN_MASK_COLOR ( \
150*4882a593Smuzhiyun 	BIT(AS73211_SCAN_INDEX_X) |   \
151*4882a593Smuzhiyun 	BIT(AS73211_SCAN_INDEX_Y) |   \
152*4882a593Smuzhiyun 	BIT(AS73211_SCAN_INDEX_Z))
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun #define AS73211_SCAN_MASK_ALL (    \
155*4882a593Smuzhiyun 	BIT(AS73211_SCAN_INDEX_TEMP) | \
156*4882a593Smuzhiyun 	AS73211_SCAN_MASK_COLOR)
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun static const struct iio_chan_spec as73211_channels[] = {
159*4882a593Smuzhiyun 	{
160*4882a593Smuzhiyun 		.type = IIO_TEMP,
161*4882a593Smuzhiyun 		.info_mask_separate =
162*4882a593Smuzhiyun 			BIT(IIO_CHAN_INFO_RAW) |
163*4882a593Smuzhiyun 			BIT(IIO_CHAN_INFO_OFFSET) |
164*4882a593Smuzhiyun 			BIT(IIO_CHAN_INFO_SCALE),
165*4882a593Smuzhiyun 		.address = AS73211_OUT_TEMP,
166*4882a593Smuzhiyun 		.scan_index = AS73211_SCAN_INDEX_TEMP,
167*4882a593Smuzhiyun 		.scan_type = {
168*4882a593Smuzhiyun 			.sign = 'u',
169*4882a593Smuzhiyun 			.realbits = 16,
170*4882a593Smuzhiyun 			.storagebits = 16,
171*4882a593Smuzhiyun 			.endianness = IIO_LE,
172*4882a593Smuzhiyun 		}
173*4882a593Smuzhiyun 	},
174*4882a593Smuzhiyun 	AS73211_COLOR_CHANNEL(X, AS73211_SCAN_INDEX_X, AS73211_OUT_MRES1),
175*4882a593Smuzhiyun 	AS73211_COLOR_CHANNEL(Y, AS73211_SCAN_INDEX_Y, AS73211_OUT_MRES2),
176*4882a593Smuzhiyun 	AS73211_COLOR_CHANNEL(Z, AS73211_SCAN_INDEX_Z, AS73211_OUT_MRES3),
177*4882a593Smuzhiyun 	IIO_CHAN_SOFT_TIMESTAMP(AS73211_SCAN_INDEX_TS),
178*4882a593Smuzhiyun };
179*4882a593Smuzhiyun 
as73211_integration_time_1024cyc(struct as73211_data * data)180*4882a593Smuzhiyun static unsigned int as73211_integration_time_1024cyc(struct as73211_data *data)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun 	/*
183*4882a593Smuzhiyun 	 * Return integration time in units of 1024 clock cycles. Integration time
184*4882a593Smuzhiyun 	 * in CREG1 is in powers of 2 (x 1024 cycles).
185*4882a593Smuzhiyun 	 */
186*4882a593Smuzhiyun 	return BIT(FIELD_GET(AS73211_CREG1_TIME_MASK, data->creg1));
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun 
as73211_integration_time_us(struct as73211_data * data,unsigned int integration_time_1024cyc)189*4882a593Smuzhiyun static unsigned int as73211_integration_time_us(struct as73211_data *data,
190*4882a593Smuzhiyun 						 unsigned int integration_time_1024cyc)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun 	/*
193*4882a593Smuzhiyun 	 * f_samp is configured in CREG3 in powers of 2 (x 1.024 MHz)
194*4882a593Smuzhiyun 	 * t_cycl is configured in CREG1 in powers of 2 (x 1024 cycles)
195*4882a593Smuzhiyun 	 * t_int_us = 1 / (f_samp) * t_cycl * US_PER_SEC
196*4882a593Smuzhiyun 	 *          = 1 / (2^CREG3_CCLK * 1,024,000) * 2^CREG1_CYCLES * 1,024 * US_PER_SEC
197*4882a593Smuzhiyun 	 *          = 2^(-CREG3_CCLK) * 2^CREG1_CYCLES * 1,000
198*4882a593Smuzhiyun 	 * In order to get rid of negative exponents, we extend the "fraction"
199*4882a593Smuzhiyun 	 * by 2^3 (CREG3_CCLK,max = 3)
200*4882a593Smuzhiyun 	 * t_int_us = 2^(3-CREG3_CCLK) * 2^CREG1_CYCLES * 125
201*4882a593Smuzhiyun 	 */
202*4882a593Smuzhiyun 	return BIT(3 - FIELD_GET(AS73211_CREG3_CCLK_MASK, data->creg3)) *
203*4882a593Smuzhiyun 		integration_time_1024cyc * 125;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun 
as73211_integration_time_calc_avail(struct as73211_data * data)206*4882a593Smuzhiyun static void as73211_integration_time_calc_avail(struct as73211_data *data)
207*4882a593Smuzhiyun {
208*4882a593Smuzhiyun 	int i;
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun 	for (i = 0; i < ARRAY_SIZE(data->int_time_avail) / 2; i++) {
211*4882a593Smuzhiyun 		unsigned int time_us = as73211_integration_time_us(data, BIT(i));
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun 		data->int_time_avail[i * 2 + 0] = time_us / USEC_PER_SEC;
214*4882a593Smuzhiyun 		data->int_time_avail[i * 2 + 1] = time_us % USEC_PER_SEC;
215*4882a593Smuzhiyun 	}
216*4882a593Smuzhiyun }
217*4882a593Smuzhiyun 
as73211_gain(struct as73211_data * data)218*4882a593Smuzhiyun static unsigned int as73211_gain(struct as73211_data *data)
219*4882a593Smuzhiyun {
220*4882a593Smuzhiyun 	/* gain can be calculated from CREG1 as 2^(11 - CREG1_GAIN) */
221*4882a593Smuzhiyun 	return BIT(AS73211_CREG1_GAIN_1 - FIELD_GET(AS73211_CREG1_GAIN_MASK, data->creg1));
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun /* must be called with as73211_data::mutex held. */
as73211_req_data(struct as73211_data * data)225*4882a593Smuzhiyun static int as73211_req_data(struct as73211_data *data)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun 	unsigned int time_us = as73211_integration_time_us(data,
228*4882a593Smuzhiyun 							    as73211_integration_time_1024cyc(data));
229*4882a593Smuzhiyun 	struct device *dev = &data->client->dev;
230*4882a593Smuzhiyun 	union i2c_smbus_data smbus_data;
231*4882a593Smuzhiyun 	u16 osr_status;
232*4882a593Smuzhiyun 	int ret;
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	if (data->client->irq)
235*4882a593Smuzhiyun 		reinit_completion(&data->completion);
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun 	/*
238*4882a593Smuzhiyun 	 * During measurement, there should be no traffic on the i2c bus as the
239*4882a593Smuzhiyun 	 * electrical noise would disturb the measurement process.
240*4882a593Smuzhiyun 	 */
241*4882a593Smuzhiyun 	i2c_lock_bus(data->client->adapter, I2C_LOCK_SEGMENT);
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun 	data->osr &= ~AS73211_OSR_DOS_MASK;
244*4882a593Smuzhiyun 	data->osr |= AS73211_OSR_DOS_MEASURE | AS73211_OSR_SS;
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	smbus_data.byte = data->osr;
247*4882a593Smuzhiyun 	ret = __i2c_smbus_xfer(data->client->adapter, data->client->addr,
248*4882a593Smuzhiyun 			data->client->flags, I2C_SMBUS_WRITE,
249*4882a593Smuzhiyun 			AS73211_REG_OSR, I2C_SMBUS_BYTE_DATA, &smbus_data);
250*4882a593Smuzhiyun 	if (ret < 0) {
251*4882a593Smuzhiyun 		i2c_unlock_bus(data->client->adapter, I2C_LOCK_SEGMENT);
252*4882a593Smuzhiyun 		return ret;
253*4882a593Smuzhiyun 	}
254*4882a593Smuzhiyun 
255*4882a593Smuzhiyun 	/*
256*4882a593Smuzhiyun 	 * Reset AS73211_OSR_SS (is self clearing) in order to avoid unintentional
257*4882a593Smuzhiyun 	 * triggering of further measurements later.
258*4882a593Smuzhiyun 	 */
259*4882a593Smuzhiyun 	data->osr &= ~AS73211_OSR_SS;
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	/*
262*4882a593Smuzhiyun 	 * Add 33% extra margin for the timeout. fclk,min = fclk,typ - 27%.
263*4882a593Smuzhiyun 	 */
264*4882a593Smuzhiyun 	time_us += time_us / 3;
265*4882a593Smuzhiyun 	if (data->client->irq) {
266*4882a593Smuzhiyun 		ret = wait_for_completion_timeout(&data->completion, usecs_to_jiffies(time_us));
267*4882a593Smuzhiyun 		if (!ret) {
268*4882a593Smuzhiyun 			dev_err(dev, "timeout waiting for READY IRQ\n");
269*4882a593Smuzhiyun 			i2c_unlock_bus(data->client->adapter, I2C_LOCK_SEGMENT);
270*4882a593Smuzhiyun 			return -ETIMEDOUT;
271*4882a593Smuzhiyun 		}
272*4882a593Smuzhiyun 	} else {
273*4882a593Smuzhiyun 		/* Wait integration time */
274*4882a593Smuzhiyun 		usleep_range(time_us, 2 * time_us);
275*4882a593Smuzhiyun 	}
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	i2c_unlock_bus(data->client->adapter, I2C_LOCK_SEGMENT);
278*4882a593Smuzhiyun 
279*4882a593Smuzhiyun 	ret = i2c_smbus_read_word_data(data->client, AS73211_OUT_OSR_STATUS);
280*4882a593Smuzhiyun 	if (ret < 0)
281*4882a593Smuzhiyun 		return ret;
282*4882a593Smuzhiyun 
283*4882a593Smuzhiyun 	osr_status = ret;
284*4882a593Smuzhiyun 	if (osr_status != (AS73211_OSR_DOS_MEASURE | AS73211_OSR_STATUS_NDATA)) {
285*4882a593Smuzhiyun 		if (osr_status & AS73211_OSR_SS) {
286*4882a593Smuzhiyun 			dev_err(dev, "%s() Measurement has not stopped\n", __func__);
287*4882a593Smuzhiyun 			return -ETIME;
288*4882a593Smuzhiyun 		}
289*4882a593Smuzhiyun 		if (osr_status & AS73211_OSR_STATUS_NOTREADY) {
290*4882a593Smuzhiyun 			dev_err(dev, "%s() Data is not ready\n", __func__);
291*4882a593Smuzhiyun 			return -ENODATA;
292*4882a593Smuzhiyun 		}
293*4882a593Smuzhiyun 		if (!(osr_status & AS73211_OSR_STATUS_NDATA)) {
294*4882a593Smuzhiyun 			dev_err(dev, "%s() No new data available\n", __func__);
295*4882a593Smuzhiyun 			return -ENODATA;
296*4882a593Smuzhiyun 		}
297*4882a593Smuzhiyun 		if (osr_status & AS73211_OSR_STATUS_LDATA) {
298*4882a593Smuzhiyun 			dev_err(dev, "%s() Result buffer overrun\n", __func__);
299*4882a593Smuzhiyun 			return -ENOBUFS;
300*4882a593Smuzhiyun 		}
301*4882a593Smuzhiyun 		if (osr_status & AS73211_OSR_STATUS_ADCOF) {
302*4882a593Smuzhiyun 			dev_err(dev, "%s() ADC overflow\n", __func__);
303*4882a593Smuzhiyun 			return -EOVERFLOW;
304*4882a593Smuzhiyun 		}
305*4882a593Smuzhiyun 		if (osr_status & AS73211_OSR_STATUS_MRESOF) {
306*4882a593Smuzhiyun 			dev_err(dev, "%s() Measurement result overflow\n", __func__);
307*4882a593Smuzhiyun 			return -EOVERFLOW;
308*4882a593Smuzhiyun 		}
309*4882a593Smuzhiyun 		if (osr_status & AS73211_OSR_STATUS_OUTCONVOF) {
310*4882a593Smuzhiyun 			dev_err(dev, "%s() Timer overflow\n", __func__);
311*4882a593Smuzhiyun 			return -EOVERFLOW;
312*4882a593Smuzhiyun 		}
313*4882a593Smuzhiyun 		dev_err(dev, "%s() Unexpected status value\n", __func__);
314*4882a593Smuzhiyun 		return -EIO;
315*4882a593Smuzhiyun 	}
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun 	return 0;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun 
as73211_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)320*4882a593Smuzhiyun static int as73211_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
321*4882a593Smuzhiyun 			     int *val, int *val2, long mask)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun 	struct as73211_data *data = iio_priv(indio_dev);
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	switch (mask) {
326*4882a593Smuzhiyun 	case IIO_CHAN_INFO_RAW: {
327*4882a593Smuzhiyun 		int ret;
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 		ret = iio_device_claim_direct_mode(indio_dev);
330*4882a593Smuzhiyun 		if (ret < 0)
331*4882a593Smuzhiyun 			return ret;
332*4882a593Smuzhiyun 
333*4882a593Smuzhiyun 		ret = as73211_req_data(data);
334*4882a593Smuzhiyun 		if (ret < 0) {
335*4882a593Smuzhiyun 			iio_device_release_direct_mode(indio_dev);
336*4882a593Smuzhiyun 			return ret;
337*4882a593Smuzhiyun 		}
338*4882a593Smuzhiyun 
339*4882a593Smuzhiyun 		ret = i2c_smbus_read_word_data(data->client, chan->address);
340*4882a593Smuzhiyun 		iio_device_release_direct_mode(indio_dev);
341*4882a593Smuzhiyun 		if (ret < 0)
342*4882a593Smuzhiyun 			return ret;
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 		*val = ret;
345*4882a593Smuzhiyun 		return IIO_VAL_INT;
346*4882a593Smuzhiyun 	}
347*4882a593Smuzhiyun 	case IIO_CHAN_INFO_OFFSET:
348*4882a593Smuzhiyun 		*val = AS73211_OFFSET_TEMP_INT;
349*4882a593Smuzhiyun 		*val2 = AS73211_OFFSET_TEMP_MICRO;
350*4882a593Smuzhiyun 		return IIO_VAL_INT_PLUS_MICRO;
351*4882a593Smuzhiyun 
352*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SCALE:
353*4882a593Smuzhiyun 		switch (chan->type) {
354*4882a593Smuzhiyun 		case IIO_TEMP:
355*4882a593Smuzhiyun 			*val = AS73211_SCALE_TEMP_INT;
356*4882a593Smuzhiyun 			*val2 = AS73211_SCALE_TEMP_MICRO;
357*4882a593Smuzhiyun 			return IIO_VAL_INT_PLUS_MICRO;
358*4882a593Smuzhiyun 
359*4882a593Smuzhiyun 		case IIO_INTENSITY: {
360*4882a593Smuzhiyun 			unsigned int scale;
361*4882a593Smuzhiyun 
362*4882a593Smuzhiyun 			switch (chan->channel2) {
363*4882a593Smuzhiyun 			case IIO_MOD_X:
364*4882a593Smuzhiyun 				scale = AS73211_SCALE_X;
365*4882a593Smuzhiyun 				break;
366*4882a593Smuzhiyun 			case IIO_MOD_Y:
367*4882a593Smuzhiyun 				scale = AS73211_SCALE_Y;
368*4882a593Smuzhiyun 				break;
369*4882a593Smuzhiyun 			case IIO_MOD_Z:
370*4882a593Smuzhiyun 				scale = AS73211_SCALE_Z;
371*4882a593Smuzhiyun 				break;
372*4882a593Smuzhiyun 			default:
373*4882a593Smuzhiyun 				return -EINVAL;
374*4882a593Smuzhiyun 			}
375*4882a593Smuzhiyun 			scale /= as73211_gain(data);
376*4882a593Smuzhiyun 			scale /= as73211_integration_time_1024cyc(data);
377*4882a593Smuzhiyun 			*val = scale;
378*4882a593Smuzhiyun 			return IIO_VAL_INT;
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun 		default:
381*4882a593Smuzhiyun 			return -EINVAL;
382*4882a593Smuzhiyun 		}}
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SAMP_FREQ:
385*4882a593Smuzhiyun 		/* f_samp is configured in CREG3 in powers of 2 (x 1.024 MHz) */
386*4882a593Smuzhiyun 		*val = BIT(FIELD_GET(AS73211_CREG3_CCLK_MASK, data->creg3)) *
387*4882a593Smuzhiyun 			AS73211_SAMPLE_FREQ_BASE;
388*4882a593Smuzhiyun 		return IIO_VAL_INT;
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun 	case IIO_CHAN_INFO_HARDWAREGAIN:
391*4882a593Smuzhiyun 		*val = as73211_gain(data);
392*4882a593Smuzhiyun 		return IIO_VAL_INT;
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun 	case IIO_CHAN_INFO_INT_TIME: {
395*4882a593Smuzhiyun 		unsigned int time_us;
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 		mutex_lock(&data->mutex);
398*4882a593Smuzhiyun 		time_us = as73211_integration_time_us(data, as73211_integration_time_1024cyc(data));
399*4882a593Smuzhiyun 		mutex_unlock(&data->mutex);
400*4882a593Smuzhiyun 		*val = time_us / USEC_PER_SEC;
401*4882a593Smuzhiyun 		*val2 = time_us % USEC_PER_SEC;
402*4882a593Smuzhiyun 		return IIO_VAL_INT_PLUS_MICRO;
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	default:
405*4882a593Smuzhiyun 		return -EINVAL;
406*4882a593Smuzhiyun 	}}
407*4882a593Smuzhiyun }
408*4882a593Smuzhiyun 
as73211_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)409*4882a593Smuzhiyun static int as73211_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
410*4882a593Smuzhiyun 			       const int **vals, int *type, int *length, long mask)
411*4882a593Smuzhiyun {
412*4882a593Smuzhiyun 	struct as73211_data *data = iio_priv(indio_dev);
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	switch (mask) {
415*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SAMP_FREQ:
416*4882a593Smuzhiyun 		*length = ARRAY_SIZE(as73211_samp_freq_avail);
417*4882a593Smuzhiyun 		*vals = as73211_samp_freq_avail;
418*4882a593Smuzhiyun 		*type = IIO_VAL_INT;
419*4882a593Smuzhiyun 		return IIO_AVAIL_LIST;
420*4882a593Smuzhiyun 
421*4882a593Smuzhiyun 	case IIO_CHAN_INFO_HARDWAREGAIN:
422*4882a593Smuzhiyun 		*length = ARRAY_SIZE(as73211_hardwaregain_avail);
423*4882a593Smuzhiyun 		*vals = as73211_hardwaregain_avail;
424*4882a593Smuzhiyun 		*type = IIO_VAL_INT;
425*4882a593Smuzhiyun 		return IIO_AVAIL_LIST;
426*4882a593Smuzhiyun 
427*4882a593Smuzhiyun 	case IIO_CHAN_INFO_INT_TIME:
428*4882a593Smuzhiyun 		*length = ARRAY_SIZE(data->int_time_avail);
429*4882a593Smuzhiyun 		*vals = data->int_time_avail;
430*4882a593Smuzhiyun 		*type = IIO_VAL_INT_PLUS_MICRO;
431*4882a593Smuzhiyun 		return IIO_AVAIL_LIST;
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	default:
434*4882a593Smuzhiyun 		return -EINVAL;
435*4882a593Smuzhiyun 	}
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun 
_as73211_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan __always_unused,int val,int val2,long mask)438*4882a593Smuzhiyun static int _as73211_write_raw(struct iio_dev *indio_dev,
439*4882a593Smuzhiyun 			       struct iio_chan_spec const *chan __always_unused,
440*4882a593Smuzhiyun 			       int val, int val2, long mask)
441*4882a593Smuzhiyun {
442*4882a593Smuzhiyun 	struct as73211_data *data = iio_priv(indio_dev);
443*4882a593Smuzhiyun 	int ret;
444*4882a593Smuzhiyun 
445*4882a593Smuzhiyun 	switch (mask) {
446*4882a593Smuzhiyun 	case IIO_CHAN_INFO_SAMP_FREQ: {
447*4882a593Smuzhiyun 		int reg_bits, freq_kHz = val / HZ_PER_KHZ;  /* 1024, 2048, ... */
448*4882a593Smuzhiyun 
449*4882a593Smuzhiyun 		/* val must be 1024 * 2^x */
450*4882a593Smuzhiyun 		if (val < 0 || (freq_kHz * HZ_PER_KHZ) != val ||
451*4882a593Smuzhiyun 				!is_power_of_2(freq_kHz) || val2)
452*4882a593Smuzhiyun 			return -EINVAL;
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun 		/* f_samp is configured in CREG3 in powers of 2 (x 1.024 MHz (=2^10)) */
455*4882a593Smuzhiyun 		reg_bits = ilog2(freq_kHz) - 10;
456*4882a593Smuzhiyun 		if (!FIELD_FIT(AS73211_CREG3_CCLK_MASK, reg_bits))
457*4882a593Smuzhiyun 			return -EINVAL;
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 		data->creg3 &= ~AS73211_CREG3_CCLK_MASK;
460*4882a593Smuzhiyun 		data->creg3 |= FIELD_PREP(AS73211_CREG3_CCLK_MASK, reg_bits);
461*4882a593Smuzhiyun 		as73211_integration_time_calc_avail(data);
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 		ret = i2c_smbus_write_byte_data(data->client, AS73211_REG_CREG3, data->creg3);
464*4882a593Smuzhiyun 		if (ret < 0)
465*4882a593Smuzhiyun 			return ret;
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun 		return 0;
468*4882a593Smuzhiyun 	}
469*4882a593Smuzhiyun 	case IIO_CHAN_INFO_HARDWAREGAIN: {
470*4882a593Smuzhiyun 		unsigned int reg_bits;
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun 		if (val < 0 || !is_power_of_2(val) || val2)
473*4882a593Smuzhiyun 			return -EINVAL;
474*4882a593Smuzhiyun 
475*4882a593Smuzhiyun 		/* gain can be calculated from CREG1 as 2^(11 - CREG1_GAIN) */
476*4882a593Smuzhiyun 		reg_bits = AS73211_CREG1_GAIN_1 - ilog2(val);
477*4882a593Smuzhiyun 		if (!FIELD_FIT(AS73211_CREG1_GAIN_MASK, reg_bits))
478*4882a593Smuzhiyun 			return -EINVAL;
479*4882a593Smuzhiyun 
480*4882a593Smuzhiyun 		data->creg1 &= ~AS73211_CREG1_GAIN_MASK;
481*4882a593Smuzhiyun 		data->creg1 |= FIELD_PREP(AS73211_CREG1_GAIN_MASK, reg_bits);
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun 		ret = i2c_smbus_write_byte_data(data->client, AS73211_REG_CREG1, data->creg1);
484*4882a593Smuzhiyun 		if (ret < 0)
485*4882a593Smuzhiyun 			return ret;
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun 		return 0;
488*4882a593Smuzhiyun 	}
489*4882a593Smuzhiyun 	case IIO_CHAN_INFO_INT_TIME: {
490*4882a593Smuzhiyun 		int val_us = val * USEC_PER_SEC + val2;
491*4882a593Smuzhiyun 		int time_ms;
492*4882a593Smuzhiyun 		int reg_bits;
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 		/* f_samp is configured in CREG3 in powers of 2 (x 1.024 MHz) */
495*4882a593Smuzhiyun 		int f_samp_1_024mhz = BIT(FIELD_GET(AS73211_CREG3_CCLK_MASK, data->creg3));
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun 		/*
498*4882a593Smuzhiyun 		 * time_ms = time_us * US_PER_MS * f_samp_1_024mhz / MHZ_PER_HZ
499*4882a593Smuzhiyun 		 *         = time_us * f_samp_1_024mhz / 1000
500*4882a593Smuzhiyun 		 */
501*4882a593Smuzhiyun 		time_ms = (val_us * f_samp_1_024mhz) / 1000;  /* 1 ms, 2 ms, ... (power of two) */
502*4882a593Smuzhiyun 		if (time_ms < 0 || !is_power_of_2(time_ms) || time_ms > AS73211_SAMPLE_TIME_MAX_MS)
503*4882a593Smuzhiyun 			return -EINVAL;
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun 		reg_bits = ilog2(time_ms);
506*4882a593Smuzhiyun 		if (!FIELD_FIT(AS73211_CREG1_TIME_MASK, reg_bits))
507*4882a593Smuzhiyun 			return -EINVAL;  /* not possible due to previous tests */
508*4882a593Smuzhiyun 
509*4882a593Smuzhiyun 		data->creg1 &= ~AS73211_CREG1_TIME_MASK;
510*4882a593Smuzhiyun 		data->creg1 |= FIELD_PREP(AS73211_CREG1_TIME_MASK, reg_bits);
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun 		ret = i2c_smbus_write_byte_data(data->client, AS73211_REG_CREG1, data->creg1);
513*4882a593Smuzhiyun 		if (ret < 0)
514*4882a593Smuzhiyun 			return ret;
515*4882a593Smuzhiyun 
516*4882a593Smuzhiyun 		return 0;
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun 	default:
519*4882a593Smuzhiyun 		return -EINVAL;
520*4882a593Smuzhiyun 	}}
521*4882a593Smuzhiyun }
522*4882a593Smuzhiyun 
as73211_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)523*4882a593Smuzhiyun static int as73211_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan,
524*4882a593Smuzhiyun 			      int val, int val2, long mask)
525*4882a593Smuzhiyun {
526*4882a593Smuzhiyun 	struct as73211_data *data = iio_priv(indio_dev);
527*4882a593Smuzhiyun 	int ret;
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
530*4882a593Smuzhiyun 
531*4882a593Smuzhiyun 	ret = iio_device_claim_direct_mode(indio_dev);
532*4882a593Smuzhiyun 	if (ret < 0)
533*4882a593Smuzhiyun 		goto error_unlock;
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	/* Need to switch to config mode ... */
536*4882a593Smuzhiyun 	if ((data->osr & AS73211_OSR_DOS_MASK) != AS73211_OSR_DOS_CONFIG) {
537*4882a593Smuzhiyun 		data->osr &= ~AS73211_OSR_DOS_MASK;
538*4882a593Smuzhiyun 		data->osr |= AS73211_OSR_DOS_CONFIG;
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 		ret = i2c_smbus_write_byte_data(data->client, AS73211_REG_OSR, data->osr);
541*4882a593Smuzhiyun 		if (ret < 0)
542*4882a593Smuzhiyun 			goto error_release;
543*4882a593Smuzhiyun 	}
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun 	ret = _as73211_write_raw(indio_dev, chan, val, val2, mask);
546*4882a593Smuzhiyun 
547*4882a593Smuzhiyun error_release:
548*4882a593Smuzhiyun 	iio_device_release_direct_mode(indio_dev);
549*4882a593Smuzhiyun error_unlock:
550*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
551*4882a593Smuzhiyun 	return ret;
552*4882a593Smuzhiyun }
553*4882a593Smuzhiyun 
as73211_ready_handler(int irq __always_unused,void * priv)554*4882a593Smuzhiyun static irqreturn_t as73211_ready_handler(int irq __always_unused, void *priv)
555*4882a593Smuzhiyun {
556*4882a593Smuzhiyun 	struct as73211_data *data = iio_priv(priv);
557*4882a593Smuzhiyun 
558*4882a593Smuzhiyun 	complete(&data->completion);
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun 	return IRQ_HANDLED;
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun 
as73211_trigger_handler(int irq __always_unused,void * p)563*4882a593Smuzhiyun static irqreturn_t as73211_trigger_handler(int irq __always_unused, void *p)
564*4882a593Smuzhiyun {
565*4882a593Smuzhiyun 	struct iio_poll_func *pf = p;
566*4882a593Smuzhiyun 	struct iio_dev *indio_dev = pf->indio_dev;
567*4882a593Smuzhiyun 	struct as73211_data *data = iio_priv(indio_dev);
568*4882a593Smuzhiyun 	struct {
569*4882a593Smuzhiyun 		__le16 chan[4];
570*4882a593Smuzhiyun 		s64 ts __aligned(8);
571*4882a593Smuzhiyun 	} scan;
572*4882a593Smuzhiyun 	int data_result, ret;
573*4882a593Smuzhiyun 
574*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
575*4882a593Smuzhiyun 
576*4882a593Smuzhiyun 	data_result = as73211_req_data(data);
577*4882a593Smuzhiyun 	if (data_result < 0 && data_result != -EOVERFLOW)
578*4882a593Smuzhiyun 		goto done;  /* don't push any data for errors other than EOVERFLOW */
579*4882a593Smuzhiyun 
580*4882a593Smuzhiyun 	if (*indio_dev->active_scan_mask == AS73211_SCAN_MASK_ALL) {
581*4882a593Smuzhiyun 		/* Optimization for reading all (color + temperature) channels */
582*4882a593Smuzhiyun 		u8 addr = as73211_channels[0].address;
583*4882a593Smuzhiyun 		struct i2c_msg msgs[] = {
584*4882a593Smuzhiyun 			{
585*4882a593Smuzhiyun 				.addr = data->client->addr,
586*4882a593Smuzhiyun 				.flags = 0,
587*4882a593Smuzhiyun 				.len = 1,
588*4882a593Smuzhiyun 				.buf = &addr,
589*4882a593Smuzhiyun 			},
590*4882a593Smuzhiyun 			{
591*4882a593Smuzhiyun 				.addr = data->client->addr,
592*4882a593Smuzhiyun 				.flags = I2C_M_RD,
593*4882a593Smuzhiyun 				.len = sizeof(scan.chan),
594*4882a593Smuzhiyun 				.buf = (u8 *)&scan.chan,
595*4882a593Smuzhiyun 			},
596*4882a593Smuzhiyun 		};
597*4882a593Smuzhiyun 
598*4882a593Smuzhiyun 		ret = i2c_transfer(data->client->adapter, msgs, ARRAY_SIZE(msgs));
599*4882a593Smuzhiyun 		if (ret < 0)
600*4882a593Smuzhiyun 			goto done;
601*4882a593Smuzhiyun 	} else {
602*4882a593Smuzhiyun 		/* Optimization for reading only color channels */
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun 		/* AS73211 starts reading at address 2 */
605*4882a593Smuzhiyun 		ret = i2c_master_recv(data->client,
606*4882a593Smuzhiyun 				(char *)&scan.chan[1], 3 * sizeof(scan.chan[1]));
607*4882a593Smuzhiyun 		if (ret < 0)
608*4882a593Smuzhiyun 			goto done;
609*4882a593Smuzhiyun 	}
610*4882a593Smuzhiyun 
611*4882a593Smuzhiyun 	if (data_result) {
612*4882a593Smuzhiyun 		/*
613*4882a593Smuzhiyun 		 * Saturate all channels (in case of overflows). Temperature channel
614*4882a593Smuzhiyun 		 * is not affected by overflows.
615*4882a593Smuzhiyun 		 */
616*4882a593Smuzhiyun 		scan.chan[1] = cpu_to_le16(U16_MAX);
617*4882a593Smuzhiyun 		scan.chan[2] = cpu_to_le16(U16_MAX);
618*4882a593Smuzhiyun 		scan.chan[3] = cpu_to_le16(U16_MAX);
619*4882a593Smuzhiyun 	}
620*4882a593Smuzhiyun 
621*4882a593Smuzhiyun 	iio_push_to_buffers_with_timestamp(indio_dev, &scan, iio_get_time_ns(indio_dev));
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun done:
624*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
625*4882a593Smuzhiyun 	iio_trigger_notify_done(indio_dev->trig);
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun 	return IRQ_HANDLED;
628*4882a593Smuzhiyun }
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun static const struct iio_info as73211_info = {
631*4882a593Smuzhiyun 	.read_raw = as73211_read_raw,
632*4882a593Smuzhiyun 	.read_avail = as73211_read_avail,
633*4882a593Smuzhiyun 	.write_raw = as73211_write_raw,
634*4882a593Smuzhiyun };
635*4882a593Smuzhiyun 
as73211_power(struct iio_dev * indio_dev,bool state)636*4882a593Smuzhiyun static int as73211_power(struct iio_dev *indio_dev, bool state)
637*4882a593Smuzhiyun {
638*4882a593Smuzhiyun 	struct as73211_data *data = iio_priv(indio_dev);
639*4882a593Smuzhiyun 	int ret;
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 	mutex_lock(&data->mutex);
642*4882a593Smuzhiyun 
643*4882a593Smuzhiyun 	if (state)
644*4882a593Smuzhiyun 		data->osr &= ~AS73211_OSR_PD;
645*4882a593Smuzhiyun 	else
646*4882a593Smuzhiyun 		data->osr |= AS73211_OSR_PD;
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun 	ret = i2c_smbus_write_byte_data(data->client, AS73211_REG_OSR, data->osr);
649*4882a593Smuzhiyun 
650*4882a593Smuzhiyun 	mutex_unlock(&data->mutex);
651*4882a593Smuzhiyun 
652*4882a593Smuzhiyun 	if (ret < 0)
653*4882a593Smuzhiyun 		return ret;
654*4882a593Smuzhiyun 
655*4882a593Smuzhiyun 	return 0;
656*4882a593Smuzhiyun }
657*4882a593Smuzhiyun 
as73211_power_disable(void * data)658*4882a593Smuzhiyun static void as73211_power_disable(void *data)
659*4882a593Smuzhiyun {
660*4882a593Smuzhiyun 	struct iio_dev *indio_dev = data;
661*4882a593Smuzhiyun 
662*4882a593Smuzhiyun 	as73211_power(indio_dev, false);
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun 
as73211_probe(struct i2c_client * client)665*4882a593Smuzhiyun static int as73211_probe(struct i2c_client *client)
666*4882a593Smuzhiyun {
667*4882a593Smuzhiyun 	struct device *dev = &client->dev;
668*4882a593Smuzhiyun 	struct as73211_data *data;
669*4882a593Smuzhiyun 	struct iio_dev *indio_dev;
670*4882a593Smuzhiyun 	int ret;
671*4882a593Smuzhiyun 
672*4882a593Smuzhiyun 	indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
673*4882a593Smuzhiyun 	if (!indio_dev)
674*4882a593Smuzhiyun 		return -ENOMEM;
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun 	data = iio_priv(indio_dev);
677*4882a593Smuzhiyun 	i2c_set_clientdata(client, indio_dev);
678*4882a593Smuzhiyun 	data->client = client;
679*4882a593Smuzhiyun 
680*4882a593Smuzhiyun 	mutex_init(&data->mutex);
681*4882a593Smuzhiyun 	init_completion(&data->completion);
682*4882a593Smuzhiyun 
683*4882a593Smuzhiyun 	indio_dev->info = &as73211_info;
684*4882a593Smuzhiyun 	indio_dev->name = AS73211_DRV_NAME;
685*4882a593Smuzhiyun 	indio_dev->channels = as73211_channels;
686*4882a593Smuzhiyun 	indio_dev->num_channels = ARRAY_SIZE(as73211_channels);
687*4882a593Smuzhiyun 	indio_dev->modes = INDIO_DIRECT_MODE;
688*4882a593Smuzhiyun 
689*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(data->client, AS73211_REG_OSR);
690*4882a593Smuzhiyun 	if (ret < 0)
691*4882a593Smuzhiyun 		return ret;
692*4882a593Smuzhiyun 	data->osr = ret;
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 	/* reset device */
695*4882a593Smuzhiyun 	data->osr |= AS73211_OSR_SW_RES;
696*4882a593Smuzhiyun 	ret = i2c_smbus_write_byte_data(data->client, AS73211_REG_OSR, data->osr);
697*4882a593Smuzhiyun 	if (ret < 0)
698*4882a593Smuzhiyun 		return ret;
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(data->client, AS73211_REG_OSR);
701*4882a593Smuzhiyun 	if (ret < 0)
702*4882a593Smuzhiyun 		return ret;
703*4882a593Smuzhiyun 	data->osr = ret;
704*4882a593Smuzhiyun 
705*4882a593Smuzhiyun 	/*
706*4882a593Smuzhiyun 	 * Reading AGEN is only possible after reset (AGEN is not available if
707*4882a593Smuzhiyun 	 * device is in measurement mode).
708*4882a593Smuzhiyun 	 */
709*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(data->client, AS73211_REG_AGEN);
710*4882a593Smuzhiyun 	if (ret < 0)
711*4882a593Smuzhiyun 		return ret;
712*4882a593Smuzhiyun 
713*4882a593Smuzhiyun 	/* At the time of writing this driver, only DEVID 2 and MUT 1 are known. */
714*4882a593Smuzhiyun 	if ((ret & AS73211_AGEN_DEVID_MASK) != AS73211_AGEN_DEVID(2) ||
715*4882a593Smuzhiyun 	    (ret & AS73211_AGEN_MUT_MASK) != AS73211_AGEN_MUT(1))
716*4882a593Smuzhiyun 		return -ENODEV;
717*4882a593Smuzhiyun 
718*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(data->client, AS73211_REG_CREG1);
719*4882a593Smuzhiyun 	if (ret < 0)
720*4882a593Smuzhiyun 		return ret;
721*4882a593Smuzhiyun 	data->creg1 = ret;
722*4882a593Smuzhiyun 
723*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(data->client, AS73211_REG_CREG2);
724*4882a593Smuzhiyun 	if (ret < 0)
725*4882a593Smuzhiyun 		return ret;
726*4882a593Smuzhiyun 	data->creg2 = ret;
727*4882a593Smuzhiyun 
728*4882a593Smuzhiyun 	ret = i2c_smbus_read_byte_data(data->client, AS73211_REG_CREG3);
729*4882a593Smuzhiyun 	if (ret < 0)
730*4882a593Smuzhiyun 		return ret;
731*4882a593Smuzhiyun 	data->creg3 = ret;
732*4882a593Smuzhiyun 	as73211_integration_time_calc_avail(data);
733*4882a593Smuzhiyun 
734*4882a593Smuzhiyun 	ret = as73211_power(indio_dev, true);
735*4882a593Smuzhiyun 	if (ret < 0)
736*4882a593Smuzhiyun 		return ret;
737*4882a593Smuzhiyun 
738*4882a593Smuzhiyun 	ret = devm_add_action_or_reset(dev, as73211_power_disable, indio_dev);
739*4882a593Smuzhiyun 	if (ret)
740*4882a593Smuzhiyun 		return ret;
741*4882a593Smuzhiyun 
742*4882a593Smuzhiyun 	ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, as73211_trigger_handler, NULL);
743*4882a593Smuzhiyun 	if (ret)
744*4882a593Smuzhiyun 		return ret;
745*4882a593Smuzhiyun 
746*4882a593Smuzhiyun 	if (client->irq) {
747*4882a593Smuzhiyun 		ret = devm_request_threaded_irq(&client->dev, client->irq,
748*4882a593Smuzhiyun 				NULL,
749*4882a593Smuzhiyun 				as73211_ready_handler,
750*4882a593Smuzhiyun 				IRQF_ONESHOT,
751*4882a593Smuzhiyun 				client->name, indio_dev);
752*4882a593Smuzhiyun 		if (ret)
753*4882a593Smuzhiyun 			return ret;
754*4882a593Smuzhiyun 	}
755*4882a593Smuzhiyun 
756*4882a593Smuzhiyun 	return devm_iio_device_register(dev, indio_dev);
757*4882a593Smuzhiyun }
758*4882a593Smuzhiyun 
as73211_suspend(struct device * dev)759*4882a593Smuzhiyun static int __maybe_unused as73211_suspend(struct device *dev)
760*4882a593Smuzhiyun {
761*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
762*4882a593Smuzhiyun 
763*4882a593Smuzhiyun 	return as73211_power(indio_dev, false);
764*4882a593Smuzhiyun }
765*4882a593Smuzhiyun 
as73211_resume(struct device * dev)766*4882a593Smuzhiyun static int __maybe_unused as73211_resume(struct device *dev)
767*4882a593Smuzhiyun {
768*4882a593Smuzhiyun 	struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
769*4882a593Smuzhiyun 
770*4882a593Smuzhiyun 	return as73211_power(indio_dev, true);
771*4882a593Smuzhiyun }
772*4882a593Smuzhiyun 
773*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(as73211_pm_ops, as73211_suspend, as73211_resume);
774*4882a593Smuzhiyun 
775*4882a593Smuzhiyun static const struct of_device_id as73211_of_match[] = {
776*4882a593Smuzhiyun 	{ .compatible = "ams,as73211" },
777*4882a593Smuzhiyun 	{ }
778*4882a593Smuzhiyun };
779*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, as73211_of_match);
780*4882a593Smuzhiyun 
781*4882a593Smuzhiyun static const struct i2c_device_id as73211_id[] = {
782*4882a593Smuzhiyun 	{ "as73211", 0 },
783*4882a593Smuzhiyun 	{ }
784*4882a593Smuzhiyun };
785*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, as73211_id);
786*4882a593Smuzhiyun 
787*4882a593Smuzhiyun static struct i2c_driver as73211_driver = {
788*4882a593Smuzhiyun 	.driver = {
789*4882a593Smuzhiyun 		.name           = AS73211_DRV_NAME,
790*4882a593Smuzhiyun 		.of_match_table = as73211_of_match,
791*4882a593Smuzhiyun 		.pm             = &as73211_pm_ops,
792*4882a593Smuzhiyun 	},
793*4882a593Smuzhiyun 	.probe_new  = as73211_probe,
794*4882a593Smuzhiyun 	.id_table   = as73211_id,
795*4882a593Smuzhiyun };
796*4882a593Smuzhiyun module_i2c_driver(as73211_driver);
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun MODULE_AUTHOR("Christian Eggers <ceggers@arri.de>");
799*4882a593Smuzhiyun MODULE_DESCRIPTION("AS73211 XYZ True Color Sensor driver");
800*4882a593Smuzhiyun MODULE_LICENSE("GPL");
801