1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * apds9300.c - IIO driver for Avago APDS9300 ambient light sensor
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2013 Oleksandr Kravchenko <o.v.kravchenko@globallogic.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/slab.h>
10*4882a593Smuzhiyun #include <linux/pm.h>
11*4882a593Smuzhiyun #include <linux/i2c.h>
12*4882a593Smuzhiyun #include <linux/err.h>
13*4882a593Smuzhiyun #include <linux/mutex.h>
14*4882a593Smuzhiyun #include <linux/interrupt.h>
15*4882a593Smuzhiyun #include <linux/iio/iio.h>
16*4882a593Smuzhiyun #include <linux/iio/sysfs.h>
17*4882a593Smuzhiyun #include <linux/iio/events.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define APDS9300_DRV_NAME "apds9300"
20*4882a593Smuzhiyun #define APDS9300_IRQ_NAME "apds9300_event"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* Command register bits */
23*4882a593Smuzhiyun #define APDS9300_CMD BIT(7) /* Select command register. Must write as 1 */
24*4882a593Smuzhiyun #define APDS9300_WORD BIT(5) /* I2C write/read: if 1 word, if 0 byte */
25*4882a593Smuzhiyun #define APDS9300_CLEAR BIT(6) /* Interrupt clear. Clears pending interrupt */
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun /* Register set */
28*4882a593Smuzhiyun #define APDS9300_CONTROL 0x00 /* Control of basic functions */
29*4882a593Smuzhiyun #define APDS9300_THRESHLOWLOW 0x02 /* Low byte of low interrupt threshold */
30*4882a593Smuzhiyun #define APDS9300_THRESHHIGHLOW 0x04 /* Low byte of high interrupt threshold */
31*4882a593Smuzhiyun #define APDS9300_INTERRUPT 0x06 /* Interrupt control */
32*4882a593Smuzhiyun #define APDS9300_DATA0LOW 0x0c /* Low byte of ADC channel 0 */
33*4882a593Smuzhiyun #define APDS9300_DATA1LOW 0x0e /* Low byte of ADC channel 1 */
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Power on/off value for APDS9300_CONTROL register */
36*4882a593Smuzhiyun #define APDS9300_POWER_ON 0x03
37*4882a593Smuzhiyun #define APDS9300_POWER_OFF 0x00
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Interrupts */
40*4882a593Smuzhiyun #define APDS9300_INTR_ENABLE 0x10
41*4882a593Smuzhiyun /* Interrupt Persist Function: Any value outside of threshold range */
42*4882a593Smuzhiyun #define APDS9300_THRESH_INTR 0x01
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define APDS9300_THRESH_MAX 0xffff /* Max threshold value */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun struct apds9300_data {
47*4882a593Smuzhiyun struct i2c_client *client;
48*4882a593Smuzhiyun struct mutex mutex;
49*4882a593Smuzhiyun int power_state;
50*4882a593Smuzhiyun int thresh_low;
51*4882a593Smuzhiyun int thresh_hi;
52*4882a593Smuzhiyun int intr_en;
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* Lux calculation */
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* Calculated values 1000 * (CH1/CH0)^1.4 for CH1/CH0 from 0 to 0.52 */
58*4882a593Smuzhiyun static const u16 apds9300_lux_ratio[] = {
59*4882a593Smuzhiyun 0, 2, 4, 7, 11, 15, 19, 24, 29, 34, 40, 45, 51, 57, 64, 70, 77, 84, 91,
60*4882a593Smuzhiyun 98, 105, 112, 120, 128, 136, 144, 152, 160, 168, 177, 185, 194, 203,
61*4882a593Smuzhiyun 212, 221, 230, 239, 249, 258, 268, 277, 287, 297, 307, 317, 327, 337,
62*4882a593Smuzhiyun 347, 358, 368, 379, 390, 400,
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
apds9300_calculate_lux(u16 ch0,u16 ch1)65*4882a593Smuzhiyun static unsigned long apds9300_calculate_lux(u16 ch0, u16 ch1)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun unsigned long lux, tmp;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* avoid division by zero */
70*4882a593Smuzhiyun if (ch0 == 0)
71*4882a593Smuzhiyun return 0;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun tmp = DIV_ROUND_UP(ch1 * 100, ch0);
74*4882a593Smuzhiyun if (tmp <= 52) {
75*4882a593Smuzhiyun lux = 3150 * ch0 - (unsigned long)DIV_ROUND_UP_ULL(ch0
76*4882a593Smuzhiyun * apds9300_lux_ratio[tmp] * 5930ull, 1000);
77*4882a593Smuzhiyun } else if (tmp <= 65) {
78*4882a593Smuzhiyun lux = 2290 * ch0 - 2910 * ch1;
79*4882a593Smuzhiyun } else if (tmp <= 80) {
80*4882a593Smuzhiyun lux = 1570 * ch0 - 1800 * ch1;
81*4882a593Smuzhiyun } else if (tmp <= 130) {
82*4882a593Smuzhiyun lux = 338 * ch0 - 260 * ch1;
83*4882a593Smuzhiyun } else {
84*4882a593Smuzhiyun lux = 0;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun return lux / 100000;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
apds9300_get_adc_val(struct apds9300_data * data,int adc_number)90*4882a593Smuzhiyun static int apds9300_get_adc_val(struct apds9300_data *data, int adc_number)
91*4882a593Smuzhiyun {
92*4882a593Smuzhiyun int ret;
93*4882a593Smuzhiyun u8 flags = APDS9300_CMD | APDS9300_WORD;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun if (!data->power_state)
96*4882a593Smuzhiyun return -EBUSY;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /* Select ADC0 or ADC1 data register */
99*4882a593Smuzhiyun flags |= adc_number ? APDS9300_DATA1LOW : APDS9300_DATA0LOW;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun ret = i2c_smbus_read_word_data(data->client, flags);
102*4882a593Smuzhiyun if (ret < 0)
103*4882a593Smuzhiyun dev_err(&data->client->dev,
104*4882a593Smuzhiyun "failed to read ADC%d value\n", adc_number);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun return ret;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
apds9300_set_thresh_low(struct apds9300_data * data,int value)109*4882a593Smuzhiyun static int apds9300_set_thresh_low(struct apds9300_data *data, int value)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun int ret;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun if (!data->power_state)
114*4882a593Smuzhiyun return -EBUSY;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun if (value > APDS9300_THRESH_MAX)
117*4882a593Smuzhiyun return -EINVAL;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun ret = i2c_smbus_write_word_data(data->client, APDS9300_THRESHLOWLOW
120*4882a593Smuzhiyun | APDS9300_CMD | APDS9300_WORD, value);
121*4882a593Smuzhiyun if (ret) {
122*4882a593Smuzhiyun dev_err(&data->client->dev, "failed to set thresh_low\n");
123*4882a593Smuzhiyun return ret;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun data->thresh_low = value;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun return 0;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
apds9300_set_thresh_hi(struct apds9300_data * data,int value)130*4882a593Smuzhiyun static int apds9300_set_thresh_hi(struct apds9300_data *data, int value)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun int ret;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun if (!data->power_state)
135*4882a593Smuzhiyun return -EBUSY;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun if (value > APDS9300_THRESH_MAX)
138*4882a593Smuzhiyun return -EINVAL;
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun ret = i2c_smbus_write_word_data(data->client, APDS9300_THRESHHIGHLOW
141*4882a593Smuzhiyun | APDS9300_CMD | APDS9300_WORD, value);
142*4882a593Smuzhiyun if (ret) {
143*4882a593Smuzhiyun dev_err(&data->client->dev, "failed to set thresh_hi\n");
144*4882a593Smuzhiyun return ret;
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun data->thresh_hi = value;
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun return 0;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
apds9300_set_intr_state(struct apds9300_data * data,int state)151*4882a593Smuzhiyun static int apds9300_set_intr_state(struct apds9300_data *data, int state)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun int ret;
154*4882a593Smuzhiyun u8 cmd;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun if (!data->power_state)
157*4882a593Smuzhiyun return -EBUSY;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun cmd = state ? APDS9300_INTR_ENABLE | APDS9300_THRESH_INTR : 0x00;
160*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client,
161*4882a593Smuzhiyun APDS9300_INTERRUPT | APDS9300_CMD, cmd);
162*4882a593Smuzhiyun if (ret) {
163*4882a593Smuzhiyun dev_err(&data->client->dev,
164*4882a593Smuzhiyun "failed to set interrupt state %d\n", state);
165*4882a593Smuzhiyun return ret;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun data->intr_en = state;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun return 0;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
apds9300_set_power_state(struct apds9300_data * data,int state)172*4882a593Smuzhiyun static int apds9300_set_power_state(struct apds9300_data *data, int state)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun int ret;
175*4882a593Smuzhiyun u8 cmd;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun cmd = state ? APDS9300_POWER_ON : APDS9300_POWER_OFF;
178*4882a593Smuzhiyun ret = i2c_smbus_write_byte_data(data->client,
179*4882a593Smuzhiyun APDS9300_CONTROL | APDS9300_CMD, cmd);
180*4882a593Smuzhiyun if (ret) {
181*4882a593Smuzhiyun dev_err(&data->client->dev,
182*4882a593Smuzhiyun "failed to set power state %d\n", state);
183*4882a593Smuzhiyun return ret;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun data->power_state = state;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun return 0;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
apds9300_clear_intr(struct apds9300_data * data)190*4882a593Smuzhiyun static void apds9300_clear_intr(struct apds9300_data *data)
191*4882a593Smuzhiyun {
192*4882a593Smuzhiyun int ret;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun ret = i2c_smbus_write_byte(data->client, APDS9300_CLEAR | APDS9300_CMD);
195*4882a593Smuzhiyun if (ret < 0)
196*4882a593Smuzhiyun dev_err(&data->client->dev, "failed to clear interrupt\n");
197*4882a593Smuzhiyun }
198*4882a593Smuzhiyun
apds9300_chip_init(struct apds9300_data * data)199*4882a593Smuzhiyun static int apds9300_chip_init(struct apds9300_data *data)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun int ret;
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun /* Need to set power off to ensure that the chip is off */
204*4882a593Smuzhiyun ret = apds9300_set_power_state(data, 0);
205*4882a593Smuzhiyun if (ret < 0)
206*4882a593Smuzhiyun goto err;
207*4882a593Smuzhiyun /*
208*4882a593Smuzhiyun * Probe the chip. To do so we try to power up the device and then to
209*4882a593Smuzhiyun * read back the 0x03 code
210*4882a593Smuzhiyun */
211*4882a593Smuzhiyun ret = apds9300_set_power_state(data, 1);
212*4882a593Smuzhiyun if (ret < 0)
213*4882a593Smuzhiyun goto err;
214*4882a593Smuzhiyun ret = i2c_smbus_read_byte_data(data->client,
215*4882a593Smuzhiyun APDS9300_CONTROL | APDS9300_CMD);
216*4882a593Smuzhiyun if (ret != APDS9300_POWER_ON) {
217*4882a593Smuzhiyun ret = -ENODEV;
218*4882a593Smuzhiyun goto err;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun /*
221*4882a593Smuzhiyun * Disable interrupt to ensure thai it is doesn't enable
222*4882a593Smuzhiyun * i.e. after device soft reset
223*4882a593Smuzhiyun */
224*4882a593Smuzhiyun ret = apds9300_set_intr_state(data, 0);
225*4882a593Smuzhiyun if (ret < 0)
226*4882a593Smuzhiyun goto err;
227*4882a593Smuzhiyun
228*4882a593Smuzhiyun return 0;
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun err:
231*4882a593Smuzhiyun dev_err(&data->client->dev, "failed to init the chip\n");
232*4882a593Smuzhiyun return ret;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
apds9300_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)235*4882a593Smuzhiyun static int apds9300_read_raw(struct iio_dev *indio_dev,
236*4882a593Smuzhiyun struct iio_chan_spec const *chan, int *val, int *val2,
237*4882a593Smuzhiyun long mask)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun int ch0, ch1, ret = -EINVAL;
240*4882a593Smuzhiyun struct apds9300_data *data = iio_priv(indio_dev);
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun mutex_lock(&data->mutex);
243*4882a593Smuzhiyun switch (chan->type) {
244*4882a593Smuzhiyun case IIO_LIGHT:
245*4882a593Smuzhiyun ch0 = apds9300_get_adc_val(data, 0);
246*4882a593Smuzhiyun if (ch0 < 0) {
247*4882a593Smuzhiyun ret = ch0;
248*4882a593Smuzhiyun break;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun ch1 = apds9300_get_adc_val(data, 1);
251*4882a593Smuzhiyun if (ch1 < 0) {
252*4882a593Smuzhiyun ret = ch1;
253*4882a593Smuzhiyun break;
254*4882a593Smuzhiyun }
255*4882a593Smuzhiyun *val = apds9300_calculate_lux(ch0, ch1);
256*4882a593Smuzhiyun ret = IIO_VAL_INT;
257*4882a593Smuzhiyun break;
258*4882a593Smuzhiyun case IIO_INTENSITY:
259*4882a593Smuzhiyun ret = apds9300_get_adc_val(data, chan->channel);
260*4882a593Smuzhiyun if (ret < 0)
261*4882a593Smuzhiyun break;
262*4882a593Smuzhiyun *val = ret;
263*4882a593Smuzhiyun ret = IIO_VAL_INT;
264*4882a593Smuzhiyun break;
265*4882a593Smuzhiyun default:
266*4882a593Smuzhiyun break;
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun mutex_unlock(&data->mutex);
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun return ret;
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun
apds9300_read_thresh(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)273*4882a593Smuzhiyun static int apds9300_read_thresh(struct iio_dev *indio_dev,
274*4882a593Smuzhiyun const struct iio_chan_spec *chan, enum iio_event_type type,
275*4882a593Smuzhiyun enum iio_event_direction dir, enum iio_event_info info,
276*4882a593Smuzhiyun int *val, int *val2)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun struct apds9300_data *data = iio_priv(indio_dev);
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun switch (dir) {
281*4882a593Smuzhiyun case IIO_EV_DIR_RISING:
282*4882a593Smuzhiyun *val = data->thresh_hi;
283*4882a593Smuzhiyun break;
284*4882a593Smuzhiyun case IIO_EV_DIR_FALLING:
285*4882a593Smuzhiyun *val = data->thresh_low;
286*4882a593Smuzhiyun break;
287*4882a593Smuzhiyun default:
288*4882a593Smuzhiyun return -EINVAL;
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun return IIO_VAL_INT;
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun
apds9300_write_thresh(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)294*4882a593Smuzhiyun static int apds9300_write_thresh(struct iio_dev *indio_dev,
295*4882a593Smuzhiyun const struct iio_chan_spec *chan, enum iio_event_type type,
296*4882a593Smuzhiyun enum iio_event_direction dir, enum iio_event_info info, int val,
297*4882a593Smuzhiyun int val2)
298*4882a593Smuzhiyun {
299*4882a593Smuzhiyun struct apds9300_data *data = iio_priv(indio_dev);
300*4882a593Smuzhiyun int ret;
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun mutex_lock(&data->mutex);
303*4882a593Smuzhiyun if (dir == IIO_EV_DIR_RISING)
304*4882a593Smuzhiyun ret = apds9300_set_thresh_hi(data, val);
305*4882a593Smuzhiyun else
306*4882a593Smuzhiyun ret = apds9300_set_thresh_low(data, val);
307*4882a593Smuzhiyun mutex_unlock(&data->mutex);
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun return ret;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
apds9300_read_interrupt_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)312*4882a593Smuzhiyun static int apds9300_read_interrupt_config(struct iio_dev *indio_dev,
313*4882a593Smuzhiyun const struct iio_chan_spec *chan,
314*4882a593Smuzhiyun enum iio_event_type type,
315*4882a593Smuzhiyun enum iio_event_direction dir)
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun struct apds9300_data *data = iio_priv(indio_dev);
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun return data->intr_en;
320*4882a593Smuzhiyun }
321*4882a593Smuzhiyun
apds9300_write_interrupt_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)322*4882a593Smuzhiyun static int apds9300_write_interrupt_config(struct iio_dev *indio_dev,
323*4882a593Smuzhiyun const struct iio_chan_spec *chan, enum iio_event_type type,
324*4882a593Smuzhiyun enum iio_event_direction dir, int state)
325*4882a593Smuzhiyun {
326*4882a593Smuzhiyun struct apds9300_data *data = iio_priv(indio_dev);
327*4882a593Smuzhiyun int ret;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun mutex_lock(&data->mutex);
330*4882a593Smuzhiyun ret = apds9300_set_intr_state(data, state);
331*4882a593Smuzhiyun mutex_unlock(&data->mutex);
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun return ret;
334*4882a593Smuzhiyun }
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun static const struct iio_info apds9300_info_no_irq = {
337*4882a593Smuzhiyun .read_raw = apds9300_read_raw,
338*4882a593Smuzhiyun };
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun static const struct iio_info apds9300_info = {
341*4882a593Smuzhiyun .read_raw = apds9300_read_raw,
342*4882a593Smuzhiyun .read_event_value = apds9300_read_thresh,
343*4882a593Smuzhiyun .write_event_value = apds9300_write_thresh,
344*4882a593Smuzhiyun .read_event_config = apds9300_read_interrupt_config,
345*4882a593Smuzhiyun .write_event_config = apds9300_write_interrupt_config,
346*4882a593Smuzhiyun };
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun static const struct iio_event_spec apds9300_event_spec[] = {
349*4882a593Smuzhiyun {
350*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
351*4882a593Smuzhiyun .dir = IIO_EV_DIR_RISING,
352*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_VALUE) |
353*4882a593Smuzhiyun BIT(IIO_EV_INFO_ENABLE),
354*4882a593Smuzhiyun }, {
355*4882a593Smuzhiyun .type = IIO_EV_TYPE_THRESH,
356*4882a593Smuzhiyun .dir = IIO_EV_DIR_FALLING,
357*4882a593Smuzhiyun .mask_separate = BIT(IIO_EV_INFO_VALUE) |
358*4882a593Smuzhiyun BIT(IIO_EV_INFO_ENABLE),
359*4882a593Smuzhiyun },
360*4882a593Smuzhiyun };
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun static const struct iio_chan_spec apds9300_channels[] = {
363*4882a593Smuzhiyun {
364*4882a593Smuzhiyun .type = IIO_LIGHT,
365*4882a593Smuzhiyun .channel = 0,
366*4882a593Smuzhiyun .indexed = true,
367*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
368*4882a593Smuzhiyun }, {
369*4882a593Smuzhiyun .type = IIO_INTENSITY,
370*4882a593Smuzhiyun .channel = 0,
371*4882a593Smuzhiyun .channel2 = IIO_MOD_LIGHT_BOTH,
372*4882a593Smuzhiyun .indexed = true,
373*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
374*4882a593Smuzhiyun .event_spec = apds9300_event_spec,
375*4882a593Smuzhiyun .num_event_specs = ARRAY_SIZE(apds9300_event_spec),
376*4882a593Smuzhiyun }, {
377*4882a593Smuzhiyun .type = IIO_INTENSITY,
378*4882a593Smuzhiyun .channel = 1,
379*4882a593Smuzhiyun .channel2 = IIO_MOD_LIGHT_IR,
380*4882a593Smuzhiyun .indexed = true,
381*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
382*4882a593Smuzhiyun },
383*4882a593Smuzhiyun };
384*4882a593Smuzhiyun
apds9300_interrupt_handler(int irq,void * private)385*4882a593Smuzhiyun static irqreturn_t apds9300_interrupt_handler(int irq, void *private)
386*4882a593Smuzhiyun {
387*4882a593Smuzhiyun struct iio_dev *dev_info = private;
388*4882a593Smuzhiyun struct apds9300_data *data = iio_priv(dev_info);
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun iio_push_event(dev_info,
391*4882a593Smuzhiyun IIO_UNMOD_EVENT_CODE(IIO_INTENSITY, 0,
392*4882a593Smuzhiyun IIO_EV_TYPE_THRESH,
393*4882a593Smuzhiyun IIO_EV_DIR_EITHER),
394*4882a593Smuzhiyun iio_get_time_ns(dev_info));
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun apds9300_clear_intr(data);
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun return IRQ_HANDLED;
399*4882a593Smuzhiyun }
400*4882a593Smuzhiyun
apds9300_probe(struct i2c_client * client,const struct i2c_device_id * id)401*4882a593Smuzhiyun static int apds9300_probe(struct i2c_client *client,
402*4882a593Smuzhiyun const struct i2c_device_id *id)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun struct apds9300_data *data;
405*4882a593Smuzhiyun struct iio_dev *indio_dev;
406*4882a593Smuzhiyun int ret;
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
409*4882a593Smuzhiyun if (!indio_dev)
410*4882a593Smuzhiyun return -ENOMEM;
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun data = iio_priv(indio_dev);
413*4882a593Smuzhiyun i2c_set_clientdata(client, indio_dev);
414*4882a593Smuzhiyun data->client = client;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun ret = apds9300_chip_init(data);
417*4882a593Smuzhiyun if (ret < 0)
418*4882a593Smuzhiyun goto err;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun mutex_init(&data->mutex);
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun indio_dev->channels = apds9300_channels;
423*4882a593Smuzhiyun indio_dev->num_channels = ARRAY_SIZE(apds9300_channels);
424*4882a593Smuzhiyun indio_dev->name = APDS9300_DRV_NAME;
425*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun if (client->irq)
428*4882a593Smuzhiyun indio_dev->info = &apds9300_info;
429*4882a593Smuzhiyun else
430*4882a593Smuzhiyun indio_dev->info = &apds9300_info_no_irq;
431*4882a593Smuzhiyun
432*4882a593Smuzhiyun if (client->irq) {
433*4882a593Smuzhiyun ret = devm_request_threaded_irq(&client->dev, client->irq,
434*4882a593Smuzhiyun NULL, apds9300_interrupt_handler,
435*4882a593Smuzhiyun IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
436*4882a593Smuzhiyun APDS9300_IRQ_NAME, indio_dev);
437*4882a593Smuzhiyun if (ret) {
438*4882a593Smuzhiyun dev_err(&client->dev, "irq request error %d\n", -ret);
439*4882a593Smuzhiyun goto err;
440*4882a593Smuzhiyun }
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun ret = iio_device_register(indio_dev);
444*4882a593Smuzhiyun if (ret < 0)
445*4882a593Smuzhiyun goto err;
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun return 0;
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun err:
450*4882a593Smuzhiyun /* Ensure that power off in case of error */
451*4882a593Smuzhiyun apds9300_set_power_state(data, 0);
452*4882a593Smuzhiyun return ret;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
apds9300_remove(struct i2c_client * client)455*4882a593Smuzhiyun static int apds9300_remove(struct i2c_client *client)
456*4882a593Smuzhiyun {
457*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(client);
458*4882a593Smuzhiyun struct apds9300_data *data = iio_priv(indio_dev);
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun iio_device_unregister(indio_dev);
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun /* Ensure that power off and interrupts are disabled */
463*4882a593Smuzhiyun apds9300_set_intr_state(data, 0);
464*4882a593Smuzhiyun apds9300_set_power_state(data, 0);
465*4882a593Smuzhiyun
466*4882a593Smuzhiyun return 0;
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun #ifdef CONFIG_PM_SLEEP
apds9300_suspend(struct device * dev)470*4882a593Smuzhiyun static int apds9300_suspend(struct device *dev)
471*4882a593Smuzhiyun {
472*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
473*4882a593Smuzhiyun struct apds9300_data *data = iio_priv(indio_dev);
474*4882a593Smuzhiyun int ret;
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun mutex_lock(&data->mutex);
477*4882a593Smuzhiyun ret = apds9300_set_power_state(data, 0);
478*4882a593Smuzhiyun mutex_unlock(&data->mutex);
479*4882a593Smuzhiyun
480*4882a593Smuzhiyun return ret;
481*4882a593Smuzhiyun }
482*4882a593Smuzhiyun
apds9300_resume(struct device * dev)483*4882a593Smuzhiyun static int apds9300_resume(struct device *dev)
484*4882a593Smuzhiyun {
485*4882a593Smuzhiyun struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
486*4882a593Smuzhiyun struct apds9300_data *data = iio_priv(indio_dev);
487*4882a593Smuzhiyun int ret;
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun mutex_lock(&data->mutex);
490*4882a593Smuzhiyun ret = apds9300_set_power_state(data, 1);
491*4882a593Smuzhiyun mutex_unlock(&data->mutex);
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun return ret;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun static SIMPLE_DEV_PM_OPS(apds9300_pm_ops, apds9300_suspend, apds9300_resume);
497*4882a593Smuzhiyun #define APDS9300_PM_OPS (&apds9300_pm_ops)
498*4882a593Smuzhiyun #else
499*4882a593Smuzhiyun #define APDS9300_PM_OPS NULL
500*4882a593Smuzhiyun #endif
501*4882a593Smuzhiyun
502*4882a593Smuzhiyun static const struct i2c_device_id apds9300_id[] = {
503*4882a593Smuzhiyun { APDS9300_DRV_NAME, 0 },
504*4882a593Smuzhiyun { }
505*4882a593Smuzhiyun };
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, apds9300_id);
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun static struct i2c_driver apds9300_driver = {
510*4882a593Smuzhiyun .driver = {
511*4882a593Smuzhiyun .name = APDS9300_DRV_NAME,
512*4882a593Smuzhiyun .pm = APDS9300_PM_OPS,
513*4882a593Smuzhiyun },
514*4882a593Smuzhiyun .probe = apds9300_probe,
515*4882a593Smuzhiyun .remove = apds9300_remove,
516*4882a593Smuzhiyun .id_table = apds9300_id,
517*4882a593Smuzhiyun };
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun module_i2c_driver(apds9300_driver);
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun MODULE_AUTHOR("Kravchenko Oleksandr <o.v.kravchenko@globallogic.com>");
522*4882a593Smuzhiyun MODULE_AUTHOR("GlobalLogic inc.");
523*4882a593Smuzhiyun MODULE_DESCRIPTION("APDS9300 ambient light photo sensor driver");
524*4882a593Smuzhiyun MODULE_LICENSE("GPL");
525