xref: /OK3568_Linux_fs/kernel/drivers/iio/imu/st_lsm6dsx/st_lsm6dsx.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * STMicroelectronics st_lsm6dsx sensor driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2016 STMicroelectronics Inc.
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Lorenzo Bianconi <lorenzo.bianconi@st.com>
8*4882a593Smuzhiyun  * Denis Ciocca <denis.ciocca@st.com>
9*4882a593Smuzhiyun  */
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #ifndef ST_LSM6DSX_H
12*4882a593Smuzhiyun #define ST_LSM6DSX_H
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <linux/device.h>
15*4882a593Smuzhiyun #include <linux/iio/iio.h>
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define ST_LSM6DS3_DEV_NAME	"lsm6ds3"
18*4882a593Smuzhiyun #define ST_LSM6DS3H_DEV_NAME	"lsm6ds3h"
19*4882a593Smuzhiyun #define ST_LSM6DSL_DEV_NAME	"lsm6dsl"
20*4882a593Smuzhiyun #define ST_LSM6DSM_DEV_NAME	"lsm6dsm"
21*4882a593Smuzhiyun #define ST_ISM330DLC_DEV_NAME	"ism330dlc"
22*4882a593Smuzhiyun #define ST_LSM6DSO_DEV_NAME	"lsm6dso"
23*4882a593Smuzhiyun #define ST_ASM330LHH_DEV_NAME	"asm330lhh"
24*4882a593Smuzhiyun #define ST_LSM6DSOX_DEV_NAME	"lsm6dsox"
25*4882a593Smuzhiyun #define ST_LSM6DSR_DEV_NAME	"lsm6dsr"
26*4882a593Smuzhiyun #define ST_LSM6DS3TRC_DEV_NAME	"lsm6ds3tr-c"
27*4882a593Smuzhiyun #define ST_ISM330DHCX_DEV_NAME	"ism330dhcx"
28*4882a593Smuzhiyun #define ST_LSM9DS1_DEV_NAME	"lsm9ds1-imu"
29*4882a593Smuzhiyun #define ST_LSM6DS0_DEV_NAME	"lsm6ds0"
30*4882a593Smuzhiyun #define ST_LSM6DSRX_DEV_NAME	"lsm6dsrx"
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun enum st_lsm6dsx_hw_id {
33*4882a593Smuzhiyun 	ST_LSM6DS3_ID,
34*4882a593Smuzhiyun 	ST_LSM6DS3H_ID,
35*4882a593Smuzhiyun 	ST_LSM6DSL_ID,
36*4882a593Smuzhiyun 	ST_LSM6DSM_ID,
37*4882a593Smuzhiyun 	ST_ISM330DLC_ID,
38*4882a593Smuzhiyun 	ST_LSM6DSO_ID,
39*4882a593Smuzhiyun 	ST_ASM330LHH_ID,
40*4882a593Smuzhiyun 	ST_LSM6DSOX_ID,
41*4882a593Smuzhiyun 	ST_LSM6DSR_ID,
42*4882a593Smuzhiyun 	ST_LSM6DS3TRC_ID,
43*4882a593Smuzhiyun 	ST_ISM330DHCX_ID,
44*4882a593Smuzhiyun 	ST_LSM9DS1_ID,
45*4882a593Smuzhiyun 	ST_LSM6DS0_ID,
46*4882a593Smuzhiyun 	ST_LSM6DSRX_ID,
47*4882a593Smuzhiyun 	ST_LSM6DSX_MAX_ID,
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #define ST_LSM6DSX_BUFF_SIZE		512
51*4882a593Smuzhiyun #define ST_LSM6DSX_CHAN_SIZE		2
52*4882a593Smuzhiyun #define ST_LSM6DSX_SAMPLE_SIZE		6
53*4882a593Smuzhiyun #define ST_LSM6DSX_TAG_SIZE		1
54*4882a593Smuzhiyun #define ST_LSM6DSX_TAGGED_SAMPLE_SIZE	(ST_LSM6DSX_SAMPLE_SIZE + \
55*4882a593Smuzhiyun 					 ST_LSM6DSX_TAG_SIZE)
56*4882a593Smuzhiyun #define ST_LSM6DSX_MAX_WORD_LEN		((32 / ST_LSM6DSX_SAMPLE_SIZE) * \
57*4882a593Smuzhiyun 					 ST_LSM6DSX_SAMPLE_SIZE)
58*4882a593Smuzhiyun #define ST_LSM6DSX_MAX_TAGGED_WORD_LEN	((32 / ST_LSM6DSX_TAGGED_SAMPLE_SIZE) \
59*4882a593Smuzhiyun 					 * ST_LSM6DSX_TAGGED_SAMPLE_SIZE)
60*4882a593Smuzhiyun #define ST_LSM6DSX_SHIFT_VAL(val, mask)	(((val) << __ffs(mask)) & (mask))
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun #define ST_LSM6DSX_CHANNEL_ACC(chan_type, addr, mod, scan_idx)		\
63*4882a593Smuzhiyun {									\
64*4882a593Smuzhiyun 	.type = chan_type,						\
65*4882a593Smuzhiyun 	.address = addr,						\
66*4882a593Smuzhiyun 	.modified = 1,							\
67*4882a593Smuzhiyun 	.channel2 = mod,						\
68*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\
69*4882a593Smuzhiyun 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),		\
70*4882a593Smuzhiyun 	.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
71*4882a593Smuzhiyun 	.scan_index = scan_idx,						\
72*4882a593Smuzhiyun 	.scan_type = {							\
73*4882a593Smuzhiyun 		.sign = 's',						\
74*4882a593Smuzhiyun 		.realbits = 16,						\
75*4882a593Smuzhiyun 		.storagebits = 16,					\
76*4882a593Smuzhiyun 		.endianness = IIO_LE,					\
77*4882a593Smuzhiyun 	},								\
78*4882a593Smuzhiyun 	.event_spec = &st_lsm6dsx_event,				\
79*4882a593Smuzhiyun 	.ext_info = st_lsm6dsx_accel_ext_info,				\
80*4882a593Smuzhiyun 	.num_event_specs = 1,						\
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun #define ST_LSM6DSX_CHANNEL(chan_type, addr, mod, scan_idx)		\
84*4882a593Smuzhiyun {									\
85*4882a593Smuzhiyun 	.type = chan_type,						\
86*4882a593Smuzhiyun 	.address = addr,						\
87*4882a593Smuzhiyun 	.modified = 1,							\
88*4882a593Smuzhiyun 	.channel2 = mod,						\
89*4882a593Smuzhiyun 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),			\
90*4882a593Smuzhiyun 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),		\
91*4882a593Smuzhiyun 	.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),	\
92*4882a593Smuzhiyun 	.scan_index = scan_idx,						\
93*4882a593Smuzhiyun 	.scan_type = {							\
94*4882a593Smuzhiyun 		.sign = 's',						\
95*4882a593Smuzhiyun 		.realbits = 16,						\
96*4882a593Smuzhiyun 		.storagebits = 16,					\
97*4882a593Smuzhiyun 		.endianness = IIO_LE,					\
98*4882a593Smuzhiyun 	},								\
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun struct st_lsm6dsx_reg {
102*4882a593Smuzhiyun 	u8 addr;
103*4882a593Smuzhiyun 	u8 mask;
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun struct st_lsm6dsx_sensor;
107*4882a593Smuzhiyun struct st_lsm6dsx_hw;
108*4882a593Smuzhiyun 
109*4882a593Smuzhiyun struct st_lsm6dsx_odr {
110*4882a593Smuzhiyun 	u32 milli_hz;
111*4882a593Smuzhiyun 	u8 val;
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun #define ST_LSM6DSX_ODR_LIST_SIZE	8
115*4882a593Smuzhiyun struct st_lsm6dsx_odr_table_entry {
116*4882a593Smuzhiyun 	struct st_lsm6dsx_reg reg;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	struct st_lsm6dsx_odr odr_avl[ST_LSM6DSX_ODR_LIST_SIZE];
119*4882a593Smuzhiyun 	int odr_len;
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun struct st_lsm6dsx_fs {
123*4882a593Smuzhiyun 	u32 gain;
124*4882a593Smuzhiyun 	u8 val;
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun #define ST_LSM6DSX_FS_LIST_SIZE		4
128*4882a593Smuzhiyun struct st_lsm6dsx_fs_table_entry {
129*4882a593Smuzhiyun 	struct st_lsm6dsx_reg reg;
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	struct st_lsm6dsx_fs fs_avl[ST_LSM6DSX_FS_LIST_SIZE];
132*4882a593Smuzhiyun 	int fs_len;
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun /**
136*4882a593Smuzhiyun  * struct st_lsm6dsx_fifo_ops - ST IMU FIFO settings
137*4882a593Smuzhiyun  * @update_fifo: Update FIFO configuration callback.
138*4882a593Smuzhiyun  * @read_fifo: Read FIFO callback.
139*4882a593Smuzhiyun  * @fifo_th: FIFO threshold register info (addr + mask).
140*4882a593Smuzhiyun  * @fifo_diff: FIFO diff status register info (addr + mask).
141*4882a593Smuzhiyun  * @th_wl: FIFO threshold word length.
142*4882a593Smuzhiyun  */
143*4882a593Smuzhiyun struct st_lsm6dsx_fifo_ops {
144*4882a593Smuzhiyun 	int (*update_fifo)(struct st_lsm6dsx_sensor *sensor, bool enable);
145*4882a593Smuzhiyun 	int (*read_fifo)(struct st_lsm6dsx_hw *hw);
146*4882a593Smuzhiyun 	struct {
147*4882a593Smuzhiyun 		u8 addr;
148*4882a593Smuzhiyun 		u16 mask;
149*4882a593Smuzhiyun 	} fifo_th;
150*4882a593Smuzhiyun 	struct {
151*4882a593Smuzhiyun 		u8 addr;
152*4882a593Smuzhiyun 		u16 mask;
153*4882a593Smuzhiyun 	} fifo_diff;
154*4882a593Smuzhiyun 	u8 th_wl;
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun /**
158*4882a593Smuzhiyun  * struct st_lsm6dsx_hw_ts_settings - ST IMU hw timer settings
159*4882a593Smuzhiyun  * @timer_en: Hw timer enable register info (addr + mask).
160*4882a593Smuzhiyun  * @hr_timer: Hw timer resolution register info (addr + mask).
161*4882a593Smuzhiyun  * @fifo_en: Hw timer FIFO enable register info (addr + mask).
162*4882a593Smuzhiyun  * @decimator: Hw timer FIFO decimator register info (addr + mask).
163*4882a593Smuzhiyun  * @freq_fine: Difference in % of ODR with respect to the typical.
164*4882a593Smuzhiyun  */
165*4882a593Smuzhiyun struct st_lsm6dsx_hw_ts_settings {
166*4882a593Smuzhiyun 	struct st_lsm6dsx_reg timer_en;
167*4882a593Smuzhiyun 	struct st_lsm6dsx_reg hr_timer;
168*4882a593Smuzhiyun 	struct st_lsm6dsx_reg fifo_en;
169*4882a593Smuzhiyun 	struct st_lsm6dsx_reg decimator;
170*4882a593Smuzhiyun 	u8 freq_fine;
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun /**
174*4882a593Smuzhiyun  * struct st_lsm6dsx_shub_settings - ST IMU hw i2c controller settings
175*4882a593Smuzhiyun  * @page_mux: register page mux info (addr + mask).
176*4882a593Smuzhiyun  * @master_en: master config register info (addr + mask).
177*4882a593Smuzhiyun  * @pullup_en: i2c controller pull-up register info (addr + mask).
178*4882a593Smuzhiyun  * @aux_sens: aux sensor register info (addr + mask).
179*4882a593Smuzhiyun  * @wr_once: write_once register info (addr + mask).
180*4882a593Smuzhiyun  * @emb_func:  embedded function register info (addr + mask).
181*4882a593Smuzhiyun  * @num_ext_dev: max number of slave devices.
182*4882a593Smuzhiyun  * @shub_out: sensor hub first output register info.
183*4882a593Smuzhiyun  * @slv0_addr: slave0 address in secondary page.
184*4882a593Smuzhiyun  * @dw_slv0_addr: slave0 write register address in secondary page.
185*4882a593Smuzhiyun  * @batch_en: Enable/disable FIFO batching.
186*4882a593Smuzhiyun  * @pause: controller pause value.
187*4882a593Smuzhiyun  */
188*4882a593Smuzhiyun struct st_lsm6dsx_shub_settings {
189*4882a593Smuzhiyun 	struct st_lsm6dsx_reg page_mux;
190*4882a593Smuzhiyun 	struct {
191*4882a593Smuzhiyun 		bool sec_page;
192*4882a593Smuzhiyun 		u8 addr;
193*4882a593Smuzhiyun 		u8 mask;
194*4882a593Smuzhiyun 	} master_en;
195*4882a593Smuzhiyun 	struct {
196*4882a593Smuzhiyun 		bool sec_page;
197*4882a593Smuzhiyun 		u8 addr;
198*4882a593Smuzhiyun 		u8 mask;
199*4882a593Smuzhiyun 	} pullup_en;
200*4882a593Smuzhiyun 	struct st_lsm6dsx_reg aux_sens;
201*4882a593Smuzhiyun 	struct st_lsm6dsx_reg wr_once;
202*4882a593Smuzhiyun 	struct st_lsm6dsx_reg emb_func;
203*4882a593Smuzhiyun 	u8 num_ext_dev;
204*4882a593Smuzhiyun 	struct {
205*4882a593Smuzhiyun 		bool sec_page;
206*4882a593Smuzhiyun 		u8 addr;
207*4882a593Smuzhiyun 	} shub_out;
208*4882a593Smuzhiyun 	u8 slv0_addr;
209*4882a593Smuzhiyun 	u8 dw_slv0_addr;
210*4882a593Smuzhiyun 	u8 batch_en;
211*4882a593Smuzhiyun 	u8 pause;
212*4882a593Smuzhiyun };
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun struct st_lsm6dsx_event_settings {
215*4882a593Smuzhiyun 	struct st_lsm6dsx_reg enable_reg;
216*4882a593Smuzhiyun 	struct st_lsm6dsx_reg wakeup_reg;
217*4882a593Smuzhiyun 	u8 wakeup_src_reg;
218*4882a593Smuzhiyun 	u8 wakeup_src_status_mask;
219*4882a593Smuzhiyun 	u8 wakeup_src_z_mask;
220*4882a593Smuzhiyun 	u8 wakeup_src_y_mask;
221*4882a593Smuzhiyun 	u8 wakeup_src_x_mask;
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun enum st_lsm6dsx_ext_sensor_id {
225*4882a593Smuzhiyun 	ST_LSM6DSX_ID_MAGN,
226*4882a593Smuzhiyun };
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun /**
229*4882a593Smuzhiyun  * struct st_lsm6dsx_ext_dev_settings - i2c controller slave settings
230*4882a593Smuzhiyun  * @i2c_addr: I2c slave address list.
231*4882a593Smuzhiyun  * @wai: Wai address info.
232*4882a593Smuzhiyun  * @id: external sensor id.
233*4882a593Smuzhiyun  * @odr_table: Output data rate of the sensor [Hz].
234*4882a593Smuzhiyun  * @fs_table: Configured sensor sensitivity table depending on full scale.
235*4882a593Smuzhiyun  * @temp_comp: Temperature compensation register info (addr + mask).
236*4882a593Smuzhiyun  * @pwr_table: Power on register info (addr + mask).
237*4882a593Smuzhiyun  * @off_canc: Offset cancellation register info (addr + mask).
238*4882a593Smuzhiyun  * @bdu: Block data update register info (addr + mask).
239*4882a593Smuzhiyun  * @out: Output register info.
240*4882a593Smuzhiyun  */
241*4882a593Smuzhiyun struct st_lsm6dsx_ext_dev_settings {
242*4882a593Smuzhiyun 	u8 i2c_addr[2];
243*4882a593Smuzhiyun 	struct {
244*4882a593Smuzhiyun 		u8 addr;
245*4882a593Smuzhiyun 		u8 val;
246*4882a593Smuzhiyun 	} wai;
247*4882a593Smuzhiyun 	enum st_lsm6dsx_ext_sensor_id id;
248*4882a593Smuzhiyun 	struct st_lsm6dsx_odr_table_entry odr_table;
249*4882a593Smuzhiyun 	struct st_lsm6dsx_fs_table_entry fs_table;
250*4882a593Smuzhiyun 	struct st_lsm6dsx_reg temp_comp;
251*4882a593Smuzhiyun 	struct {
252*4882a593Smuzhiyun 		struct st_lsm6dsx_reg reg;
253*4882a593Smuzhiyun 		u8 off_val;
254*4882a593Smuzhiyun 		u8 on_val;
255*4882a593Smuzhiyun 	} pwr_table;
256*4882a593Smuzhiyun 	struct st_lsm6dsx_reg off_canc;
257*4882a593Smuzhiyun 	struct st_lsm6dsx_reg bdu;
258*4882a593Smuzhiyun 	struct {
259*4882a593Smuzhiyun 		u8 addr;
260*4882a593Smuzhiyun 		u8 len;
261*4882a593Smuzhiyun 	} out;
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun /**
265*4882a593Smuzhiyun  * struct st_lsm6dsx_settings - ST IMU sensor settings
266*4882a593Smuzhiyun  * @wai: Sensor WhoAmI default value.
267*4882a593Smuzhiyun  * @reset: register address for reset.
268*4882a593Smuzhiyun  * @boot: register address for boot.
269*4882a593Smuzhiyun  * @bdu: register address for Block Data Update.
270*4882a593Smuzhiyun  * @max_fifo_size: Sensor max fifo length in FIFO words.
271*4882a593Smuzhiyun  * @id: List of hw id/device name supported by the driver configuration.
272*4882a593Smuzhiyun  * @channels: IIO channels supported by the device.
273*4882a593Smuzhiyun  * @irq_config: interrupts related registers.
274*4882a593Smuzhiyun  * @drdy_mask: register info for data-ready mask (addr + mask).
275*4882a593Smuzhiyun  * @odr_table: Hw sensors odr table (Hz + val).
276*4882a593Smuzhiyun  * @fs_table: Hw sensors gain table (gain + val).
277*4882a593Smuzhiyun  * @decimator: List of decimator register info (addr + mask).
278*4882a593Smuzhiyun  * @batch: List of FIFO batching register info (addr + mask).
279*4882a593Smuzhiyun  * @fifo_ops: Sensor hw FIFO parameters.
280*4882a593Smuzhiyun  * @ts_settings: Hw timer related settings.
281*4882a593Smuzhiyun  * @shub_settings: i2c controller related settings.
282*4882a593Smuzhiyun  */
283*4882a593Smuzhiyun struct st_lsm6dsx_settings {
284*4882a593Smuzhiyun 	u8 wai;
285*4882a593Smuzhiyun 	struct st_lsm6dsx_reg reset;
286*4882a593Smuzhiyun 	struct st_lsm6dsx_reg boot;
287*4882a593Smuzhiyun 	struct st_lsm6dsx_reg bdu;
288*4882a593Smuzhiyun 	u16 max_fifo_size;
289*4882a593Smuzhiyun 	struct {
290*4882a593Smuzhiyun 		enum st_lsm6dsx_hw_id hw_id;
291*4882a593Smuzhiyun 		const char *name;
292*4882a593Smuzhiyun 	} id[ST_LSM6DSX_MAX_ID];
293*4882a593Smuzhiyun 	struct {
294*4882a593Smuzhiyun 		const struct iio_chan_spec *chan;
295*4882a593Smuzhiyun 		int len;
296*4882a593Smuzhiyun 	} channels[2];
297*4882a593Smuzhiyun 	struct {
298*4882a593Smuzhiyun 		struct st_lsm6dsx_reg irq1;
299*4882a593Smuzhiyun 		struct st_lsm6dsx_reg irq2;
300*4882a593Smuzhiyun 		struct st_lsm6dsx_reg irq1_func;
301*4882a593Smuzhiyun 		struct st_lsm6dsx_reg irq2_func;
302*4882a593Smuzhiyun 		struct st_lsm6dsx_reg lir;
303*4882a593Smuzhiyun 		struct st_lsm6dsx_reg clear_on_read;
304*4882a593Smuzhiyun 		struct st_lsm6dsx_reg hla;
305*4882a593Smuzhiyun 		struct st_lsm6dsx_reg od;
306*4882a593Smuzhiyun 	} irq_config;
307*4882a593Smuzhiyun 	struct st_lsm6dsx_reg drdy_mask;
308*4882a593Smuzhiyun 	struct st_lsm6dsx_odr_table_entry odr_table[2];
309*4882a593Smuzhiyun 	struct st_lsm6dsx_fs_table_entry fs_table[2];
310*4882a593Smuzhiyun 	struct st_lsm6dsx_reg decimator[ST_LSM6DSX_MAX_ID];
311*4882a593Smuzhiyun 	struct st_lsm6dsx_reg batch[ST_LSM6DSX_MAX_ID];
312*4882a593Smuzhiyun 	struct st_lsm6dsx_fifo_ops fifo_ops;
313*4882a593Smuzhiyun 	struct st_lsm6dsx_hw_ts_settings ts_settings;
314*4882a593Smuzhiyun 	struct st_lsm6dsx_shub_settings shub_settings;
315*4882a593Smuzhiyun 	struct st_lsm6dsx_event_settings event_settings;
316*4882a593Smuzhiyun };
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun enum st_lsm6dsx_sensor_id {
319*4882a593Smuzhiyun 	ST_LSM6DSX_ID_GYRO,
320*4882a593Smuzhiyun 	ST_LSM6DSX_ID_ACC,
321*4882a593Smuzhiyun 	ST_LSM6DSX_ID_EXT0,
322*4882a593Smuzhiyun 	ST_LSM6DSX_ID_EXT1,
323*4882a593Smuzhiyun 	ST_LSM6DSX_ID_EXT2,
324*4882a593Smuzhiyun 	ST_LSM6DSX_ID_MAX,
325*4882a593Smuzhiyun };
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun enum st_lsm6dsx_fifo_mode {
328*4882a593Smuzhiyun 	ST_LSM6DSX_FIFO_BYPASS = 0x0,
329*4882a593Smuzhiyun 	ST_LSM6DSX_FIFO_CONT = 0x6,
330*4882a593Smuzhiyun };
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun /**
333*4882a593Smuzhiyun  * struct st_lsm6dsx_sensor - ST IMU sensor instance
334*4882a593Smuzhiyun  * @name: Sensor name.
335*4882a593Smuzhiyun  * @id: Sensor identifier.
336*4882a593Smuzhiyun  * @hw: Pointer to instance of struct st_lsm6dsx_hw.
337*4882a593Smuzhiyun  * @gain: Configured sensor sensitivity.
338*4882a593Smuzhiyun  * @odr: Output data rate of the sensor [Hz].
339*4882a593Smuzhiyun  * @watermark: Sensor watermark level.
340*4882a593Smuzhiyun  * @decimator: Sensor decimation factor.
341*4882a593Smuzhiyun  * @sip: Number of samples in a given pattern.
342*4882a593Smuzhiyun  * @ts_ref: Sensor timestamp reference for hw one.
343*4882a593Smuzhiyun  * @ext_info: Sensor settings if it is connected to i2c controller
344*4882a593Smuzhiyun  */
345*4882a593Smuzhiyun struct st_lsm6dsx_sensor {
346*4882a593Smuzhiyun 	char name[32];
347*4882a593Smuzhiyun 	enum st_lsm6dsx_sensor_id id;
348*4882a593Smuzhiyun 	struct st_lsm6dsx_hw *hw;
349*4882a593Smuzhiyun 
350*4882a593Smuzhiyun 	u32 gain;
351*4882a593Smuzhiyun 	u32 odr;
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun 	u16 watermark;
354*4882a593Smuzhiyun 	u8 decimator;
355*4882a593Smuzhiyun 	u8 sip;
356*4882a593Smuzhiyun 	s64 ts_ref;
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	struct {
359*4882a593Smuzhiyun 		const struct st_lsm6dsx_ext_dev_settings *settings;
360*4882a593Smuzhiyun 		u32 slv_odr;
361*4882a593Smuzhiyun 		u8 addr;
362*4882a593Smuzhiyun 	} ext_info;
363*4882a593Smuzhiyun };
364*4882a593Smuzhiyun 
365*4882a593Smuzhiyun /**
366*4882a593Smuzhiyun  * struct st_lsm6dsx_hw - ST IMU MEMS hw instance
367*4882a593Smuzhiyun  * @dev: Pointer to instance of struct device (I2C or SPI).
368*4882a593Smuzhiyun  * @regmap: Register map of the device.
369*4882a593Smuzhiyun  * @irq: Device interrupt line (I2C or SPI).
370*4882a593Smuzhiyun  * @fifo_lock: Mutex to prevent concurrent access to the hw FIFO.
371*4882a593Smuzhiyun  * @conf_lock: Mutex to prevent concurrent FIFO configuration update.
372*4882a593Smuzhiyun  * @page_lock: Mutex to prevent concurrent memory page configuration.
373*4882a593Smuzhiyun  * @suspend_mask: Suspended sensor bitmask.
374*4882a593Smuzhiyun  * @enable_mask: Enabled sensor bitmask.
375*4882a593Smuzhiyun  * @fifo_mask: Enabled hw FIFO bitmask.
376*4882a593Smuzhiyun  * @ts_gain: Hw timestamp rate after internal calibration.
377*4882a593Smuzhiyun  * @ts_sip: Total number of timestamp samples in a given pattern.
378*4882a593Smuzhiyun  * @sip: Total number of samples (acc/gyro/ts) in a given pattern.
379*4882a593Smuzhiyun  * @buff: Device read buffer.
380*4882a593Smuzhiyun  * @irq_routing: pointer to interrupt routing configuration.
381*4882a593Smuzhiyun  * @event_threshold: wakeup event threshold.
382*4882a593Smuzhiyun  * @enable_event: enabled event bitmask.
383*4882a593Smuzhiyun  * @iio_devs: Pointers to acc/gyro iio_dev instances.
384*4882a593Smuzhiyun  * @settings: Pointer to the specific sensor settings in use.
385*4882a593Smuzhiyun  * @orientation: sensor chip orientation relative to main hardware.
386*4882a593Smuzhiyun  * @scan: Temporary buffers used to align data before iio_push_to_buffers()
387*4882a593Smuzhiyun  */
388*4882a593Smuzhiyun struct st_lsm6dsx_hw {
389*4882a593Smuzhiyun 	struct device *dev;
390*4882a593Smuzhiyun 	struct regmap *regmap;
391*4882a593Smuzhiyun 	int irq;
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	struct mutex fifo_lock;
394*4882a593Smuzhiyun 	struct mutex conf_lock;
395*4882a593Smuzhiyun 	struct mutex page_lock;
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	u8 suspend_mask;
398*4882a593Smuzhiyun 	u8 enable_mask;
399*4882a593Smuzhiyun 	u8 fifo_mask;
400*4882a593Smuzhiyun 	s64 ts_gain;
401*4882a593Smuzhiyun 	u8 ts_sip;
402*4882a593Smuzhiyun 	u8 sip;
403*4882a593Smuzhiyun 
404*4882a593Smuzhiyun 	const struct st_lsm6dsx_reg *irq_routing;
405*4882a593Smuzhiyun 	u8 event_threshold;
406*4882a593Smuzhiyun 	u8 enable_event;
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	u8 *buff;
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun 	struct iio_dev *iio_devs[ST_LSM6DSX_ID_MAX];
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	const struct st_lsm6dsx_settings *settings;
413*4882a593Smuzhiyun 
414*4882a593Smuzhiyun 	struct iio_mount_matrix orientation;
415*4882a593Smuzhiyun 	/* Ensure natural alignment of buffer elements */
416*4882a593Smuzhiyun 	struct {
417*4882a593Smuzhiyun 		__le16 channels[3];
418*4882a593Smuzhiyun 		s64 ts __aligned(8);
419*4882a593Smuzhiyun 	} scan[3];
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun static __maybe_unused const struct iio_event_spec st_lsm6dsx_event = {
423*4882a593Smuzhiyun 	.type = IIO_EV_TYPE_THRESH,
424*4882a593Smuzhiyun 	.dir = IIO_EV_DIR_EITHER,
425*4882a593Smuzhiyun 	.mask_separate = BIT(IIO_EV_INFO_VALUE) |
426*4882a593Smuzhiyun 			 BIT(IIO_EV_INFO_ENABLE)
427*4882a593Smuzhiyun };
428*4882a593Smuzhiyun 
429*4882a593Smuzhiyun static __maybe_unused const unsigned long st_lsm6dsx_available_scan_masks[] = {
430*4882a593Smuzhiyun 	0x7, 0x0,
431*4882a593Smuzhiyun };
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun extern const struct dev_pm_ops st_lsm6dsx_pm_ops;
434*4882a593Smuzhiyun 
435*4882a593Smuzhiyun int st_lsm6dsx_probe(struct device *dev, int irq, int hw_id,
436*4882a593Smuzhiyun 		     struct regmap *regmap);
437*4882a593Smuzhiyun int st_lsm6dsx_sensor_set_enable(struct st_lsm6dsx_sensor *sensor,
438*4882a593Smuzhiyun 				 bool enable);
439*4882a593Smuzhiyun int st_lsm6dsx_fifo_setup(struct st_lsm6dsx_hw *hw);
440*4882a593Smuzhiyun int st_lsm6dsx_set_watermark(struct iio_dev *iio_dev, unsigned int val);
441*4882a593Smuzhiyun int st_lsm6dsx_update_watermark(struct st_lsm6dsx_sensor *sensor,
442*4882a593Smuzhiyun 				u16 watermark);
443*4882a593Smuzhiyun int st_lsm6dsx_update_fifo(struct st_lsm6dsx_sensor *sensor, bool enable);
444*4882a593Smuzhiyun int st_lsm6dsx_flush_fifo(struct st_lsm6dsx_hw *hw);
445*4882a593Smuzhiyun int st_lsm6dsx_resume_fifo(struct st_lsm6dsx_hw *hw);
446*4882a593Smuzhiyun int st_lsm6dsx_read_fifo(struct st_lsm6dsx_hw *hw);
447*4882a593Smuzhiyun int st_lsm6dsx_read_tagged_fifo(struct st_lsm6dsx_hw *hw);
448*4882a593Smuzhiyun int st_lsm6dsx_check_odr(struct st_lsm6dsx_sensor *sensor, u32 odr, u8 *val);
449*4882a593Smuzhiyun int st_lsm6dsx_shub_probe(struct st_lsm6dsx_hw *hw, const char *name);
450*4882a593Smuzhiyun int st_lsm6dsx_shub_set_enable(struct st_lsm6dsx_sensor *sensor, bool enable);
451*4882a593Smuzhiyun int st_lsm6dsx_set_page(struct st_lsm6dsx_hw *hw, bool enable);
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun static inline int
st_lsm6dsx_update_bits_locked(struct st_lsm6dsx_hw * hw,unsigned int addr,unsigned int mask,unsigned int val)454*4882a593Smuzhiyun st_lsm6dsx_update_bits_locked(struct st_lsm6dsx_hw *hw, unsigned int addr,
455*4882a593Smuzhiyun 			      unsigned int mask, unsigned int val)
456*4882a593Smuzhiyun {
457*4882a593Smuzhiyun 	int err;
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	mutex_lock(&hw->page_lock);
460*4882a593Smuzhiyun 	err = regmap_update_bits(hw->regmap, addr, mask, val);
461*4882a593Smuzhiyun 	mutex_unlock(&hw->page_lock);
462*4882a593Smuzhiyun 
463*4882a593Smuzhiyun 	return err;
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun 
466*4882a593Smuzhiyun static inline int
st_lsm6dsx_read_locked(struct st_lsm6dsx_hw * hw,unsigned int addr,void * val,unsigned int len)467*4882a593Smuzhiyun st_lsm6dsx_read_locked(struct st_lsm6dsx_hw *hw, unsigned int addr,
468*4882a593Smuzhiyun 		       void *val, unsigned int len)
469*4882a593Smuzhiyun {
470*4882a593Smuzhiyun 	int err;
471*4882a593Smuzhiyun 
472*4882a593Smuzhiyun 	mutex_lock(&hw->page_lock);
473*4882a593Smuzhiyun 	err = regmap_bulk_read(hw->regmap, addr, val, len);
474*4882a593Smuzhiyun 	mutex_unlock(&hw->page_lock);
475*4882a593Smuzhiyun 
476*4882a593Smuzhiyun 	return err;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun static inline int
st_lsm6dsx_write_locked(struct st_lsm6dsx_hw * hw,unsigned int addr,unsigned int val)480*4882a593Smuzhiyun st_lsm6dsx_write_locked(struct st_lsm6dsx_hw *hw, unsigned int addr,
481*4882a593Smuzhiyun 			unsigned int val)
482*4882a593Smuzhiyun {
483*4882a593Smuzhiyun 	int err;
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun 	mutex_lock(&hw->page_lock);
486*4882a593Smuzhiyun 	err = regmap_write(hw->regmap, addr, val);
487*4882a593Smuzhiyun 	mutex_unlock(&hw->page_lock);
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun 	return err;
490*4882a593Smuzhiyun }
491*4882a593Smuzhiyun 
492*4882a593Smuzhiyun static inline const struct iio_mount_matrix *
st_lsm6dsx_get_mount_matrix(const struct iio_dev * iio_dev,const struct iio_chan_spec * chan)493*4882a593Smuzhiyun st_lsm6dsx_get_mount_matrix(const struct iio_dev *iio_dev,
494*4882a593Smuzhiyun 			    const struct iio_chan_spec *chan)
495*4882a593Smuzhiyun {
496*4882a593Smuzhiyun 	struct st_lsm6dsx_sensor *sensor = iio_priv(iio_dev);
497*4882a593Smuzhiyun 	struct st_lsm6dsx_hw *hw = sensor->hw;
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 	return &hw->orientation;
500*4882a593Smuzhiyun }
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun static const
503*4882a593Smuzhiyun struct iio_chan_spec_ext_info __maybe_unused st_lsm6dsx_accel_ext_info[] = {
504*4882a593Smuzhiyun 	IIO_MOUNT_MATRIX(IIO_SHARED_BY_ALL, st_lsm6dsx_get_mount_matrix),
505*4882a593Smuzhiyun 	{ }
506*4882a593Smuzhiyun };
507*4882a593Smuzhiyun 
508*4882a593Smuzhiyun #endif /* ST_LSM6DSX_H */
509