1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * ADIS16460 IMU driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2019 Analog Devices Inc.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/spi/spi.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <linux/iio/iio.h>
13*4882a593Smuzhiyun #include <linux/iio/imu/adis.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <linux/debugfs.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define ADIS16460_REG_FLASH_CNT 0x00
18*4882a593Smuzhiyun #define ADIS16460_REG_DIAG_STAT 0x02
19*4882a593Smuzhiyun #define ADIS16460_REG_X_GYRO_LOW 0x04
20*4882a593Smuzhiyun #define ADIS16460_REG_X_GYRO_OUT 0x06
21*4882a593Smuzhiyun #define ADIS16460_REG_Y_GYRO_LOW 0x08
22*4882a593Smuzhiyun #define ADIS16460_REG_Y_GYRO_OUT 0x0A
23*4882a593Smuzhiyun #define ADIS16460_REG_Z_GYRO_LOW 0x0C
24*4882a593Smuzhiyun #define ADIS16460_REG_Z_GYRO_OUT 0x0E
25*4882a593Smuzhiyun #define ADIS16460_REG_X_ACCL_LOW 0x10
26*4882a593Smuzhiyun #define ADIS16460_REG_X_ACCL_OUT 0x12
27*4882a593Smuzhiyun #define ADIS16460_REG_Y_ACCL_LOW 0x14
28*4882a593Smuzhiyun #define ADIS16460_REG_Y_ACCL_OUT 0x16
29*4882a593Smuzhiyun #define ADIS16460_REG_Z_ACCL_LOW 0x18
30*4882a593Smuzhiyun #define ADIS16460_REG_Z_ACCL_OUT 0x1A
31*4882a593Smuzhiyun #define ADIS16460_REG_SMPL_CNTR 0x1C
32*4882a593Smuzhiyun #define ADIS16460_REG_TEMP_OUT 0x1E
33*4882a593Smuzhiyun #define ADIS16460_REG_X_DELT_ANG 0x24
34*4882a593Smuzhiyun #define ADIS16460_REG_Y_DELT_ANG 0x26
35*4882a593Smuzhiyun #define ADIS16460_REG_Z_DELT_ANG 0x28
36*4882a593Smuzhiyun #define ADIS16460_REG_X_DELT_VEL 0x2A
37*4882a593Smuzhiyun #define ADIS16460_REG_Y_DELT_VEL 0x2C
38*4882a593Smuzhiyun #define ADIS16460_REG_Z_DELT_VEL 0x2E
39*4882a593Smuzhiyun #define ADIS16460_REG_MSC_CTRL 0x32
40*4882a593Smuzhiyun #define ADIS16460_REG_SYNC_SCAL 0x34
41*4882a593Smuzhiyun #define ADIS16460_REG_DEC_RATE 0x36
42*4882a593Smuzhiyun #define ADIS16460_REG_FLTR_CTRL 0x38
43*4882a593Smuzhiyun #define ADIS16460_REG_GLOB_CMD 0x3E
44*4882a593Smuzhiyun #define ADIS16460_REG_X_GYRO_OFF 0x40
45*4882a593Smuzhiyun #define ADIS16460_REG_Y_GYRO_OFF 0x42
46*4882a593Smuzhiyun #define ADIS16460_REG_Z_GYRO_OFF 0x44
47*4882a593Smuzhiyun #define ADIS16460_REG_X_ACCL_OFF 0x46
48*4882a593Smuzhiyun #define ADIS16460_REG_Y_ACCL_OFF 0x48
49*4882a593Smuzhiyun #define ADIS16460_REG_Z_ACCL_OFF 0x4A
50*4882a593Smuzhiyun #define ADIS16460_REG_LOT_ID1 0x52
51*4882a593Smuzhiyun #define ADIS16460_REG_LOT_ID2 0x54
52*4882a593Smuzhiyun #define ADIS16460_REG_PROD_ID 0x56
53*4882a593Smuzhiyun #define ADIS16460_REG_SERIAL_NUM 0x58
54*4882a593Smuzhiyun #define ADIS16460_REG_CAL_SGNTR 0x60
55*4882a593Smuzhiyun #define ADIS16460_REG_CAL_CRC 0x62
56*4882a593Smuzhiyun #define ADIS16460_REG_CODE_SGNTR 0x64
57*4882a593Smuzhiyun #define ADIS16460_REG_CODE_CRC 0x66
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun struct adis16460_chip_info {
60*4882a593Smuzhiyun unsigned int num_channels;
61*4882a593Smuzhiyun const struct iio_chan_spec *channels;
62*4882a593Smuzhiyun unsigned int gyro_max_val;
63*4882a593Smuzhiyun unsigned int gyro_max_scale;
64*4882a593Smuzhiyun unsigned int accel_max_val;
65*4882a593Smuzhiyun unsigned int accel_max_scale;
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun struct adis16460 {
69*4882a593Smuzhiyun const struct adis16460_chip_info *chip_info;
70*4882a593Smuzhiyun struct adis adis;
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
74*4882a593Smuzhiyun
adis16460_show_serial_number(void * arg,u64 * val)75*4882a593Smuzhiyun static int adis16460_show_serial_number(void *arg, u64 *val)
76*4882a593Smuzhiyun {
77*4882a593Smuzhiyun struct adis16460 *adis16460 = arg;
78*4882a593Smuzhiyun u16 serial;
79*4882a593Smuzhiyun int ret;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun ret = adis_read_reg_16(&adis16460->adis, ADIS16460_REG_SERIAL_NUM,
82*4882a593Smuzhiyun &serial);
83*4882a593Smuzhiyun if (ret)
84*4882a593Smuzhiyun return ret;
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun *val = serial;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun return 0;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun DEFINE_DEBUGFS_ATTRIBUTE(adis16460_serial_number_fops,
91*4882a593Smuzhiyun adis16460_show_serial_number, NULL, "0x%.4llx\n");
92*4882a593Smuzhiyun
adis16460_show_product_id(void * arg,u64 * val)93*4882a593Smuzhiyun static int adis16460_show_product_id(void *arg, u64 *val)
94*4882a593Smuzhiyun {
95*4882a593Smuzhiyun struct adis16460 *adis16460 = arg;
96*4882a593Smuzhiyun u16 prod_id;
97*4882a593Smuzhiyun int ret;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun ret = adis_read_reg_16(&adis16460->adis, ADIS16460_REG_PROD_ID,
100*4882a593Smuzhiyun &prod_id);
101*4882a593Smuzhiyun if (ret)
102*4882a593Smuzhiyun return ret;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun *val = prod_id;
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun return 0;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun DEFINE_DEBUGFS_ATTRIBUTE(adis16460_product_id_fops,
109*4882a593Smuzhiyun adis16460_show_product_id, NULL, "%llu\n");
110*4882a593Smuzhiyun
adis16460_show_flash_count(void * arg,u64 * val)111*4882a593Smuzhiyun static int adis16460_show_flash_count(void *arg, u64 *val)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun struct adis16460 *adis16460 = arg;
114*4882a593Smuzhiyun u32 flash_count;
115*4882a593Smuzhiyun int ret;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun ret = adis_read_reg_32(&adis16460->adis, ADIS16460_REG_FLASH_CNT,
118*4882a593Smuzhiyun &flash_count);
119*4882a593Smuzhiyun if (ret)
120*4882a593Smuzhiyun return ret;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun *val = flash_count;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun return 0;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun DEFINE_DEBUGFS_ATTRIBUTE(adis16460_flash_count_fops,
127*4882a593Smuzhiyun adis16460_show_flash_count, NULL, "%lld\n");
128*4882a593Smuzhiyun
adis16460_debugfs_init(struct iio_dev * indio_dev)129*4882a593Smuzhiyun static int adis16460_debugfs_init(struct iio_dev *indio_dev)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun struct adis16460 *adis16460 = iio_priv(indio_dev);
132*4882a593Smuzhiyun struct dentry *d = iio_get_debugfs_dentry(indio_dev);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun debugfs_create_file_unsafe("serial_number", 0400,
135*4882a593Smuzhiyun d, adis16460, &adis16460_serial_number_fops);
136*4882a593Smuzhiyun debugfs_create_file_unsafe("product_id", 0400,
137*4882a593Smuzhiyun d, adis16460, &adis16460_product_id_fops);
138*4882a593Smuzhiyun debugfs_create_file_unsafe("flash_count", 0400,
139*4882a593Smuzhiyun d, adis16460, &adis16460_flash_count_fops);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun return 0;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun #else
145*4882a593Smuzhiyun
adis16460_debugfs_init(struct iio_dev * indio_dev)146*4882a593Smuzhiyun static int adis16460_debugfs_init(struct iio_dev *indio_dev)
147*4882a593Smuzhiyun {
148*4882a593Smuzhiyun return 0;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun #endif
152*4882a593Smuzhiyun
adis16460_set_freq(struct iio_dev * indio_dev,int val,int val2)153*4882a593Smuzhiyun static int adis16460_set_freq(struct iio_dev *indio_dev, int val, int val2)
154*4882a593Smuzhiyun {
155*4882a593Smuzhiyun struct adis16460 *st = iio_priv(indio_dev);
156*4882a593Smuzhiyun int t;
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun t = val * 1000 + val2 / 1000;
159*4882a593Smuzhiyun if (t <= 0)
160*4882a593Smuzhiyun return -EINVAL;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun t = 2048000 / t;
163*4882a593Smuzhiyun if (t > 2048)
164*4882a593Smuzhiyun t = 2048;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun if (t != 0)
167*4882a593Smuzhiyun t--;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun return adis_write_reg_16(&st->adis, ADIS16460_REG_DEC_RATE, t);
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
adis16460_get_freq(struct iio_dev * indio_dev,int * val,int * val2)172*4882a593Smuzhiyun static int adis16460_get_freq(struct iio_dev *indio_dev, int *val, int *val2)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun struct adis16460 *st = iio_priv(indio_dev);
175*4882a593Smuzhiyun uint16_t t;
176*4882a593Smuzhiyun int ret;
177*4882a593Smuzhiyun unsigned int freq;
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun ret = adis_read_reg_16(&st->adis, ADIS16460_REG_DEC_RATE, &t);
180*4882a593Smuzhiyun if (ret)
181*4882a593Smuzhiyun return ret;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun freq = 2048000 / (t + 1);
184*4882a593Smuzhiyun *val = freq / 1000;
185*4882a593Smuzhiyun *val2 = (freq % 1000) * 1000;
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun return IIO_VAL_INT_PLUS_MICRO;
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
adis16460_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long info)190*4882a593Smuzhiyun static int adis16460_read_raw(struct iio_dev *indio_dev,
191*4882a593Smuzhiyun const struct iio_chan_spec *chan, int *val, int *val2, long info)
192*4882a593Smuzhiyun {
193*4882a593Smuzhiyun struct adis16460 *st = iio_priv(indio_dev);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun switch (info) {
196*4882a593Smuzhiyun case IIO_CHAN_INFO_RAW:
197*4882a593Smuzhiyun return adis_single_conversion(indio_dev, chan, 0, val);
198*4882a593Smuzhiyun case IIO_CHAN_INFO_SCALE:
199*4882a593Smuzhiyun switch (chan->type) {
200*4882a593Smuzhiyun case IIO_ANGL_VEL:
201*4882a593Smuzhiyun *val = st->chip_info->gyro_max_scale;
202*4882a593Smuzhiyun *val2 = st->chip_info->gyro_max_val;
203*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL;
204*4882a593Smuzhiyun case IIO_ACCEL:
205*4882a593Smuzhiyun *val = st->chip_info->accel_max_scale;
206*4882a593Smuzhiyun *val2 = st->chip_info->accel_max_val;
207*4882a593Smuzhiyun return IIO_VAL_FRACTIONAL;
208*4882a593Smuzhiyun case IIO_TEMP:
209*4882a593Smuzhiyun *val = 50; /* 50 milli degrees Celsius/LSB */
210*4882a593Smuzhiyun return IIO_VAL_INT;
211*4882a593Smuzhiyun default:
212*4882a593Smuzhiyun return -EINVAL;
213*4882a593Smuzhiyun }
214*4882a593Smuzhiyun case IIO_CHAN_INFO_OFFSET:
215*4882a593Smuzhiyun *val = 500; /* 25 degrees Celsius = 0x0000 */
216*4882a593Smuzhiyun return IIO_VAL_INT;
217*4882a593Smuzhiyun case IIO_CHAN_INFO_SAMP_FREQ:
218*4882a593Smuzhiyun return adis16460_get_freq(indio_dev, val, val2);
219*4882a593Smuzhiyun default:
220*4882a593Smuzhiyun return -EINVAL;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun
adis16460_write_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int val,int val2,long info)224*4882a593Smuzhiyun static int adis16460_write_raw(struct iio_dev *indio_dev,
225*4882a593Smuzhiyun const struct iio_chan_spec *chan, int val, int val2, long info)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun switch (info) {
228*4882a593Smuzhiyun case IIO_CHAN_INFO_SAMP_FREQ:
229*4882a593Smuzhiyun return adis16460_set_freq(indio_dev, val, val2);
230*4882a593Smuzhiyun default:
231*4882a593Smuzhiyun return -EINVAL;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun enum {
236*4882a593Smuzhiyun ADIS16460_SCAN_GYRO_X,
237*4882a593Smuzhiyun ADIS16460_SCAN_GYRO_Y,
238*4882a593Smuzhiyun ADIS16460_SCAN_GYRO_Z,
239*4882a593Smuzhiyun ADIS16460_SCAN_ACCEL_X,
240*4882a593Smuzhiyun ADIS16460_SCAN_ACCEL_Y,
241*4882a593Smuzhiyun ADIS16460_SCAN_ACCEL_Z,
242*4882a593Smuzhiyun ADIS16460_SCAN_TEMP,
243*4882a593Smuzhiyun };
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun #define ADIS16460_MOD_CHANNEL(_type, _mod, _address, _si, _bits) \
246*4882a593Smuzhiyun { \
247*4882a593Smuzhiyun .type = (_type), \
248*4882a593Smuzhiyun .modified = 1, \
249*4882a593Smuzhiyun .channel2 = (_mod), \
250*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
251*4882a593Smuzhiyun .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
252*4882a593Smuzhiyun .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
253*4882a593Smuzhiyun .address = (_address), \
254*4882a593Smuzhiyun .scan_index = (_si), \
255*4882a593Smuzhiyun .scan_type = { \
256*4882a593Smuzhiyun .sign = 's', \
257*4882a593Smuzhiyun .realbits = (_bits), \
258*4882a593Smuzhiyun .storagebits = (_bits), \
259*4882a593Smuzhiyun .endianness = IIO_BE, \
260*4882a593Smuzhiyun }, \
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun #define ADIS16460_GYRO_CHANNEL(_mod) \
264*4882a593Smuzhiyun ADIS16460_MOD_CHANNEL(IIO_ANGL_VEL, IIO_MOD_ ## _mod, \
265*4882a593Smuzhiyun ADIS16460_REG_ ## _mod ## _GYRO_LOW, ADIS16460_SCAN_GYRO_ ## _mod, \
266*4882a593Smuzhiyun 32)
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun #define ADIS16460_ACCEL_CHANNEL(_mod) \
269*4882a593Smuzhiyun ADIS16460_MOD_CHANNEL(IIO_ACCEL, IIO_MOD_ ## _mod, \
270*4882a593Smuzhiyun ADIS16460_REG_ ## _mod ## _ACCL_LOW, ADIS16460_SCAN_ACCEL_ ## _mod, \
271*4882a593Smuzhiyun 32)
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun #define ADIS16460_TEMP_CHANNEL() { \
274*4882a593Smuzhiyun .type = IIO_TEMP, \
275*4882a593Smuzhiyun .indexed = 1, \
276*4882a593Smuzhiyun .channel = 0, \
277*4882a593Smuzhiyun .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
278*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_SCALE) | \
279*4882a593Smuzhiyun BIT(IIO_CHAN_INFO_OFFSET), \
280*4882a593Smuzhiyun .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
281*4882a593Smuzhiyun .address = ADIS16460_REG_TEMP_OUT, \
282*4882a593Smuzhiyun .scan_index = ADIS16460_SCAN_TEMP, \
283*4882a593Smuzhiyun .scan_type = { \
284*4882a593Smuzhiyun .sign = 's', \
285*4882a593Smuzhiyun .realbits = 16, \
286*4882a593Smuzhiyun .storagebits = 16, \
287*4882a593Smuzhiyun .endianness = IIO_BE, \
288*4882a593Smuzhiyun }, \
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun static const struct iio_chan_spec adis16460_channels[] = {
292*4882a593Smuzhiyun ADIS16460_GYRO_CHANNEL(X),
293*4882a593Smuzhiyun ADIS16460_GYRO_CHANNEL(Y),
294*4882a593Smuzhiyun ADIS16460_GYRO_CHANNEL(Z),
295*4882a593Smuzhiyun ADIS16460_ACCEL_CHANNEL(X),
296*4882a593Smuzhiyun ADIS16460_ACCEL_CHANNEL(Y),
297*4882a593Smuzhiyun ADIS16460_ACCEL_CHANNEL(Z),
298*4882a593Smuzhiyun ADIS16460_TEMP_CHANNEL(),
299*4882a593Smuzhiyun IIO_CHAN_SOFT_TIMESTAMP(7)
300*4882a593Smuzhiyun };
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun static const struct adis16460_chip_info adis16460_chip_info = {
303*4882a593Smuzhiyun .channels = adis16460_channels,
304*4882a593Smuzhiyun .num_channels = ARRAY_SIZE(adis16460_channels),
305*4882a593Smuzhiyun /*
306*4882a593Smuzhiyun * storing the value in rad/degree and the scale in degree
307*4882a593Smuzhiyun * gives us the result in rad and better precession than
308*4882a593Smuzhiyun * storing the scale directly in rad.
309*4882a593Smuzhiyun */
310*4882a593Smuzhiyun .gyro_max_val = IIO_RAD_TO_DEGREE(200 << 16),
311*4882a593Smuzhiyun .gyro_max_scale = 1,
312*4882a593Smuzhiyun .accel_max_val = IIO_M_S_2_TO_G(20000 << 16),
313*4882a593Smuzhiyun .accel_max_scale = 5,
314*4882a593Smuzhiyun };
315*4882a593Smuzhiyun
316*4882a593Smuzhiyun static const struct iio_info adis16460_info = {
317*4882a593Smuzhiyun .read_raw = &adis16460_read_raw,
318*4882a593Smuzhiyun .write_raw = &adis16460_write_raw,
319*4882a593Smuzhiyun .update_scan_mode = adis_update_scan_mode,
320*4882a593Smuzhiyun .debugfs_reg_access = adis_debugfs_reg_access,
321*4882a593Smuzhiyun };
322*4882a593Smuzhiyun
adis16460_enable_irq(struct adis * adis,bool enable)323*4882a593Smuzhiyun static int adis16460_enable_irq(struct adis *adis, bool enable)
324*4882a593Smuzhiyun {
325*4882a593Smuzhiyun /*
326*4882a593Smuzhiyun * There is no way to gate the data-ready signal internally inside the
327*4882a593Smuzhiyun * ADIS16460 :(
328*4882a593Smuzhiyun */
329*4882a593Smuzhiyun if (enable)
330*4882a593Smuzhiyun enable_irq(adis->spi->irq);
331*4882a593Smuzhiyun else
332*4882a593Smuzhiyun disable_irq(adis->spi->irq);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun return 0;
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun #define ADIS16460_DIAG_STAT_IN_CLK_OOS 7
338*4882a593Smuzhiyun #define ADIS16460_DIAG_STAT_FLASH_MEM 6
339*4882a593Smuzhiyun #define ADIS16460_DIAG_STAT_SELF_TEST 5
340*4882a593Smuzhiyun #define ADIS16460_DIAG_STAT_OVERRANGE 4
341*4882a593Smuzhiyun #define ADIS16460_DIAG_STAT_SPI_COMM 3
342*4882a593Smuzhiyun #define ADIS16460_DIAG_STAT_FLASH_UPT 2
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun static const char * const adis16460_status_error_msgs[] = {
345*4882a593Smuzhiyun [ADIS16460_DIAG_STAT_IN_CLK_OOS] = "Input clock out of sync",
346*4882a593Smuzhiyun [ADIS16460_DIAG_STAT_FLASH_MEM] = "Flash memory failure",
347*4882a593Smuzhiyun [ADIS16460_DIAG_STAT_SELF_TEST] = "Self test diagnostic failure",
348*4882a593Smuzhiyun [ADIS16460_DIAG_STAT_OVERRANGE] = "Sensor overrange",
349*4882a593Smuzhiyun [ADIS16460_DIAG_STAT_SPI_COMM] = "SPI communication failure",
350*4882a593Smuzhiyun [ADIS16460_DIAG_STAT_FLASH_UPT] = "Flash update failure",
351*4882a593Smuzhiyun };
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun static const struct adis_timeout adis16460_timeouts = {
354*4882a593Smuzhiyun .reset_ms = 225,
355*4882a593Smuzhiyun .sw_reset_ms = 225,
356*4882a593Smuzhiyun .self_test_ms = 10,
357*4882a593Smuzhiyun };
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun static const struct adis_data adis16460_data = {
360*4882a593Smuzhiyun .diag_stat_reg = ADIS16460_REG_DIAG_STAT,
361*4882a593Smuzhiyun .glob_cmd_reg = ADIS16460_REG_GLOB_CMD,
362*4882a593Smuzhiyun .prod_id_reg = ADIS16460_REG_PROD_ID,
363*4882a593Smuzhiyun .prod_id = 16460,
364*4882a593Smuzhiyun .self_test_mask = BIT(2),
365*4882a593Smuzhiyun .self_test_reg = ADIS16460_REG_GLOB_CMD,
366*4882a593Smuzhiyun .has_paging = false,
367*4882a593Smuzhiyun .read_delay = 5,
368*4882a593Smuzhiyun .write_delay = 5,
369*4882a593Smuzhiyun .cs_change_delay = 16,
370*4882a593Smuzhiyun .status_error_msgs = adis16460_status_error_msgs,
371*4882a593Smuzhiyun .status_error_mask = BIT(ADIS16460_DIAG_STAT_IN_CLK_OOS) |
372*4882a593Smuzhiyun BIT(ADIS16460_DIAG_STAT_FLASH_MEM) |
373*4882a593Smuzhiyun BIT(ADIS16460_DIAG_STAT_SELF_TEST) |
374*4882a593Smuzhiyun BIT(ADIS16460_DIAG_STAT_OVERRANGE) |
375*4882a593Smuzhiyun BIT(ADIS16460_DIAG_STAT_SPI_COMM) |
376*4882a593Smuzhiyun BIT(ADIS16460_DIAG_STAT_FLASH_UPT),
377*4882a593Smuzhiyun .enable_irq = adis16460_enable_irq,
378*4882a593Smuzhiyun .timeouts = &adis16460_timeouts,
379*4882a593Smuzhiyun };
380*4882a593Smuzhiyun
adis16460_probe(struct spi_device * spi)381*4882a593Smuzhiyun static int adis16460_probe(struct spi_device *spi)
382*4882a593Smuzhiyun {
383*4882a593Smuzhiyun struct iio_dev *indio_dev;
384*4882a593Smuzhiyun struct adis16460 *st;
385*4882a593Smuzhiyun int ret;
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
388*4882a593Smuzhiyun if (indio_dev == NULL)
389*4882a593Smuzhiyun return -ENOMEM;
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun spi_set_drvdata(spi, indio_dev);
392*4882a593Smuzhiyun
393*4882a593Smuzhiyun st = iio_priv(indio_dev);
394*4882a593Smuzhiyun
395*4882a593Smuzhiyun st->chip_info = &adis16460_chip_info;
396*4882a593Smuzhiyun indio_dev->name = spi_get_device_id(spi)->name;
397*4882a593Smuzhiyun indio_dev->channels = st->chip_info->channels;
398*4882a593Smuzhiyun indio_dev->num_channels = st->chip_info->num_channels;
399*4882a593Smuzhiyun indio_dev->info = &adis16460_info;
400*4882a593Smuzhiyun indio_dev->modes = INDIO_DIRECT_MODE;
401*4882a593Smuzhiyun
402*4882a593Smuzhiyun ret = adis_init(&st->adis, indio_dev, spi, &adis16460_data);
403*4882a593Smuzhiyun if (ret)
404*4882a593Smuzhiyun return ret;
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun ret = devm_adis_setup_buffer_and_trigger(&st->adis, indio_dev, NULL);
407*4882a593Smuzhiyun if (ret)
408*4882a593Smuzhiyun return ret;
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun adis16460_enable_irq(&st->adis, 0);
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun ret = __adis_initial_startup(&st->adis);
413*4882a593Smuzhiyun if (ret)
414*4882a593Smuzhiyun return ret;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun ret = devm_iio_device_register(&spi->dev, indio_dev);
417*4882a593Smuzhiyun if (ret)
418*4882a593Smuzhiyun return ret;
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun adis16460_debugfs_init(indio_dev);
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun return 0;
423*4882a593Smuzhiyun }
424*4882a593Smuzhiyun
425*4882a593Smuzhiyun static const struct spi_device_id adis16460_ids[] = {
426*4882a593Smuzhiyun { "adis16460", 0 },
427*4882a593Smuzhiyun {}
428*4882a593Smuzhiyun };
429*4882a593Smuzhiyun MODULE_DEVICE_TABLE(spi, adis16460_ids);
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun static const struct of_device_id adis16460_of_match[] = {
432*4882a593Smuzhiyun { .compatible = "adi,adis16460" },
433*4882a593Smuzhiyun {}
434*4882a593Smuzhiyun };
435*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, adis16460_of_match);
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun static struct spi_driver adis16460_driver = {
438*4882a593Smuzhiyun .driver = {
439*4882a593Smuzhiyun .name = "adis16460",
440*4882a593Smuzhiyun .of_match_table = adis16460_of_match,
441*4882a593Smuzhiyun },
442*4882a593Smuzhiyun .id_table = adis16460_ids,
443*4882a593Smuzhiyun .probe = adis16460_probe,
444*4882a593Smuzhiyun };
445*4882a593Smuzhiyun module_spi_driver(adis16460_driver);
446*4882a593Smuzhiyun
447*4882a593Smuzhiyun MODULE_AUTHOR("Dragos Bogdan <dragos.bogdan@analog.com>");
448*4882a593Smuzhiyun MODULE_DESCRIPTION("Analog Devices ADIS16460 IMU driver");
449*4882a593Smuzhiyun MODULE_LICENSE("GPL");
450